Relevant bibliographies by topics / Analog and RF

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Analog and RF'

Author: Grafiati
Published: 4 June 2021
Last updated: 18 February 2022

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Journal articles on the topic "Analog and RF"

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OKADA, Kenichi. "Digitally Assisted Analog and RF Circuits." IEICE Transactions on Electronics E98.C, no. 6 (2015): 461–70. http://dx.doi.org/10.1587/transele.e98.c.461.

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Mostafanezhad, Isar, and Olga Boric-Lubecke. "An RF Based Analog Linear Demodulator." IEEE Microwave and Wireless Components Letters 21, no. 7 (July 2011): 392–94. http://dx.doi.org/10.1109/lmwc.2011.2154318.

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Musayev, Javid, and Antonio Liscidini. "A Quantized Analog RF Front End." IEEE Journal of Solid-State Circuits 54, no. 7 (July 2019): 1929–40. http://dx.doi.org/10.1109/jssc.2019.2914576.

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Muhammad, Khurram, Thomas Murphy, and Robert Bogdan Staszewski. "Verification of Digital RF Processors: RF, Analog, Baseband, and Software." IEEE Journal of Solid-State Circuits 42, no. 5 (May 2007): 992–1002. http://dx.doi.org/10.1109/jssc.2007.894327.

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Deng, Jun, Liang Zhou, Xiao Zong Huang, Xu Huang, Yu Jing Li, Lin Tao Liu, and Yi Tao. "Study of System Modeling and Simulation Based on Mixed Domain for Analog-Digital Mixed SoC." Applied Mechanics and Materials 423-426 (September 2013): 2688–92. http://dx.doi.org/10.4028/www.scientific.net/amm.423-426.2688.

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The design of digital-analog mixed SoC involves RF/analog and digital domains, how to effectively improve the design reliability and to reduce the development cycles has become a research hotspot. This paper establishes the appropriate behavioral models of RF / analog / digital IP modules, and carries out the behavioral simulation based on the built mixed-domain simulation platform and the behavioral libraries of RF/analog/digital IP module, which enhances the reliability and stability of mixed SoC design, and reduces the design cycle. Those explorations may be helpful to the designers of digital-analog mixed SoC.
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OKUBO, NAOFUMI. "Notice the Analog Circuit Technology. RF Systems Need Analog Circuit Technologies." Journal of the Institute of Electrical Engineers of Japan 118, no. 7/8 (1998): 422–25. http://dx.doi.org/10.1541/ieejjournal.118.422.

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Bruines, Joop J. P. "Process outlook for analog and RF applications." Microelectronic Engineering 54, no. 1-2 (December 2000): 35–48. http://dx.doi.org/10.1016/s0167-9317(00)80057-x.

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Cooklev, Todor, Robert Normoyle, and David Clendenen. "The VITA 49 Analog RF-Digital Interface." IEEE Circuits and Systems Magazine 12, no. 4 (2012): 21–32. http://dx.doi.org/10.1109/mcas.2012.2221520.

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Lim, Tao Chuan, Emilie Bernard, Olivier Rozeau, Thomas Ernst, Bernard Guillaumot, Nathalie Vulliet, Christel Buj-Dufournet, et al. "Analog/RF Performance of Multichannel SOI MOSFET." IEEE Transactions on Electron Devices 56, no. 7 (July 2009): 1473–82. http://dx.doi.org/10.1109/ted.2009.2021438.

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Wang, Yiqi, Mengxin Liu, Jinshun Bi, and Zhengsheng Han. "PDSOI DTMOS for analog and RF application." Journal of Semiconductors 32, no. 5 (May 2011): 054004. http://dx.doi.org/10.1088/1674-4926/32/5/054004.

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Dissertations / Theses on the topic "Analog and RF"

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Ayari, Haithem. "Indirect Analog / RF IC Testing : Confidence & Robusteness improvments." Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2013. http://tel.archives-ouvertes.fr/tel-00998677.

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The conventional approach for testing RF circuits is specification-based testing, which involves verifying sequentially all specification requirements that are promised in the data sheet. This approach is a long-time effective testapproach but nowadays suffers from significant drawbacks.First, it requires generation and capture of test signals at the DUT operating frequency. As the operational frequencies of DUT are increasing, it becomes difficult to manage signal generation and capture using ATE. As a consequence, there is a need of expensive and specialized equipment. In addition,as conventional tests target several parameters, there is a need of several data captures and multiple test configurations. As a consequence, by adding settling time between each test and test application time, the whole test time becomes very long, and the test board very complex.Another challenge regarding RF circuit testing is wafer-level testing. Indeed, the implementation of specification-based tests at wafer level is extremely difficult due to probing issues and high parasitic effects on the test interface.Moreover, multi-site testing is usually not an option due to the small count of available RF test resources, which decreases test throughput. Hence, the current practice is often to verify the device specifications only after packaging.The problem with this solution is that defective dies are identified late in the manufacturing flow, which leads to packaging loss and decreases the global yield of the process.In order to reduce production costs, there is therefore a need to develop test solutions applicable at wafer level, so that faulty circuits can be removed very early in the production flow. This is particularly important for dies designed to be integrated in Systems-In-Package (SIP).In this context, a promising solution is to develop indirect test methods. Basically, it consists in using DUT signatures to non-conventional stimuli to predict the result of conventional tests. The underlying idea is to learn during an initial phase the unknown dependency between simple measurements and conventional tests. This dependency can then be modeled through regression functions. During the testing phase, only the indirect measurements are performed and specifications are predicted using the regression model built in the learning phase.Our work has been focused on two main directions. First, we have explored the implementation of the alternate test method based on DC measurements for RF circuits and we have proposed a methodology to select the most appropriateset of DC parameters. Results from two test vehicles (a LNA using electrical simulations and a PA using real production data) indicate that the proposed methodology allows precise estimation of the DUT performances while minimizing the number of DC measurements to be carried out.Second, we have proposed a novel implementation of the alternate test strategy in order to improve confidence in alternate test predictions and to overcome the effect of limited training set sizes. The idea is to exploit model redundancy in order to identify, during the production testing phase, devices with suspect predictions; these devices are then are removed from the alternate test tierand directed to a second tier where further testing may apply.
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Voorakaranam, Ramakrishna. "Signature based testing of analog and RF circuits." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15009.

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Cahill, James P. "Rayleigh-Scattering-Induced Noise in Analog RF-Photonic Links." Thesis, University of Maryland, Baltimore County, 2015. http://pqdtopen.proquest.com/#viewpdf?dispub=3707242.

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Analog RF-photonic links hold the potential to increase the precision of time and frequency synchronization in commercial applications by orders of magnitude. However, current RF-photonic links that are used for synchronization must suppress optical-fiber-induced noise by using bi-directional active feedback schemes, in which light must travel through the optical fiber in both directions. These schemes are incompatible with most existing fiber-optic networks. Unless this noise can be suppressed using different methods, RF-photonic time and frequency synchronization will remain accessible only to the research community. As a first step towards identifying alternate means of suppressing the optical-fiber-induced noise, this dissertation presents an extensive experimental characterization and limited theoretical discussion of the dominant optical-intensity and RF-phase noise source in a laboratory setting, where environmental fluctuations are small. The experimental results indicate that the optical-fiber-induced RF-phase noise and optical-intensity noise are caused by the same physical mechanism. The experimental results demonstrate that this mechanism is related to the laser-phase noise but not the laser intensity noise. The bandwidth of the optical-fiber-induced noise depends on the optical-fiber length for lasers with low phase noise, while for lasers with high phase noise, the bandwidth is constant. I demonstrate that the optical-intensity and RF-phase noise can be mitigated by dithering the laser frequency. Based on these results, I hypothesize that interference from Rayleigh scattering is the underlying mechanism of the optical-intensity and RF-phase noise. Prior theoretical work, carried out with high phase noise lasers, predicts that the noise induced by this process will have a bandwidth that is proportional to the laser linewidth and that is constant with respect to the optical-fiber length, for lasers with high-phase noise, which is consistent with the experimental results. I derive a simple model that is valid for low-phase-noise lasers. I compare this model with the experimental results and find that it matches the optical-fiber-length-dependent bandwidth that is measured for low-phase-noise lasers.

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Bhattacharya, Sambuddha. "Template-driven parasitic-aware optimization of analog/RF IC layouts /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6121.

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Jangkrajarng, Nuttorn. "Analog/RF VLSI layout generation : layout retargeting via symbolic template /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6084.

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Tang, Hongxia. "Study of Design for Reliability of RF and Analog Circuits." Doctoral diss., University of Central Florida, 2012. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5525.

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Due to continued device dimensions scaling, CMOS transistors in the nanometer regime have resulted in major reliability and variability challenges. Reliability issues such as channel hot electron injection, gate dielectric breakdown, and negative bias temperature instability (NBTI) need to be accounted for in the design of robust RF circuits. In addition, process variations in the nanoscale CMOS transistors are another major concern in today's circuits design. An adaptive gate-source biasing scheme to improve the RF circuit reliability is presented in this work. The adaptive method automatically adjusts the gate-source voltage to compensate the reduction in drain current subjected to various device reliability mechanisms. A class-AB RF power amplifier shows that the use of a source resistance makes the power-added efficiency robust against threshold voltage and mobility variations, while the use of a source inductance is more reliable for the input third-order intercept point. A RF power amplifier with adaptive gate biasing is proposed to improve the circuit device reliability degradation and process variation. The performances of the power amplifier with adaptive gate biasing are compared with those of the power amplifier without adaptive gate biasing technique. The adaptive gate biasing makes the power amplifier more resilient to process variations as well as the device aging such as mobility and threshold voltage degradation. Injection locked voltage-controlled oscillators (VCOs) have been examined. The VCOs are implemented using TSMC 0.18 μm mixed-signal CMOS technology. The injection locked oscillators have improved phase noise performance than free running oscillators. A differential Clapp-VCO has been designed and fabricated for the evaluation of hot electron reliability. The differential Clapp-VCO is formed using cross-coupled nMOS transistors, on-chip transformers/inductors, and voltage-controlled capacitors. The experimental data demonstrate that the hot carrier damage increases the oscillation frequency and degrades the phase noise of Clapp-VCO. A p-channel transistor only VCO has been designed for low phase noise. The simulation results show that the phase noise degrades after NBTI stress at elevated temperature. This is due to increased interface states after NBTI stress. The process variability has also been evaluated.
ID: 031001466; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Adviser: Jiann S. Yuan.; Title from PDF title page (viewed July 10, 2013).; Thesis (Ph.D.)--University of Central Florida, 2012.; Includes bibliographical references (p. 101-111).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
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Banerjee, Aritra. "Design of digitally assisted adaptive analog and RF circuits and systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/52919.

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With more and more integration of analog and RF circuits in scaled CMOS technologies, process variation is playing a critical role which makes it difficult to achieve all the performance specifications across all the process corners. Moreover, at scaled technology nodes, due to lower voltage and current handling capabilities of the devices, they suffer from reliability issues that reduce the overall lifetime of the system. Finally, traditional static style of designing analog and RF circuits does not result in optimal performance of the system. A new design paradigm is emerging toward digitally assisted analog and RF circuits and systems aiming to leverage digital correction and calibration techniques to detect and compensate for the manufacturing imperfections and improve the analog and RF performance offering a high level of integration. The objective of the proposed research is to design digital friendly and performance tunable adaptive analog/RF circuits and systems with digital enhancement techniques for higher performance, better process variation tolerance, and more reliable operation and developing strategy for testing the proposed adaptive systems. An adaptation framework is developed for process variation tolerant RF systems which has two parts – optimized test stimulus driven diagnosis of individual modules and power optimal system level tuning. Another direct tuning approach is developed and demonstrated on a carbon nanotube based analog circuit. An adaptive switched mode power amplifier is designed which is more digital-intensive in nature and has higher efficiency, improved reliability and better process resiliency. Finally, a testing strategy for adaptive RF systems is shown which reduces test time and test cost compared to traditional testing.
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Svensson, Gustaf. "Analog Baseband Implementation of a Wideband Observation Receiver for RF Applications." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-131081.

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During the thesis, a two-staged analog baseband circuit incorporating a passive analog filter and a wideband voltage amplifier were successfully designed, implemented in an IC mask layout in a 65nm CMOS technology, and joined with a previously designed analog front-end design to form a wideband observation receiver. The baseband circuit is capable of receiving an IF bandwidth up to 990MHz produced by the analog front-end using low-side injection. The final circuit shows high IMD3 of at least 90 dBc. The voltage amplifier delivers a voltage amplification of 15 dB with around 0.08 dB amplitude precision over the bandwidth, while the passive filter is capable of a passband amplitude precision of 0.67 dB over the bandwidth, while effectively suppress signal images created by the mixer with at least 60 dBc. Both stages were realized in an IC mask layout, in addition, the filter layout were simulated using an EM simulator.
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Cortes, Fernando da Rocha Paixao. "Analysis, design and implementation of analog/RF blocks suitable for a multi-band analog interface for CMOS SOCs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2008. http://hdl.handle.net/10183/13132.

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O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico.
The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.
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Bhattacharya, Soumendu. "Alternate Testing of Analog and RF Systems using Extracted Test Response Features." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7200.

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Testing is an integral part of modern semiconductor industry. The necessity of test is evident, especially for low-yielding processes, to ensure Quality of Service (QoS) to the customers. Testing is a major contributing factor to the total manufacturing cost of analog/RF systems, with test cost estimated to be up to 40% of the overall cost. Due to the lack of low-cost, high-speed testers and other test instrumentation that can be used in a production line, low-cost testing of high-frequency devices/systems is a tremendous challenge to semiconductor test community. Also, simulation times being very high for such systems, the only possible way to generate reliable tests for RF systems is by performing direct measurements on hardware. At the same time, inserting test points for such circuits while maintaining signal integrity is a difficult task to achieve. The proposed research develops a test strategy to reduce overall test cost for RF circuits. A built-in-test (BIT) approach using sensors is proposed for this purpose, which are designed into high-frequency circuits. The work develops algorithms for selecting optimal test access points, and the stimulus for testing the DUT. The test stimulus can be generated on-chip, through efficient design reuse or using custom built circuits. The test responses are captured and analyzed by on-chip sensors, which are custom designed to extract test response features. The sensors, which have low silicon area overhead, output either DC or low frequency test response signals and are compatible to low-speed testers; hence are low-cost. The specifications of the system are computed using a set of nonlinear models developed using the alternate test methodology. The whole approach has been applied to a RF receiver at 1 GHz, used as a test vehicle to prove the feasibility of the proposed approach. Finally, the method is verified through measurements made on a large number of devices, similar to an industrial production test situation. The proposed method using sensors estimated system-level as well as device-level specifications very accurately in the emulated production test environment with a significantly smaller test cost than existing production tests.
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Books on the topic "Analog and RF"

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Talbot, Daniel B. Practical Analog and RF Electronics. First edition. | Boca Raton : CRC Press, 2021.: CRC Press, 2020. http://dx.doi.org/10.1201/9781003088547.

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Hickman, Ian. Hickman's analog and RF circuits. Oxford, [England]: Newnes, 1998.

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Substrate noise coupling in analog/RF circuits. Boston: Artech House, 2010.

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CMOS nanoelectronics: Analog and RF VLSI circuits. New York: McGraw-Hill, 2011.

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Fakhfakh, Mourad. Analog/RF and Mixed-Signal Circuit Systematic Design. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013.

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Smaini, Lydi. RF Analog Impairments Modeling for Communication Systems Simulation. Chichester, UK: John Wiley & Sons, Ltd, 2012. http://dx.doi.org/10.1002/9781118438046.

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GRABINSKI, WLADYSLAW, BART NAUWELAERS, and DOMINIQUE SCHREURS, eds. TRANSISTOR LEVEL MODELING FOR ANALOG/RF IC DESIGN. Dordrecht: Springer Netherlands, 2006. http://dx.doi.org/10.1007/1-4020-4556-5.

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Fakhfakh, Mourad, Esteban Tlelo-Cuautle, and Rafael Castro-Lopez, eds. Analog/RF and Mixed-Signal Circuit Systematic Design. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-36329-0.

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Device modeling for analog and RF CMOS circuit design. Chichester: John Wiley & Sons, 2004.

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Ytterdal, Trond, Yuhua Cheng, and Tor A. Fjeldly. Device Modeling for Analog and RF CMOS Circuit Design. Chichester, UK: John Wiley & Sons, Ltd, 2003. http://dx.doi.org/10.1002/0470863803.

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Book chapters on the topic "Analog and RF"

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El-Kareh, Badih, and Lou N. Hutter. "Analog/RF CMOS." In Silicon Analog Components, 221–306. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-15085-3_6.

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El-Kareh, Badih, and Lou N. Hutter. "Analog/RF CMOS." In Silicon Analog Components, 205–74. New York, NY: Springer New York, 2015. http://dx.doi.org/10.1007/978-1-4939-2751-7_6.

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Laflere, Willem, Michiel Steyaert, and Jan Craninckx. "Switched RF Transmitters." In Analog Circuit Design, 145–62. Dordrecht: Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8263-4_8.

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Tiemeijer, L. F., L. M. F. de Maaijer, R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen. "RF CMOS Modelling." In Analog Circuit Design, 129–49. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-3047-0_6.

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Klaassen, D. B. M., B. Nauta, and R. R. J. Vanoppen. "RF modelling of MOSFETs." In Analog Circuit Design, 3–24. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4613-1443-1_1.

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Pulsford, Nicolas J. "Passive Integrated RF Filters." In Analog Circuit Design, 343–51. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-3047-0_16.

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Crols, Jan. "Power Management in RF Circuits." In Analog Circuit Design, 225–45. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4020-2805-2_11.

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Brianti, F., G. Chien, T. Cho, S. Lo, S. Mehta, J. Ou, J. Rudell, T. Weigandt, J. Weldon, and P. Gray. "High Integration CMOS RF Transceivers." In Analog Circuit Design, 25–38. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4613-1443-1_2.

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Song, Bang-Sup. "RF Circuits." In System-level Techniques for Analog Performance Enhancement, 165–94. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-27921-3_6.

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Leblebici, Duran, and Yusuf Leblebici. "RF Oscillators." In Fundamentals of High Frequency CMOS Analog Integrated Circuits, 269–92. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-63658-6_6.

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Conference papers on the topic "Analog and RF"

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Henshaw, B. "Design of an RF transceiver." In IEE Colloquium Analog Signal Processing. IEE, 1998. http://dx.doi.org/10.1049/ic:19980854.

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Marshall, Andrew. "RF, analog design I." In 2016 29th IEEE International System-on-Chip Conference (SOCC). IEEE, 2016. http://dx.doi.org/10.1109/socc.2016.7905424.

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Wang, Haibo. "RF, analog design II." In 2016 29th IEEE International System-on-Chip Conference (SOCC). IEEE, 2016. http://dx.doi.org/10.1109/socc.2016.7905485.

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Moult, L., and J. E. Chen. "The K-model: RF IC modelling for communication systems simulation." In IEE Colloquium Analog Signal Processing. IEE, 1998. http://dx.doi.org/10.1049/ic:19980853.

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Srinivas, M. B. "T2A: Analog and RF circuits." In 2017 30th IEEE International System-on-Chip Conference (SOCC). IEEE, 2017. http://dx.doi.org/10.1109/socc.2017.8226050.

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Ghosh, Dipankar, Mukta Singh Parihar, G. Alastair Armstrong, and Abhinav Kranti. "Low power nanoscale RF/analog MOSFETs." In 2012 IEEE 12th International Conference on Nanotechnology (IEEE-NANO). IEEE, 2012. http://dx.doi.org/10.1109/nano.2012.6321973.

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"SE1 Digitally Enhanced Analog & RF." In 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. IEEE, 2007. http://dx.doi.org/10.1109/isscc.2007.373570.

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"SESSION 10 - Analog/RF Devices I." In Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. IEEE, 2004. http://dx.doi.org/10.1109/vlsit.2004.1345413.

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"SESSION 21- Analog/RF Devices II." In Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. IEEE, 2004. http://dx.doi.org/10.1109/vlsit.2004.1345488.

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Vandooren, A., B. Parvais, L. Witters, A. Walke, A. Vais, C. Merckling, D. Lin, et al. "3D technologies for analog/RF applications." In 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2017. http://dx.doi.org/10.1109/s3s.2017.8308746.

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Reports on the topic "Analog and RF"

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Hovater, C., and J. Fugitt. Analog techniques in CEBAF'S RF control system. Office of Scientific and Technical Information (OSTI), January 1989. http://dx.doi.org/10.2172/6042928.

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