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Ayari, Haithem. "Indirect Analog / RF IC Testing : Confidence & Robusteness improvments." Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2013. http://tel.archives-ouvertes.fr/tel-00998677.
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The conventional approach for testing RF circuits is specification-based testing, which involves verifying sequentially all specification requirements that are promised in the data sheet. This approach is a long-time effective testapproach but nowadays suffers from significant drawbacks.First, it requires generation and capture of test signals at the DUT operating frequency. As the operational frequencies of DUT are increasing, it becomes difficult to manage signal generation and capture using ATE. As a consequence, there is a need of expensive and specialized equipment. In addition,as conventional tests target several parameters, there is a need of several data captures and multiple test configurations. As a consequence, by adding settling time between each test and test application time, the whole test time becomes very long, and the test board very complex.Another challenge regarding RF circuit testing is wafer-level testing. Indeed, the implementation of specification-based tests at wafer level is extremely difficult due to probing issues and high parasitic effects on the test interface.Moreover, multi-site testing is usually not an option due to the small count of available RF test resources, which decreases test throughput. Hence, the current practice is often to verify the device specifications only after packaging.The problem with this solution is that defective dies are identified late in the manufacturing flow, which leads to packaging loss and decreases the global yield of the process.In order to reduce production costs, there is therefore a need to develop test solutions applicable at wafer level, so that faulty circuits can be removed very early in the production flow. This is particularly important for dies designed to be integrated in Systems-In-Package (SIP).In this context, a promising solution is to develop indirect test methods. Basically, it consists in using DUT signatures to non-conventional stimuli to predict the result of conventional tests. The underlying idea is to learn during an initial phase the unknown dependency between simple measurements and conventional tests. This dependency can then be modeled through regression functions. During the testing phase, only the indirect measurements are performed and specifications are predicted using the regression model built in the learning phase.Our work has been focused on two main directions. First, we have explored the implementation of the alternate test method based on DC measurements for RF circuits and we have proposed a methodology to select the most appropriateset of DC parameters. Results from two test vehicles (a LNA using electrical simulations and a PA using real production data) indicate that the proposed methodology allows precise estimation of the DUT performances while minimizing the number of DC measurements to be carried out.Second, we have proposed a novel implementation of the alternate test strategy in order to improve confidence in alternate test predictions and to overcome the effect of limited training set sizes. The idea is to exploit model redundancy in order to identify, during the production testing phase, devices with suspect predictions; these devices are then are removed from the alternate test tierand directed to a second tier where further testing may apply.
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Voorakaranam, Ramakrishna. "Signature based testing of analog and RF circuits." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15009.
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Cahill, James P. "Rayleigh-Scattering-Induced Noise in Analog RF-Photonic Links." Thesis, University of Maryland, Baltimore County, 2015. http://pqdtopen.proquest.com/#viewpdf?dispub=3707242.
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Analog RF-photonic links hold the potential to increase the precision of time and frequency synchronization in commercial applications by orders of magnitude. However, current RF-photonic links that are used for synchronization must suppress optical-fiber-induced noise by using bi-directional active feedback schemes, in which light must travel through the optical fiber in both directions. These schemes are incompatible with most existing fiber-optic networks. Unless this noise can be suppressed using different methods, RF-photonic time and frequency synchronization will remain accessible only to the research community. As a first step towards identifying alternate means of suppressing the optical-fiber-induced noise, this dissertation presents an extensive experimental characterization and limited theoretical discussion of the dominant optical-intensity and RF-phase noise source in a laboratory setting, where environmental fluctuations are small. The experimental results indicate that the optical-fiber-induced RF-phase noise and optical-intensity noise are caused by the same physical mechanism. The experimental results demonstrate that this mechanism is related to the laser-phase noise but not the laser intensity noise. The bandwidth of the optical-fiber-induced noise depends on the optical-fiber length for lasers with low phase noise, while for lasers with high phase noise, the bandwidth is constant. I demonstrate that the optical-intensity and RF-phase noise can be mitigated by dithering the laser frequency. Based on these results, I hypothesize that interference from Rayleigh scattering is the underlying mechanism of the optical-intensity and RF-phase noise. Prior theoretical work, carried out with high phase noise lasers, predicts that the noise induced by this process will have a bandwidth that is proportional to the laser linewidth and that is constant with respect to the optical-fiber length, for lasers with high-phase noise, which is consistent with the experimental results. I derive a simple model that is valid for low-phase-noise lasers. I compare this model with the experimental results and find that it matches the optical-fiber-length-dependent bandwidth that is measured for low-phase-noise lasers.
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Bhattacharya, Sambuddha. "Template-driven parasitic-aware optimization of analog/RF IC layouts /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6121.
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Jangkrajarng, Nuttorn. "Analog/RF VLSI layout generation : layout retargeting via symbolic template /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6084.
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Tang, Hongxia. "Study of Design for Reliability of RF and Analog Circuits." Doctoral diss., University of Central Florida, 2012. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5525.
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Due to continued device dimensions scaling, CMOS transistors in the nanometer regime have resulted in major reliability and variability challenges. Reliability issues such as channel hot electron injection, gate dielectric breakdown, and negative bias temperature instability (NBTI) need to be accounted for in the design of robust RF circuits. In addition, process variations in the nanoscale CMOS transistors are another major concern in today's circuits design.
An adaptive gate-source biasing scheme to improve the RF circuit reliability is presented in this work. The adaptive method automatically adjusts the gate-source voltage to compensate the reduction in drain current subjected to various device reliability mechanisms. A class-AB RF power amplifier shows that the use of a source resistance makes the power-added efficiency robust against threshold voltage and mobility variations, while the use of a source inductance is more reliable for the input third-order intercept point.
A RF power amplifier with adaptive gate biasing is proposed to improve the circuit device reliability degradation and process variation. The performances of the power amplifier with adaptive gate biasing are compared with those of the power amplifier without adaptive gate biasing technique. The adaptive gate biasing makes the power amplifier more resilient to process variations as well as the device aging such as mobility and threshold voltage degradation.
Injection locked voltage-controlled oscillators (VCOs) have been examined. The VCOs are implemented using TSMC 0.18 μm mixed-signal CMOS technology. The injection locked oscillators have improved phase noise performance than free running oscillators.
A differential Clapp-VCO has been designed and fabricated for the evaluation of hot electron reliability. The differential Clapp-VCO is formed using cross-coupled nMOS transistors, on-chip transformers/inductors, and voltage-controlled capacitors. The experimental data demonstrate that the hot carrier damage increases the oscillation frequency and degrades the phase noise of Clapp-VCO.
A p-channel transistor only VCO has been designed for low phase noise. The simulation results show that the phase noise degrades after NBTI stress at elevated temperature. This is due to increased interface states after NBTI stress. The process variability has also been evaluated.ID: 031001466; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Adviser: Jiann S. Yuan.; Title from PDF title page (viewed July 10, 2013).; Thesis (Ph.D.)--University of Central Florida, 2012.; Includes bibliographical references (p. 101-111).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
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Banerjee, Aritra. "Design of digitally assisted adaptive analog and RF circuits and systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/52919.
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With more and more integration of analog and RF circuits in scaled CMOS technologies, process variation is playing a critical role which makes it difficult to achieve all the performance specifications across all the process corners. Moreover, at scaled technology nodes, due to lower voltage and current handling capabilities of the devices, they suffer from reliability issues that reduce the overall lifetime of the system. Finally, traditional static style of designing analog and RF circuits does not result in optimal performance of the system. A new design paradigm is emerging toward digitally assisted analog and RF circuits and systems aiming to leverage digital correction and calibration techniques to detect and compensate for the manufacturing imperfections and improve the analog and RF performance offering a high level of integration. The objective of the proposed research is to design digital friendly and performance tunable adaptive analog/RF circuits and systems with digital enhancement techniques for higher performance, better process variation tolerance, and more reliable operation and developing strategy for testing the proposed adaptive systems. An adaptation framework is developed for process variation tolerant RF systems which has two parts – optimized test stimulus driven diagnosis of individual modules and power optimal system level tuning. Another direct tuning approach is developed and demonstrated on a carbon nanotube based analog circuit. An adaptive switched mode power amplifier is designed which is more digital-intensive in nature and has higher efficiency, improved reliability and better process resiliency. Finally, a testing strategy for adaptive RF systems is shown which reduces test time and test cost compared to traditional testing.
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Svensson, Gustaf. "Analog Baseband Implementation of a Wideband Observation Receiver for RF Applications." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-131081.
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During the thesis, a two-staged analog baseband circuit incorporating a passive analog filter and a wideband voltage amplifier were successfully designed, implemented in an IC mask layout in a 65nm CMOS technology, and joined with a previously designed analog front-end design to form a wideband observation receiver. The baseband circuit is capable of receiving an IF bandwidth up to 990MHz produced by the analog front-end using low-side injection. The final circuit shows high IMD3 of at least 90 dBc. The voltage amplifier delivers a voltage amplification of 15 dB with around 0.08 dB amplitude precision over the bandwidth, while the passive filter is capable of a passband amplitude precision of 0.67 dB over the bandwidth, while effectively suppress signal images created by the mixer with at least 60 dBc. Both stages were realized in an IC mask layout, in addition, the filter layout were simulated using an EM simulator.
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Cortes, Fernando da Rocha Paixao. "Analysis, design and implementation of analog/RF blocks suitable for a multi-band analog interface for CMOS SOCs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2008. http://hdl.handle.net/10183/13132.
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O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico.The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.
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Bhattacharya, Soumendu. "Alternate Testing of Analog and RF Systems using Extracted Test Response Features." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7200.
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Testing is an integral part of modern semiconductor industry. The necessity of test is evident, especially for low-yielding processes, to ensure Quality of Service (QoS) to the customers. Testing is a major contributing factor to the total manufacturing cost of analog/RF systems, with test cost estimated to be up to 40% of the overall cost. Due to the lack of low-cost, high-speed testers and other test instrumentation that can be used in a production line, low-cost testing of high-frequency devices/systems is a tremendous challenge to semiconductor test community. Also, simulation times being very high for such systems, the only possible way to generate reliable tests for RF systems is by performing direct measurements on hardware. At the same time, inserting test points for such circuits while maintaining signal integrity is a difficult task to achieve.
The proposed research develops a test strategy to reduce overall test cost for RF circuits. A built-in-test (BIT) approach using sensors is proposed for this purpose, which are designed into high-frequency circuits. The work develops algorithms for selecting optimal test access points, and the stimulus for testing the DUT. The test stimulus can be generated on-chip, through efficient design reuse or using custom built circuits. The test responses are captured and analyzed by on-chip sensors, which are custom designed to extract test response features. The sensors, which have low silicon area overhead, output either DC or low frequency test response signals and are compatible to low-speed testers; hence are low-cost. The specifications of the system are computed using a set of nonlinear models developed using the alternate test methodology. The whole approach has been applied to a RF receiver at 1 GHz, used as a test vehicle to prove the feasibility of the proposed approach. Finally, the method is verified through measurements made on a large number of devices, similar to an industrial production test situation. The proposed method using sensors estimated system-level as well as device-level specifications very accurately in the emulated production test environment with a significantly smaller test cost than existing production tests.
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Leung, Matthew Chung-Hin. "CMOS RF SOC Transmitter Front-End, Power Management and Digital Analog Interface." Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24664.
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With the growing trend of wireless electronics, frequency spectrum is crowded with different applications. High data transfer rate solutions that operate in license-exempt frequency spectrum range are sought. The most promising candidate is the 60 GHz multi-giga bit transfer rate millimeter wave circuit. In order to provide a cost-effective solution, circuits designed in CMOS are implemented in a single SOC.
In this work, a modeling technique created in Cadence shows an error of less than 3dB in magnitude and 5 degree in phase for a single transistor. Additionally, less than 3dB error of power performance for the PA is also verified. At the same time, layout strategies required for millimeter wave front-end circuits are investigated. All of these combined techniques help the design converge to one simulation platform for system level simulation.
Another aspect enabling the design as a single SOC lies in integration. In order to integrate digital and analog circuits together, necessary peripheral circuits must be designed. An on-chip voltage regulator, which steps down the analog power supply voltage and is compatible with digital circuits, has been designed and has demonstrated an efficiency of 65 percent with the specific area constraint. The overall output voltage ripple generated is about 2 percent.
With the necessary power supply voltage, gate voltage bias circuit designs have been illustrated. They provide feasible solutions in terms of area and power consumption. Temperature and power supply sensitivities are minimized in first two designs. Process variation is further compensated in the third design. The third design demonstrates a powerful solution that each aspect of variations is well within 10%.
As the DC conditions are achieved on-chip for both the digital and analog circuits, digital and analog circuits must be connected together with a DAC. A high speed DAC is designed with special layout techniques. It is verified that the DAC can operate at a speed higher than 3 Gbps from the pulse-shaping FIR filter measurement result.
With all of these integrated elements and modeling techniques, a high data transfer rate CMOS RF SOC operating at 60 GHz is possible.
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YANG, WEI. "AUTOMATIC HIGH-LEVEL MODEL GENERATION FOR ANALOG RF CIRCUITS IN VHDL-AMS." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109207864.
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Thandri, Bharath Kumar. "Design of RF/IF analog to digital converters for software radio communication receivers." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5774.
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Software radio architecture can support multiple standards by performing analogto-
digital (A/D) conversion of the radio frequency (RF) signals and running
reconfigurable software programs on the backend digital signal processor (DSP). A
slight variation of this architecture is the software defined radio architecture in which the
A/D conversion is performed on intermediate frequency (IF) signals after a single down
conversion.
The first part of this research deals with the design and implementation of a
fourth order continuous time bandpass sigma-delta (CT BP) C based on LC filters
for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC
architecture is proposed which uses only non-return to zero feedback digital to analog
converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz
and 1 MHz, respectively, around 950 MHz while consuming 75 mW of power from ±
1.25 V supply.
The second part of this research deals with the design of a fourth order CT BP ADC based on gm-C integrators with an automatic digital tuning scheme for IF
digitization at 125 MHz and a clock frequency of 500 MHz. A linearized CMOS OTA
architecture combines both cross coupling and source degeneration in order to obtain
good IM3 performance. A system level digital tuning scheme is proposed to tune the
ADC performance over process, voltage and temperature variations. The output bit
stream of the ADC is captured using an external DSP, where a software tuning algorithm
tunes the ADC parameters for best SNR performance. The IF ADC was designed in
TSMC 0.35 µm CMOS technology and it consumes 152 mW of power from ± 1.65 V
supply.
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Eltayeb, Mathani Abdalla Mohamed. "Analog Linearization of an RF PA Using Baseband Feedback and Power Gate Tracking." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020.
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The advent of 5G has introduced more complicated modulation schemes that produce signals with high peak-to-average power ratios. Requirements on linearity for wideband signals are becoming more crucial. However linearity is not the only critical parameter, efficiency is a key feature in many applications. The power consumed within the RF amplifier impacts the efficiency of the whole communication systems, increasing the need for cooling and limiting the battery lifetime for handset devices. Achievement
of high efficiency typically has a negative impact on the linearity of the power amplifier, which in turn introduces nonlinear distortion components on the transmitted signal. A common solution in communication systems is to push for efficiency and then employ one or more linearity enhancement schemes to correct the signal. Among these schemes digital predistiotion
(DPD) is a popular one for its effectiveness in correcting the signals’ distortion. Not without consequences though; due to memory effects DPD has limitations when it comes to bandwidth. With growing demand on wideband communication analog linearization methods appear very attractive. This thesis presents the effects of baseband feedback as an alternative to linearization by digital predistortion. In addition, the thesis work explores the possibility of enhancing linearity by tracking the power of the envelope at the gate. The activities carried out include simulation, implementation and measurements.
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Dornelas, Helga Uchoa. "Low power SAR analog-to-digital converter for internet-of-things RF receivers." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/186015.
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The "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of high relevance in this area. The exponential increase of devices with wireless capabilities as well as the number of users, alongside with the decreasing costs for implementation of broadband communications, created a suitable environment for IoT applications. An IoT device is typically composed by a wireless transceiver, a battery and/or energy harvesting unit, a power management unit, sensors and conditioning unit, a microprocessor and data storage unit. Energy supply is a limiting factor in many applications and the transceiver usually demands a significant amount of power. In this scenario the emerging wireless communication standard IEEE 802.11ah, in which this work focuses, was proposed as an option for low power sub-GHz radio communication. A typical architecture of modern radio receivers contains the analog radio-frequency (RF) front-end, which amplifies, demodulates and filters the input signal, and also analog-to-digital converters (ADC), that translate the analog signals to the digital domain. Additionally, the Successive-Approximation (SAR) ADC architecture has become popular recently due to its power efficiency, simplicity, and compatibility with scaled-down integrated CMOS technology. In this work, the RF receiver architecture and its specifications aiming low power consumption and IEEE 802.11ah standard complying are outlined, being the basis to the proposition of an 8-bit resolution and 10 MHz sampling rate ADC. A power efficient switching scheme for the charge redistribution SAR ADC architecture is explored in detail, along with the circuit-level design of the digital-to-analog converter (DAC). The transistor-level design of the two remaining ADC main blocks, sampling switch and comparator, are also explored. Electrical simulation of the physical layout, including parasitics, at a 130nm CMOS process resulted in a SINAD of 47:3 dB and 45:5 dB and at the receiver IF 3 MHz and at the Nyquist rate, respectively, consuming 21 W with a power supply of 1 V . The SAR ADC resulting Figure-of-Merit (FoM) corresponded to 11:1 fJ/conv-step at IF, and 13:7 fJ/conv-step at the Nyquist rate.
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Negreiros, Marcelo. "Low cost BIST techniques for linear and non-linear analog circuits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/6225.
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Com a crescente demanda por produtos eletrônicos de consumo de alta complexidade, o mercado necessita de um rápido ciclo de desenvolvimento de produto com baixo custo. O projeto de equipamentos eletrônicos baseado no uso de núcleos de propriedade intelectual ("IP cores") proporciona flexibilidade e velocidade de desenvolvimento dos chamados "sistemas num chip". Entretanto, os custos do teste destes sistemas podem alcançar um percentual significativo do valor total de produção, principalmente no caso de sistemas contendo "IP cores" analógicos ou "mixed-signal". Técnicas de teste embarcado (BIST e DFT) para circuitos analógicos, embora potencialmente capazes de minimizar o problema, apresentam limitações que restringem seu emprego a casos específicos. Algumas técnicas são dependentes do circuito, necessitando reconfiguração do circuito sob teste, e não são, em geral, utilizáveis em RF. No ambiente de "sistemas num chip", como recursos de processamento e memória estão disponíveis, eles poderiam ser utilizados durante o teste. No entanto, a sobrecarga de adicionar conversores AD e DA pode ser muito onerosa para a maior parte dos sistemas, e o roteamento analógico dos sinais pode não ser possível, além de poder introduzir distorção do sinal. Neste trabalho um digitalizador simples e de baixo custo é usado ao invés de um conversor AD para possibilitar a implementação de estratégias de teste no ambiente de "sistemas num chip". Graças ao baixo acréscimo de área analógica do conversor, múltiplos pontos de teste podem ser usados. Graças ao desempenho do conversor, é possível observar características dos sinais analógicos presentes nos "IP cores", incluindo a faixa de freqüências de RF usada em transceptores para comunicações sem fio. O digitalizador foi utilizado com sucesso no teste de circuitos analógicos de baixa freqüência e de RF. Como o teste é baseado no domínio freqüência, características nãolineares como produtos de intermodulação podem também ser avaliadas. Especificamente, resultados práticos com protótipos foram obtidos para filtros de banda base e para um mixer a 100MHz. A aplicação do conversor para avaliação da figura de ruído também foi abordada, e resultados experimentais utilizando amplificadores operacionais convencionais foram obtidos para freqüências na faixa de áudio. O método proposto é capaz de melhorar a testabilidade de projetos que utilizam circuitos de sinais mistos, sendo adequado ao uso no ambiente de "sistemas num chip" usado em muitos produtos atualmente.With the ever increasing demands for high complexity consumer electronic products, market pressures demand faster product development and lower cost. SoCbased design can provide the required design flexibility and speed by allowing the use of IP cores. However, testing costs in the SoC environment can reach a substantial percent of the total production cost. Analog testing costs may dominate the total test cost, as testing of analog circuits usually require functional verification of the circuit and special testing procedures. For RF analog circuits commonly used in wireless applications, testing is further complicated because of the high frequencies involved. In summary, reducing analog test cost is of major importance in the electronic industry today. BIST techniques for analog circuits, though potentially able to solve the analog test cost problem, have some limitations. Some techniques are circuit dependent, requiring reconfiguration of the circuit being tested, and are generally not usable in RF circuits. In the SoC environment, as processing and memory resources are available, they could be used in the test. However, the overhead for adding additional AD and DA converters may be too costly for most systems, and analog routing of signals may not be feasible and may introduce signal distortion. In this work a simple and low cost digitizer is used instead of an ADC in order to enable analog testing strategies to be implemented in a SoC environment. Thanks to the low analog area overhead of the converter, multiple analog test points can be observed and specific analog test strategies can be enabled. As the digitizer is always connected to the analog test point, it is not necessary to include muxes and switches that would degrade the signal path. For RF analog circuits, this is specially useful, as the circuit impedance is fixed and the influence of the digitizer can be accounted for in the design phase. Thanks to the simplicity of the converter, it is able to reach higher frequencies, and enables the implementation of low cost RF test strategies. The digitizer has been applied successfully in the testing of both low frequency and RF analog circuits. Also, as testing is based on frequency-domain characteristics, nonlinear characteristics like intermodulation products can also be evaluated. Specifically, practical results were obtained for prototyped base band filters and a 100MHz mixer. The application of the converter for noise figure evaluation was also addressed, and experimental results for low frequency amplifiers using conventional opamps were obtained. The proposed method is able to enhance the testability of current mixed-signal designs, being suitable for the SoC environment used in many industrial products nowadays.
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Zimmerman, Mark D. "In Vivo RF Powering for Advanced Biological Research." Case Western Reserve University School of Graduate Studies / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=case1212429431.
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McGinnis, Ryan Edward. "Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1152542196.
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Devarakond, Shyam Kumar. "Signature driven low cost test, diagnosis and tuning of wireless systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47594.
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With increased and varied performance demands, it is essential that complex multi-standard radio/systems coexist on a same chip. To have cost and performance benefits, these analog/RF systems are implemented in scaled nanometer nodes. At these nodes, the high level of variability in process variations is making the task of manufacturing high fidelity systems a challenge leading to yield and reliability issues. Hence, in the post-manufacturing phase, test and diagnosis steps are critical to identify the cause and effect of the process variations. Further, intelligent post-manufacturing tuning techniques are required to correct the effect of process variations on analog/RF systems. In this work, a die-level concurrent test and diagnosis approach using optimized measurements obtained in high volume manufacturing environment is proposed for analog/RF circuits. Such a simultaneous test and diagnosis methodology enables monitoring parametric process shifts and providing rapid feedback to the fab to minimize or prevent yield loss. In the case of devices that are continuously operating in the field, an efficient on-line diagnosis approach has been developed to perform reliability related prognosis. For advanced RF technologies such as MIMO-OFDM systems, a rapid system-level testing scheme is presented that performs concurrent testing of the multiple RF chains. Depending on the availability of the computational resources and system tuning knobs, different low-cost methodologies for post-manufacture tuning or self-healing of RF SISO/MIMO systems are developed. These include faster digital monitoring and tuning techniques, on-chip tuning techniques using digital logic that enables die-level self-tuning, and DSP-based power conscious iterative techniques for SISO/MIMO RF systems. An adaptive power-performance tuning technique is developed for those devices that have a post-manufacture power consumption value that is more than the acceptable limit. These intelligent post-manufacturing techniques result in reduced manufacturing cost, improved yield, and reliability of analog/RF systems.
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Pheng, Bobby B. "3D Electromagnetic Simulation Tool Exposure for Undergraduate Electrical Engineers: Incorporation into an Analog Filters Course." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/819.
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With the growth of wireless communications, comes the need for engineers knowledgeable in 3D electromagnetic (EM) simulation of high-frequency circuits. To give electrical engineering students a better understanding of the behavior of electromagnetic fields, experiments including the use of 3D EM simulation software were proposed. Most students get lost in differential equations, curls, and divergences; this thesis aims to remedy that by exposing them to 3D EM simulation, which may motivate them toward further study in electromagnetics. Also, experience using EMPro is very beneficial for future RF/microwave/antenna engineers, as use of 3D EM simulation is becoming a requirement for this field. 3D EM simulators solve problems where using classical analysis techniques is impractical. Classical EM solutions to simple objects such as boxes, cylinders, and spheres, are widely known; but when the object is more complex, numerical approaches are preferred for their speed.
Currently, Cal Poly does not use 3D electromagnetic simulation in any of its courses. Targeted relevant courses include EE 335/375: EM Fields & Transmission Lines, EE 402: EM Waves, EE 405/445: High-Frequency Amplifier Design, EE 425/455: Analog Filter Design, EE 502: Microwave Engineering, and EE 533: Antennas. As a starting point, EE 425/455 was targeted.
In choosing which filters to investigate, simplicity and cost were the most important factors. For simplicity, transverse electromagnetic (TEM) mode filters were chosen; also, using a trough design for these filters would allow for simple construction and access. Also, a circular waveguide filter was chosen as an alternative to the TEM filters, as the modes are either transverse electric or transverse magnetic. To lower costs, printed circuit board was used to construct the filters, along with brass tubing, semi-rigid coaxial cable, and copper plumbing caps.
From these guidelines, three electronic bandpass filter experiments were investigated: a 1 GHz half-wave coaxial resonator filter, a 2 GHz copper end cap filter, and a tunable 1 GHz quarter-wave coaxial resonator filter. Electric and magnetic field coupling was used to excite the filters. They were then simulated using finite difference time domain (FDTD) simulations in Agilent EMPro. From the simulations, tradeoffs between insertion loss and bandwidth were observed. After, the filters were built and measured using a network analyzer. The quarter-wave filter was incorporated in Cal Poly’s EE 455 course during spring 2012. Students completed an EMPro tutorial, simulated the filters, and measured them using network analyzers. Student feedback was mixed, and modifications were made for future implementations.
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Eklund, Henrik. "Linearization of Resistive Digital-to-Analog Converter for RF-Applications Using Compensator and Digital Predistortion." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-177574.
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High-speed digital-to-analog converters are critical components in many radiofrequency (RF) applications. The resistive DAC (RDAC) architecture is suitable for high-speed implementation in extremely scaled digital circuit nodes. An RDAC core can be implemented as a resistance network and a digital block, consisting of inverters as drivers to the resistive network. One disadvantage of the architecture is the input code-dependent supply current. Combined with a non-zero supply network impedance, the code-dependent current will introduce non-linearity in the output voltage. One way to circumvent the problem is to use a high-performance voltage regulator, which counteracts the voltage variation in the impedance in the RDAC supply network. In this thesis work, two alternative solutions are investigated; Compensation with another signal-dependent impedance in parallel with the RDAC core to reduce the impedance variations and a digital predistorter (DPD) which corrects the non-linearities of RDAC output voltage. The investigated techniques can be used for improving the linearity of an RDAC in certain cases. The current compensation technique works best at low frequencies, while the DPD can be used for all frequencies to relax requirements on routing resistance or voltage regulation design.
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Patel, Vipul J. "A Poly-phased, Time-interleaved Radio Frequency Digital-to-analog Converter (Poly-TI-RF-DAC)." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright1516146989134088.
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Wang, Fa. "Efficient Pre-Silicon Validation and Post-Silicon Tuning of Self-Healing Analog/RF Integrated Circuits." Research Showcase @ CMU, 2015. http://repository.cmu.edu/dissertations/614.
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The advent of the nanoscale integrated circuit (IC) technology makes high performance analog and RF circuit increasingly susceptible to large-scale process variations. Process variations, including inter-die variations and local mismatches, significantly impact the parametric yield of analog/RF circuit, and must be properly handled at all levels of design hierarchy. Traditional approaches based on over-design are not sufficient to maintain high parametric yield, due to the large-scale process variations and aggressive design specifications at advanced technology nodes. In this context, the self-healing circuit has emerged as promising methodology to address the variability issue. In this thesis, we propose efficient pre-silicon validation and post-silicon tuning techniques, which are essential for the practical usage of self-healing methodology. One important problem in self-healing methodology is to efficiently and accurately predict the parametric yield in pre-silicon. The main challenge of this problem is caused by multiple circuit states related to tuning knobs. Given that these circuit states closely interact with process variations, they must be properly modeled in order to accurately estimate the parametric yield. Towards this goal, we develop an efficient performance modeling algorithm, referred to Correlated Bayesian Model Fusion (C-BMF) that explores the correlation between circuit states. Next, based on the performance model, the self-healing behavior and the parametric yield can be efficiently and accurately predicted. Another important problem in self-healing circuit is to efficiently perform post-silicon tuning. Towards this goal, indirect performance sensing methodology has recently attracted great attention. In the indirect performance sensing paradigm, the performance of interest (PoI) is not directly measured by on-chip sensor, but is instead accurately predicted from an indirect sensor model. Such indirect sensor model takes a set of other performances as inputs, which are referred to as the performances of measurements (PoMs). The PoMs are selected such that they are highly correlated with PoI and are easy to measure. Due to the process shift associated with manufacturing lines, the indirect sensor model must be calibrated from time to time. For the purpose of reducing the model calibration cost, we propose a Bayesian Model Fusion (BMF) algorithm that reuses the information collected in early stage of manufacturing. We further extend BMF to a Co-learning Bayesian Model Fusion (CL-BMF) algorithm that incorporates not only the early stage information, but also the current stage information that was not considered in the original modeling problem.
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Bousseaud, Pierre. "Récepteur SDR par échantillonnage direct du signal RF." Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENT122/document.
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Mes travaux de thèse portent sur l'échantillonnage direct du signal RF en réception après l'antenne, dans un contexte d'applications radio-logicielle et radio-cognitive. Le but de cette technique est de pouvoir traiter le signal quelle que soit la modulation utilisée et dans une large gamme de fréquences, directement après l'antenne, en réduisant au maximum la partie analogique. Pour cela une architecture d'échantillonneur passif a été utilisée. L'originalité de cette architecture consiste en l'implémentation d'un système d'échantillonnage différentiel en quadrature purement passif, constitué d'un réseau de capacités commutées. En fixant la constante de temps du système à une valeur élevée devant la fréquence minimale du signal RF à démoduler, l'échantillonneur se comporte à la fois en tant que mélangeur et filtre en fréquence. Cela permet la réjection des brouilleurs hors de la bande de réception et contribue à améliorer sensiblement la dynamique du système de réception, le tout pour une consommation très faible. Aussi, le système est flexible en fréquence, permettant ainsi de recevoir le spectre RF sur une large bande et de recevoir différents types de signaux modulés. Celui-ci a été intégré dans un front-end de réception complet en technologie CMOS 130nm pour des applications dans les bandes ISM (433MHz et 868MHz) dont les débits de transmission sont limités à 1Mbits/s. L'architecture développée est adaptée à des applications de type radio-logicielle ou radio-cognitive, lorsqu'une agilité en fréquence, une grande dynamique et des contraintes de consommation très basse sont viséesMy thesis work is focusing on the RF signal direct sampling reception after the antenna in a software-defined radio applications and cognitive radio context. The purpose of this technique is to treat the signal whatever the modulation used and in a wide range of frequencies, directly after the antenna while minimizing at maximum the analog part. For this, a passive sampler architecture has been used. The originality of this architecture consists in the implementation of a passive differential sampling system working in quadrature, consisting of a switched capacitors network. By setting the time system constant to a high value compared to the minimum frequency of the RF signal to be demodulated , the sampler acts both as a filter and a frequency mixer. This allows the rejection of interferers outside the reception band and contributes to improve significantly the receiver system dynamic, for a very low consumption. Also, the system is flexible in frequency, which permits to receive the RF spectrum over a wide band of frequencies and detect different types of modulated transmitted signals. It has been integrated into a complete front-end 130nm CMOS technology receiver dedicated to ISM bands applications (433MHz and 868MHz bands) whose transmission data rates are limited to 1Mbit/s. The developed architecture is suitable for software-defined radio or cognitive radio applications where frequency agility, high dynamic and very low power constraints are targeted
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Larguech, Syhem. "Test indirect des circuits analogiques et RF : implémentation sûre et efficace." Thesis, Montpellier, 2015. http://www.theses.fr/2015MONTS185/document.
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Être en mesure de vérifier si un circuit intégré est fonctionnel après fabrication peut s'avérer très difficile. Dans le cas des circuits analogiques et Radio Fréquence (RF) les procédures et les équipements de test nécessaires ont un impact majeur sur le prix de revient des circuits. Une approche intéressante pour réduire l'impact du coût du test consiste à mesurer des paramètres nécessitant des ressources de test faible coût et corréler ces mesures, dites mesures indirectes, avec les spécifications à tester. On parle alors de technique de test indirect (ou test alternatif) car il n'y a pas de mesure directe des spécifications, qui nécessiterait des équipements et du temps de test importants, mais ces spécifications sont estimées à partir des mesures « faibles couts ». Même si cette approche semble attractive elle n'est viable que si nous sommes en mesure d'établir une précision suffisante de l'estimation des performances et que cette estimation reste stable et indépendante des lots de circuits à traiter. L'objectif principal de cette thèse est de mettre en œuvre une stratégie générique permettant de proposer un flot de test indirect efficace et robuste. Pour être en mesure de construire cette stratégie nous avons amenés différentes contributions. Dans un premier temps, on a développée une nouvelle métrique dans cette thèse pour évaluer la robustesse des prédictions relaissées. Dans un deuxième temps, on a défini et analysé une stratégie pour la construction d'un model optimal. Cette dernière englobe un prétraitement de données ensuite une analyse comparative entre différentes méthodes de sélections de mesures indirectes aussi l'étude d'autres paramètres tels que la taille des combinaisons de mesures indirectes ainsi que celle de la taille de set d'apprentissage. Aussi on a proposé une stratégie pour une confidente exploration d'espace de mesures indirectes afin de construire plusieurs meilleurs modèles qu'on peut se servir par la suite pour résoudre des problèmes de confiance et d'optimisation. Les études comparatives réalisées ont été effectuées sur 2 cas d'études expérimentaux et à partir de métriques classiques et de la nouvelle métrique proposée permettant ainsi d'évaluer objectivement la robustesse de chaque solution.En fin, nous avons développé une stratégie complète mettant en œuvre des techniques de redondance de modèles de corrélation qui permettent d'améliorer grandement la robustesse et l'efficacité de la prise de décision en fonction des mesures obtenues. Cette stratégie est adaptable à n'importe quel contexte en termes de compromis entre le coût du test et le niveau de confiance et de précision attenduBeing able to check whether an IC is functional or not after the manufacturing process is very difficult. Particularly for analog and Radio Frequency (RF) circuits, test equipment and procedures required have a major impact on the circuits cost. An interesting approach to reduce the impact of the test cost is to measure parameters requiring low cost test resources and correlate these measurements, called indirect measurements, with the targeted specifications. This is known as indirect test technique because there is no direct measurement for these specifications, which requires so expensive test equipment and an important testing time, but these specifications are estimated w.r.t "low-cost measurements". While this approach seems attractive, it is only viable if we are able to establish a sufficient accuracy for the performance estimation and if this estimation remains stable and independent from the circuits sets under test.The main goal of this thesis is to implement a robust and effective indirect test strategy for a given application and to improve test decisions based on data analysis.To be able to build this strategy, we have brought various contributions. Initially, we have defined new metric developed in this thesis to assess the reliability of the estimated performances. Secondly, we have analyzed and defined a strategy for the construction of an optimal model. This latter includes a data preprocessing followed by a comparative analysis of different methods of indirect measurement selection. Then, we have proposed a strategy for a confidant exploration of the indirect measurement space in order to build several best models that can be used later to solve trust and optimization issues. Comparative studies were performed on 2 experimental data sets by using both of the conventional and the developed metrics to evaluate the robustness of each solution in an objective way.Finally, we have developed a comprehensive strategy based on an efficient implementation of the redundancy techniques w.r.t to the build models. This strategy has greatly improved the robustness and the effectiveness of the decision plan based on the obtained measurements. This strategy is adaptable to any context in terms of compromise between the test cost, the confidence level and the expected precision
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Nygaard, Erich Johannes. "Signal Transport and RF over Fiber Design for ALPACA." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8753.
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The design of the RF over fiber signal transport system for the ALPACA receiver is described, with particular attention to the strict noise requirements as well as dynamic range considerations. Also discussed are analytical tools for analyzing dynamic range in the context of RFI-rich radio astronomy observational settings, including formulas for maximum interference to noise ratios and a simulation framework for predicting distortion levels. Phase and gain stability measurements of the signal transport system are presented, including the effects of the multi-strand armored fiber optic cable. The resulting system meets design requirements, with equivalent noise temperature below 900 K in 90° F ambient air, resulting in less than 1 K contribution to the system noise temperature. Typical gain is 31-37 dB, and gain differences between channels are stable within 0.25 dB in 90° F conditions. Phase drift between channels due to electronics remains below 1° at room temperature, and below 1.3° in a warm environment. The fiber optic cable is predicted to cause phase changes between channels of no more than 1.3° per °C. Typical spurious free dynamic range is 99 dB·Hz^(⅔), and distortion levels for normal RFI conditions at Arecibo are expected to be 28 dB below the system noise floor.
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Valdes, Garcia Alberto. "System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5757.
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This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand
(UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits.
The MultiBand OFDM (MB-OFDM) proposal for UWB communications has
received significant attention for the implementation of very high data rate (up to
480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion
quadrature mixer, and the overall radio system-level design are proposed for
an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented
in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with
interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in
quadrature with fast hopping, and a linear phase baseband section with 42dB of gain
programmability. The receiver IC mounted on a FR-4 substrate provides a maximum
gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a
2.5V supply.
Two BIT techniques for analog and RF circuits are developed. The goal is to reduce
the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the
magnitude and phase responses at different nodes of an analog circuit. A complete
prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is
demonstrated by performing frequency response measurements in a range of 1 to
130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF
RMS Detector and a methodology for its use in the built-in measurement of the gain and
1dB compression point of RF circuits are proposed to address the problem of on-chip
testing at RF frequencies. The proposed device generates a DC voltage proportional to
the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology
presents and input capacitance <15fF and occupies and area of 0.03mm2. The application
of these two techniques in combination with a loop-back test architecture significantly
enhances the testability of a wireless transceiver system.
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Kundur, Abhinay. "Digital and Analog Signal Encryption and Decryption in Mid RF Range Using Hybrid Acousto-Optic Chaos." University of Dayton / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1336100009.
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Kumar, Akshay. "Measurement of Antenna Performance in Analog LMR Systems Using PL Tone Analysis." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/46188.
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We are interested in measuring the in situ antenna performance in analog land mobile radio (LMR) FM systems. The gain (efficiency and directivity) and self-impedance of an antenna sufficiently characterize its performance and a number of traditional methods exist to measure these quantities. However it is hard to do antenna gain measurements using these methods. Furthermore, it turns out that volumetric antenna gain measurements are not quite relevant for understanding in situ performance. In this thesis, we present a novel approach for directly measuring the in situ performance of antennas in analog LMR systems. The procedure involves receiving an FM signal simultaneously using the antenna under test (AUT) and a reference antenna. Both received signals are demodulated to audio using separate but identical receivers. Then a convenient method for characterizing the audio signal quality is to analyze the private line (PL) tone. The PL tone signal-to-noise ratio (SNR) is calculated by measuring the power of the tone relative to the sub-audio noise power. The PL tone SNR for both antenna systems is compared as it provides a ``bottom line'' evaluation of the antenna performance. The audio SNR can also be mapped to RF SNR using a theoretical method. From simulation and experimental studies, we conclude that the RF SNR estimated using this technique is within 0.5 dB of the actual value for RF SNR values between +3 and +36 dB. Finally, we demonstrate this procedure in actual in situ LMR antenna measurements.Master of Science
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Hamanaka, Cristian Otsuka. "Projeto de circuitos para geração de tensão de referência em sistemas receptores/transmissores RF." Universidade de São Paulo, 2007. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-09012008-164614/.
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Este trabalho consiste no projeto de uma Fonte de Tensão de Referência CMOS com coeficiente de temperatura inferior a 50 ppm/ºC. Esta fonte deve ser aplicada em receptores/transmissores de radio freqüência mas pode também ser utilizada em qualquer sistema analógico. A tecnologia utilizada foi a CMOS 0,35 µm da AMS (Austria Micro Systems) com quatro níveis de metal e dois de silício policristalino. A fonte de tensão implementada é do tipo Bandgap e utiliza dispositivos MOS em inversão fraca, um transistor bipolar parasitário e resistores de silício policristalino de alta resistividade. No circuito é produzida uma tensão PTAT (Proportional to Absolute Temperature) que somada a tensão base-emissor do transistor bipolar resulta numa tensão de saída independente da temperatura. O projeto e o desenho do layout desta fonte foram realizados. A partir do layout foram gerados netlists para simulações realizadas utilizando o software ELDO com o modelo MOS BSIM3v3, nas condições de operação típicas, worst speed e worst power. Através destas simulações verificou-se que o circuito atendia as especificações iniciais. O valor da tensão de saída, no entanto, apesar de estar próximo do valor desejado de 1,25 V, variou com as condições de simulação empregadas. Dois circuitos Bandgap diferentes foram enviados para fabricação: um circuito com resistores integrados (dimensões de 220 µm x 76 µm) e outro sem os resistores (dimensões de 190 µm x 36 µm). Este último permite, com o ajuste do valor dos resistores colocados externamente, modificar, se necessário, as condições de operação do circuito. Os circuitos foram caracterizados obtendo-se para o circuito com resistores integrados um coeficiente de temperatura inferior à 40 ppm/ºC, taxa de variação da saída com a tensão de alimentação próxima de 19 mV/V. O valor da tensão de saída a 50 ºC esteve entre 1,1835 V e 1,2559 V (1,25 V ± 67 mV). Para o circuito sem os resistores integrados, obteve-se um coeficiente de temperatura que chegou à 90 ppm/ºC, taxa de variação da saída com a tensão de alimentação inferior à 28 mV/V. O valor da tensão de saída a 50 ºC esteve entre 1,247 V e 1,2588 V (1,25 V ± 9 mV). A faixa de temperatura utilizada para as medidas foi de -30 ºC a 100 ºC. O consumo de corrente dos circuitos é de aproximadamente 14 µA e seu funcionamento é garantido para tensões de alimentação tão baixas quanto 1,8 V.This work consists in the design of a CMOS Voltage Reference Source with a temperature coefficient inferior to 50 ppm/ºC. This voltage source should be applied in radio frequency receptor/transmitter but can be also applied in any analog system. The technology employed in the design is the CMOS 0.35 µm from the AMS (Austria Micro Systems) with four metal levels and two poly-silicon levels. The implemented voltage source is of the Bandgap type and uses MOS devices in weak inversion, a parasitic bipolar transistor, and resistors made with high resistive poly-silicon. The circuit produces a PTAT (Proportional to Absolute Temperature) voltage that is added to the bipolar transistor base-emitter voltage to build an output voltage independent of temperature. The project and the drawing of the layout of the circuit had been carried out. The netlists of the circuit were generated from the layout and they were employed in simulations done with the software ELDO and the BSIM3v3 MOS model, in typical, worst speed, and worst power conditions. Through these simulations it was verified that the circuit reached the initial specifications. The value of the output voltage, however, although being next to the desired value of 1.25 V, varied with the employed simulation conditions. Two different Bandgap circuits had been sent to the foundry: a circuit with integrated resistors (dimensions of 220 µm x 76 µm) and another one without the resistors (dimensions of 190 µm x 36 µm). This last one allows, with the adjustment of external resistor values, modifying, if necessary, the operation conditions of the circuit. The circuits had been characterized and the circuit with integrated resistors has a temperature coefficient inferior to 40 ppm/ºC, an output variation rate with the power supply close to 19 mV/V. The output voltage value at 50 ºC is between 1.1835 V and 1.2559 V (1.25 V ± 67 mV). The circuit without the resistors has a temperature coefficient as high as 90 ppm/ºC, an output variation rate with the power supply inferior to 28 mV/V. The output voltage value at 50 ºC is between 1.247 V and 1.2588 V (1.25 V ± 9 mV). The temperature range used in the measurements was from -30 ºC to 100 ºC. The current consumption of the circuits is approximately of 14 µA, and they operate with power supply voltages as low as 1.8 V.
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Gao, Yuan [Verfasser], and Klaus [Akademischer Betreuer] Solbach. "Low RF-complexity massive MIMO systems : antenna selection and hybrid analog-digital beamforming / Yuan Gao ; Betreuer: Klaus Solbach." Duisburg, 2017. http://d-nb.info/1142113604/34.
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Huang, Ke. "Modélisation de fautes et diagnostic pour les circuits mixtes/RF nanométriques." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00670338.
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Le diagnostic de fautes est essentiel pour atteindre l'objectif de temps avant mise sur le marché (time to market) des premiers prototypes de circuits intégrés. Une autre application du diagnostic est dans l'environnement de production. Les informations du diagnostic sont très utiles pour les concepteurs de circuits afin d'améliorer la conception et ainsi augmenter le rendement de production. Dans le cas où le circuit est une partie d'un système d'importance critique pour la sûreté (e.g. automobile, aérospatial), il est important que les fabricants s'engagent à identifier la source d'une défaillance dans le cas d'un retour client pour ensuite améliorer l'environnement de production afin d'éviter la récurrence d'un tel défaut et donc améliorer la sûreté. Dans le cadre de cette thèse, nous avons développé une méthodologie de modélisation et de diagnostic de fautes pour les circuits analogiques/mixtes. Une nouvelle approche basée sur l'apprentissage automatique a été proposée afin de considérer les fautes catastrophiques et paramétriques en même temps dans le diagnostic. Ensuite, nous avons focalisé sur le diagnostic de défauts spot qui sont considérés comme le mécanisme de défauts principal de circuits intégrés. Enfin, la méthodologie du diagnostic proposée a été validée par les données de circuits défectueux fournies par NXP Semiconductors - Netherlands. Mots clés: Diagnostic de fautes, modélisation de fautes, test analogique, analyse de défauts, apprentissage automatique
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Nilsson, Johan, and Mikael Rothin. "Live Demonstration of Mismatch Compensation for Time-Interleaved ADCs." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-78709.
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The purpose of this thesis is to demonstrate the effects of mismatch errors that occur in time-interleaved analog-to-digital converters (TI-ADC) and how these are compensated for by proprietary methods from Signal Processing Devices Sweden AB. This will be demonstrated by two different implementations, both based on the combined digitizer/generator SDR14. These demonstrations shall be done in a way that is easy to grasp for people with limited knowledge in signal processing. The first implementation is an analog video demo where an analog video signal is sampled by such an TI-ADC in the SDR14, and then converted back to analog and displayed with the help of a TV tuner. The mismatch compensation can be turned on and off and the difference on the resulting video image is clearly visible. The second implementation is a digital communication demo based on W-CDMA, implemented on the FPGA of the SDR14. Four parallel W-CDMA signals of 5 MHz are sent and received by the SDR14. QPSK, 16-QAM, and 64-QAM modulated signals were successfully sent and the mismatch effects were clearly visible in the constellation diagrams. Techniques used are, for example: root-raised cosine pulse shaping, RF modulation, carrier recovery, and timing recovery.
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Omid, Abedi. "Analog and Digital Approaches to UWB Narrowband Interference Cancellation." Thèse, Université d'Ottawa / University of Ottawa, 2012. http://hdl.handle.net/10393/23366.
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Ultra wide band (UWB) is an extremely promising wireless technology for researchers and industrials. One of the most interesting is its high data rate and fading robustness due to selective frequency fading. However, beside such advantages, UWB system performance is highly affected by existing narrowband interference (NBI), undesired UWB signals and tone/multi-tone noises. For this reason, research about NBI cancellation is still a challenge to improve the system performance vs. receiver complexity, power consumption, linearity, etc. In this work, the two major receiver sections, i.e., analog (radiofrequency or RF) and digital (digital signal processing or DSP), were considered and new techniques proposed to reduce circuit complexity and power consumption, while improving signal parameters. In the RF section, different multiband UWB low-noise amplifier key design parameters were investigated like circuit configuration, input matching and desired/undesired frequency band filtering, highlighting the most suitable filtering package for efficient UWB NBI cancellation. In the DSP section, due to pulse transmitter signals, different issues like modulation type and level, pulse variety, shape and color noise/tone noise assumptions, were addressed for efficient NBI cancelation. A comparison was performed in terms of bit-error rate, signal-to-interference ratio, signal-to-noise ratio, and channel capacity to highlight the most suitable parameters for efficient DSP design. The optimum number of filters that allows the filter bandwidth to be reduced by following the required low sampling rate and thus improving the system bit error rate was also investigated.
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Öresjö, Per. "A High Speed Sigma Delta A/D-Converter for a General Purpose RF Front End in 90nm-Technology." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8706.
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In this report a transistor-level design of a GHz Sigma-Delta analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational amplifiers.
The clock frequency used for verification was 2.5 GHz and the output band-width was 10 MHz. The system is flexible in that the number of internal bits can be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB as well as a four-bit system yielding an SNR of 82.5 dB are analyzed.
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VIJAY, VIKAS. "A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283.
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Alam, Shaikh Md Khairul. "A CMOS front end for high linearity zero-if WCDMA receiver." The Ohio State University, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=osu1164834218.
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Xiong, Botao [Verfasser], Klaus [Akademischer Betreuer] Hofmann, and Thomas [Akademischer Betreuer] Hollstein. "Digitally assisted analog electronics: trade-offs and applications on mixed signal and RF front-ends / Botao Xiong ; Klaus Hofmann, Thomas Hollstein." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2017. http://d-nb.info/1135386056/34.
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Arora, Rajan. "Trade-offs between performance and reliability of sub 100-nm RF-CMOS technologies." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50140.
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The objective of this research is to develop an understanding of the trade-offs between performance and reliability in sub 100-nm silicon-on-insulator (SOI) CMOS technologies. Such trade-offs can be used to demonstrate high performance reliable circuits in scaled technologies. Several CMOS reliability concerns such as hot-carrier stress, ionizing irradiation damage, RF stress, temperature effects, and single-event effects are studied. These reliability mechanisms can cause temporary or permanent damage to the semiconductor device and to the circuits using them. Several improvements are made to the device layout and process to achieve optimum performance. Parasitics are shown to play a dominant role in the performance and reliability of sub 100-nm devices. Various techniques are suggested to reduce these parasitics, such as the use of the following: a) optimum device-width, b) optimum gate-finger to gate-finger spacing, c) optimum source/drain metal contact spacing, and d) floating-body/body-contact. The major contributions from this research are summarized as follows: 1) Role of floating-body effects on the performance and reliability of sub 100-nm CMOS-on-SOI technologies is investigated for the first time [1], [2]. It is demonstrated through experimental data and TCAD simulations that floating-body devices have improved RF performance but degraded reliability compared to body-contacted devices. 2) Floating-body effects in a cascode core is studied. Cascode cores are demonstrated to achieve much larger reliability lifetimes than a single device. A variety of cascode topologies are studied to achieve the trade-o s between performance and reliability for high-power applications [2]. 3) The use of body-contact to modulate the performance of devices and single-poledouble- throw (SPDT) switches is studied. The SPDT switch performance is shown to improve with a negative body-bias. 4) The impact of device width on the RF performance and reliability is studied. Larger width devices are shown to have greater degradation, posing challenging questions for RF design in strained-Si technologies [3]. 5) A novel study showing the e ect of source/drain metal contact spacing and gate-finger to gate-finger spacing on the device RF performance is carried out. Further, the impact of above on the hot-carrier, RF stress, and total-dose irradiation tolerance is studied [3], [4]. 6) Latchup phenomenon in CMOS is shown to be possible at cryogenic temperatures (below 50 K), and its consequences are discussed [5]. 7) A time-dependent device degradation model has been developed in technology computer aided design (TCAD) to model reliability in CMOS and SiGe devices. 8) The total-dose irradiation tolerance and hot-carrier reliability of 32-nm CMOSon- SOI technology is reported for the first time. The impact of HfO2 based gate dielectric on the performance and reliability is studied [6]. 9) The impact of technology scaling from 65-nm to 32-nm on the performance and reliability of CMOS technologies is studied [6]. 10) Cryogenic performance and reliability of 45-nm nFETs is investigated. The RF performance improves significantly at 77 K. The hot-carrier device reliability is shown to improve at low temperatures in short-channel CMOS technologies.
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Thomsson, Pontus, and Aghamiri Cyrus Seyed. "Design of a 16 GSps RF Sampling Resistive DAC with on-chip Voltage Regulator." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-177548.
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Wireless communication technologies continue to evolve to meet the demand for increased data throughput. To achieve higher data throughput one approach is to increase the bandwidth. One problem related to very large bandwidths is the implementation of digital-to-analog converters with sampling rates roughly in the 5 to 20 GHz range. Traditionally, current-steering data converters have been the go-to choice but their linearity suffers at higher frequencies. An alternative to the current-steering digital-to-analog converter is the voltage-mode digital-to-analog converter, which is an attractive option for integration into digital intensive application-specific integrated circuits due to its digital-in-nature architecture. In this thesis, a resistive voltage-mode digital-to-analog converter with an integrated low-dropout voltage regulator is proposed for a sampling rate of 16 GSps. The proposed resistive voltage-mode digital-to-analog converter with an output impedance matched to a 100 Ω load, achieves a spurious-free dynamic range of 64 dBc and intermodulation distortion of 66 dBc for output frequencies up to 5.5 GHz in the worst process corner.
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Chamas, Ibrahim. "The Analysis and Design of Phase-tunable Low-Power Low-Phase-Noise I/Q Signal Sources for Analog Phase Calibrated Transceivers." Diss., Virginia Tech, 2008. http://hdl.handle.net/10919/102076.
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Due to the demand for low-cost, small-form factor and large-scale integration of system-on-chip wireless transceivers, the image-reject, zero-IF and low-IF receiver architectures have become the main topologies used in mainstream wireless communication systems. Consequently, signal sources with quadrature phase outputs [quadrature oscillators (QOs)] are therefore essential, and their phase noise, driving capability, tuning range, oscillation frequency, and power consumption have a major impact on the overall receiver performance. Additionally, it is required that the QO synthesize precise I/Q waveforms across the signal bandwidth over process, voltage, and temperature variations for adequate image-rejection and signal modulation/demodulation. While the use of symmetrical layout and large inter-digitated devices minimize both systematic and random mismatches, this solution alone may not succeed in achieving the stringent performance requirements dictated by modern wireless standards particularly as the technology scales into the sub-100nm regime, necessitating both phase and gain calibration of the mismatched I/Q channels post-fabrication. Given the necessity for precise RF quadrature signal synthesis, the goal of this work is to investigate low-power low-phase-noise quadrature oscillator (QVCO) topologies with an integrated phase calibration feature.
The first part of this work focuses on the analysis and modeling of cross-coupled LC QVCOs. The analysis focuses on understanding the oscillator basic performance characteristics, design trade-offs, phase-noise performance, effect of including phase shift in the coupling paths, and on examining the quadrature accuracy in presence of process variations. New design parameters and circuit insight are developed and a generalized first order linear model and a one-port model are proposed. Particularly, we introduce the concept of an effective core and coupling transconductances to explain various oscillator properties. Additionally, a new incremental circuit element — the quadrature resistance — is introduced to evaluate the effect of coupling on the open-loop quality factor and hence on the oscillator phase noise performance. Mechanisms affecting the mode selectivity are identified and modeled. A qualitative and quantitative study of the effect of mismatch on the phase imbalance and amplitude error is presented. Particularly, closed-form intuitive expressions of the phase imbalance and amplitude error are derived and verified via circuit simulation.
Based on our understanding of the various mechanisms affecting the quadrature accuracy, the second part of this work introduces a very efficient quadrature phase calibration technique based on the disconnected-source parallel-coupled LC QVCO topology. The phase-tunable LC QVCO (PT-QVCO) achieves an ultra-wide I/Q phase tuning range without affecting the relative amplitude error or consuming additional power or chip area. Additionally, in restoring the phase balance, it is observed that the proposed method restores the phase noise performance to its optimal value which presents a potential advantage over classical calibration techniques. Time domain measurements performed on a 5 GHz prototype show that I/Q signals with phase error up to ~±30°, beyond which the VCO cores are unlocked, can be driven to perfect quadrature phase. The PT-QVCO can be tuned from 3.87-4.45 GHz at the negative mode and 4.4-5.4 GHz at the positive mode, a total of ~1.5 GHz. The fabricated circuit including pad structures occupies an area of 1.1x0.7 mm² and drains 18mW (excluding buffer circuits) from a 1.8 V supply voltage.
The third part of this work introduces a new low-power, low-phase-noise super harmonic injection-coupled LC QVCO (IC-QVCO) topology. Analysis of the waveform accuracy reveals an inverse dependence of the quadrature error on the tank quality factor thus allowing circuit optimization for both low phase noise and precise quadrature synthesis. Additionally, a tunable tail filter (TTF) is incorporated to calibrate the residual quadrature imbalance in presence of a 3-σ variation in the device parameters. An X-band IC-QVCO prototype with a TTF implemented in a 0.18μm RF CMOS process, achieves a measured phase noise figure-of-merit ranging from 177.3 to 182.6 dBc/Hz along the 9.0 to 9.6 GHz frequency tuning range while dissipating only 9mW from the 1.8V supply. The TTF reduces both the 1/f² and 1/f³ phase noise and calibrates the residual phase error within ±11° post-fabrication without affecting the relative amplitude error or the phase noise performance. The circuit performance compares favorably with recently published work.
In the fourth part of this work, we explore the implementation of LC QVCOs as potential I/Q sources at millimeter-wave (MMW) frequencies. Among the several design challenges that emerge as the oscillator frequency is scaled into the MMW band, precise quadrature synthesis and adequate frequency tuning range are among the hardest to achieve. After describing the limitation of using an MOS varactor and a digitally controlled switch capacitor array for frequency tuning, we propose an alternative frequency tuning technique based on the fundamental operation of LC QVCOs. The off-resonance operation, which is defined by the coupling network, suggests varying the coupling current to achieve frequency tuning. In essence, by modifying the bias current of the coupling transistors (GMc-tuning), a wide and linear frequency tuning range can be achieved. Extensive simulation results of a 60 GHz prototype, implemented in a 90 nm commercial RF CMOS process, demonstrates a 5 GHz of frequency tuning range (57.5 GHz → 62.5 GHz), a tuning sensitivity of 1GHz/mA, and a 4dB improvement in the phase noise compared to a varactor solution.
Finally, the Appendix includes recent research work on the analysis and design of gPh.D.
While resting in bed due to illness, the Dutch scientist Christiaan Huygens keenly observed that the pendulums of two clocks hanging on the wall moved synchronously when the clocks were hung close to each other. He concluded that these two oscillatory systems were forced to move in unison by virtue of mechanical coupling through the wall. In essence, each pendulum injected mechanical vibrations into the wall that was strong enough to lock the adjacent pendulum into synchronous motion. Injection locking of oscillatory systems plays a critical role in communication systems ranging from frequency division, to generating clocks (oscillators) with finer phase separation, to the synthesis of orthogonal (quadrature) clocks. All communication systems have the same basic form. Firstly, there will some type of an information or data source which can be a keyboard or a microphone in a smartphone. The source is connected to a receiver by some sort of a channel. In wireless systems, the channel is the air medium. Moreover, to comply with the FCC and 3GPP requirements, data can only be transmitted wirelessly within a predefined set of frequencies and with stringent emission requirements to avoid interference with other wireless systems. These frequencies are generated by high fidelity clock sources, also known as oscillators. Consider a group of people sharing the same room and hence the same channel want to share information. Without regulating the “loudness” of each communicating ensemble, the quality of communication can be severely impaired. Moreover, it is to be expected that information can be shared more efficiently if each pair is allocated non-overlapping timeslots – speak when others are quiet. Called time orthogonality, all wireless systems require precise orthogonal (quadrature) clock sources to improve the communication efficiency. The precision of quadrature clocks is determined by the amplitude and phase accuracy. This dissertation takes a deep dive into the analysis and implementation of high accuracy quadrature (I/Q) clock sources using the concept of injection locking. These I/Q clocks or oscillators, also known as quadrature voltage controlled oscillators (QVCOs), have gained enormous popularity in the last decade. The first part of this work focuses on the analysis and modeling of QVCOs. The analysis focuses on understanding the oscillator basic performance characteristics, and on examining the quadrature accuracy in presence of process variations. New design parameters and circuit insight are developed and a generalized first order linear model and a one-port model are proposed. A qualitative and quantitative study of the effect of mismatch on the phase imbalance and amplitude error is presented. Particularly, closed-form intuitive expressions of the phase imbalance and amplitude error are derived and verified via circuit simulation. Based on our understanding of the various mechanisms affecting the quadrature accuracy, the second part of this work introduces a very efficient quadrature phase calibration technique based The phase-tunable QVCO (PT-QVCO) achieves an ultra-wide I/Q phase tuning range without affecting the oscillator other performance metrics. The proposed topology was successfully verified in silicon using a 5GHz prototype. The third part of this work introduces a new low-power, low-phase-noise injection coupled QVCO (IC-QVCO) topology. An X-band IC-QVCO prototype was successfully verified in a 0.18m RF CMOS process. In the fourth part of this work, we explore the implementation of QVCOs as potential I/Q sources at millimeter-wave (MMW) frequencies. Among the several design challenges that emerge as the oscillator frequency is scaled into the MMW band, precise quadrature synthesis and adequate frequency tuning range are among the hardest to achieve. After describing the limitation of using an conventional frequency tuning techniques, we propose an alternative approach based on the fundamental operation of QVCOs that outperforms existing solutions.
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PATEL, VIPUL J. "BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065.
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Suenaga, Portuguès Kay. "Test estructural i predictiu per a circuits RF CMOS." Doctoral thesis, Universitat de les Illes Balears, 2008. http://hdl.handle.net/10803/9431.
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En aquesta tesi s'ha desenvolupat una tècnica de test que permet testar un LNA i un mesclador, situats en el capçal RF d'un receptor CMOS, en una configuració de test semblant al mode normal de funcionament.La circuiteria necessària per a implementar aquesta tècnica consta d'un generador IF, per a generar el senyal IF de test, i d'un mesclador auxiliar, per a obtenir el senyal RF de test.
Les observables de test escollides han estat l'amplitud de la tensió de sortida del mesclador i el component DC del corrent de consum.
S'ha estudiat l'eficàcia de la tècnica de test proposada utilitzant les estratègies de test estructural i predictiu, mitjançant simulacions i mesures experimentals. La seva eficàcia és comparable a altres tècniques de test existents, però l'àrea addicional dedicada a la circuiteria test és inferior.
En esta tesis se ha desarrollado una técnica de test que permite verificar un LNA y un mezclador, situados en el cabezal RF de un receptor CMOS, en una configuración de test similar al modo normal de funcionamiento.
Los circuitos necesarios para implementar esta técnica son: un generador IF, que permite generar la señal IF de test, y un mezclador auxiliar, para obtener la señal RF de test.
Las observables de test seleccionadas han sido la amplitud de la tensión de salida y la componente DC de la corriente de consumo.
Se ha estudiado la eficacia de la técnica propuesta usando las estrategias de test estructural y predictiva, mediante simulaciones y medidas experimentales. Su eficacia es comparable a otras técnicas existentes, pero el área dedicada a la circuiteria de test es inferior.
This PhD thesis develops a test technique intended for the RF front end of CMOS integrated receivers. This test technique allows testing individually the building blocks of the receiver in a sequential way. The test mode configuration of each block is similar to the normal mode operation.
The auxiliary circuitry required to generate the test stimuli consists of an IF generator, which generates the IF test signal, and an auxiliary mixer that produces the RF test signal by mixing the IF test signal with the local oscillator signal.
The test observables selected for the test are the voltage amplitude after the IF amplifier, and the DC component of the supply current in each block.
The capability of the proposed test technique to perform structural and predictive test strategies has been validated by simulation and experimentally. Its efficiency is comparable to other existing techniques, but the silicon area overhead is lower.
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Blom, Martin. "En oscillatorbank till en lågfrekvensradar : LORA/VHF." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2153.
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The goal of this thesis work is to enable an existing UHF radar to operate in the VHF band instead. In order to achieve this, new coherent local oscillators are required. Different options are suggested and one of them is implemented and analyzed.
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Akkouche, Nourredine. "Optimisation du test de production de circuits analogiques et RF par des techniques de modélisation statistique." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00625469.
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La part dû au test dans le coût de conception et de fabrication des circuits intégrés ne cesse de croître, d'où la nécessité d'optimiser cette étape devenue incontournable. Dans cette thèse, de nouvelles méthodes d'ordonnancement et de réduction du nombre de tests à effectuer sont proposées. La solution est un ordre des tests permettant de détecter au plus tôt les circuits défectueux, qui pourra aussi être utilisé pour éliminer les tests redondants. Ces méthodes de test sont basées sur la modélisation statistique du circuit sous test. Cette modélisation inclus plusieurs modèles paramétriques et non paramétrique permettant de s'adapté à tous les types de circuit. Une fois le modèle validé, les méthodes de test proposées génèrent un grand échantillon contenant des circuits défectueux. Ces derniers permettent une meilleure estimation des métriques de test, en particulier le taux de défauts. Sur la base de cette erreur, un ordonnancement des tests est construit en maximisant la détection des circuits défectueux au plus tôt. Avec peu de tests, la méthode de sélection et d'évaluation est utilisée pour obtenir l'ordre optimal des tests. Toutefois, avec des circuits contenant un grand nombre de tests, des heuristiques comme la méthode de décomposition, les algorithmes génétiques ou les méthodes de la recherche flottante sont utilisées pour approcher la solution optimale.
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Moon, Sung Tae. "Design of high performance frequency synthesizers in communication systems." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2329.
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Frequency synthesizer is a key building block of fully-integrated wireless communication
systems. Design of a frequency synthesizer requires the understanding of
not only the circuit-level but also of the transceiver system-level considerations. This
dissertation presents a full cycle of the synthesizer design procedure starting from the
interpretation of standards to the testing and measurement results.
A new methodology of interpreting communication standards into low level circuit
specifications is developed to clarify how the requirements are calculated. A
detailed procedure to determine important design variables is presented incorporating
the fundamental theory and non-ideal effects such as phase noise and reference
spurs. The design procedure can be easily adopted for different applications.
A BiCMOS frequency synthesizer compliant for both wireless local area network
(WLAN) 802.11a and 802.11b standards is presented as a design example. The two
standards are carefully studied according to the proposed standard interpretation
method. In order to satisfy stringent requirements due to the multi-standard architecture,
an improved adaptive dual-loop phase-locked loop (PLL) architecture is
proposed. The proposed improvements include a new loop filter topology with an
active capacitance multiplier and a tunable dead zone circuit. These improvements
are crucial for monolithic integration of the synthesizer with no off-chip components.
The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time
performance while making it more suitable for monolithic integration. It opens a
new possibility of using an integer-N architecture for various other communication
standards, while maintaining the benefit of the integer-N architecture; an optimal
performance in area and power consumption.
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Johansson, Mattias, and Jonas Ehrs. "Low-Power Low-Noise IQ Modulator Designs in 90nm CMOS for GSM/EDGE/WCDMA/LTE." Thesis, Linköping University, Department of Electrical Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-54552.
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The current consumption of the IQ modulator is a significant part of the totalcurrent consumption of a mobile transmitter platform and reducing it is of greatinterest. Also, as the WCDMA/LTE standards specifies full duplex transmissionsand Tx and Rx are most often using the same antenna, it is crucial to have asolution with low noise generation. Two new proposals have been studied with theaim to reduce the current consumption and noise contribution of the IQ modulator.
A current mode envelope tracking IQM is the first of the studied designs. Thisimplementation lowers the bias currents in the circuit in relation to the amplitudeof the baseband input signals, meaning that a low input amplitude results in alowering of the current consumption. It proves to be very efficient for basebandsignals with a high peak-to-average ratio. Simulations and calculations have shownthat an average current reduction of 56 % can be achieved for an arbitrary LTEbaseband signal.
The second is an entirely new passive mixer design where the baseband voltagesare sequentially copied to the RF node, removing the need for V-to-I conversion inthe mixer which reduces current consumption and noise. Results from simulationshas proven that this design is fully capable of improving both current consumptionas well as the noise levels. With an output power of 4.0 dBm, the power consumptionwas 43.3 mW, including clock generating circuits. This, combined with thefact that the design is small and simple, means that there is definitely a possibilityto replace the present IQM design with a passive mixer.
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Janicot, Vincent. "Simulation des circuits électroniques RF/Analogiques/Numériques excités par des signaux à modulation complexe." Phd thesis, Université Joseph Fourier (Grenoble), 2002. http://tel.archives-ouvertes.fr/tel-00004464.
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La taille, la complexité et les performances des circuits électroniques de télécommunication sont de plus en plus contraignantes tandis que le temps et le coût de commercialisation doivent être réduits au maximum. Voulant répondre au vide existant sur le marché de la CAO dans ce domaine, ce travail est consacré à la simulation mixte de systèmes de communication complets parcourus par des signaux numériques, des signaux analogiques basse-fréquence, des signaux quasi-périodiques et des signaux RF à modulation digitale complexe. Le premier chapitre du manuscrit présente les différents types de circuits et de signaux que l'on veut simuler. La deuxième partie décrit d'abord les principales méthodes de simulation RF existantes. On développe ensuite les innovations apportées à la méthode de l'Equilibrage Harmonique, basée sur une utilisation efficace du spectre, et enfin celles apportées à l'algorithme de l'Enveloppe. Le troisième chapitre propose une nouvelle méthodologie pour simuler des circuits complets RF/Analogiques/Numériques dans le cadre de l'algorithme de l'Enveloppe : couplage avec un simulateur numérique, prise en compte de modèles comportementaux et partition analogique/RF des circuits. Enfin, la dernière partie illustre les potentialités de cette nouvelle technique d'analyse sur quelques circuits typiques. Pour la première fois, des systèmes complexes mixtes, décrits aux niveaux logique, transistor et comportemental, peuvent être simulés dans un seul flot et dans des temps raisonnables.
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Oliveira, Vlademir de Jesus Silva [UNESP]. "Desenvolvimento de um sintetizador de freqüência de baixo custo em tecnologia CMOS." Universidade Estadual Paulista (UNESP), 2009. http://hdl.handle.net/11449/100280.
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Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS...
In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture
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Khereddine, Rafik. "Méthode adaptative de contrôle logique et de test de circuits AMS/FR." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00647169.
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Les technologies microélectroniques ainsi que les outils de CAO actuels permettent la conception de plus en plus rapide de circuits et systèmes intégrés très complexes. L'un des plus importants problèmes rencontrés est de gérer la complexité en terme de nombre de transistors présents dans le système à manipuler ainsi qu'en terme de diversité des composants, dans la mesure où les systèmes actuels intègrent, sur un même support de type SiP ou bien SoC, de plus en plus de blocs fonctionnels hétérogènes. Le but de cette thèse est la recherche de nouvelles techniques de test qui mettent à contribution les ressources embarquées pour le test et le contrôle des modules AMS et RF. L'idée principale est de mettre en oeuvre pour ces composantes des méthodes de test et de contrôle suffisamment simples pour que les ressources numériques embarquées puissent permettre leur implémentation à faible coût. Les techniques proposées utilisent des modèles de représentation auto-régressifs qui prennent en comptes les non linéarités spécifiques à ce type de modules. Les paramètres du modèle comportemental du système sont utilisés pour la prédiction des performances du système qui sont nécessaire pour l'élaboration de la signature de test et le contrôle de la consommation du circuit. Deux démonstrateurs ont été mis en place pour valider la technique proposée : une chaine RF conçue au sein du groupe RMS et un accéléromètre de type MMA7361L.