To see the other types of publications on this topic, follow the link: Analog circuit design.
Dissertations / Theses on the topic 'Analog circuit design'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 dissertations / theses for your research on the topic 'Analog circuit design.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Lui, Siu-hong. "Analog circuit design by nonconvex polynomial optimization two design examples /." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39557418.
Full text
2
Wang, Xiaoying [Verfasser]. "Analog Circuit Design Approaches / Xiaoying Wang." München : Verlag Dr. Hut, 2014. http://d-nb.info/1053859848/34.
Full text
3
Lui, Siu-hong, and 呂小康. "Analog circuit design by nonconvex polynomial optimization: two design examples." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39557418.
Full text
4
Seda, Steven J. "Symbolic analysis for analog circuit design automation /." Zürich, 1993. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=10058.
Full text
5
Odame, Kofi. "Exploiting device nonlinearity in analog circuit design." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29751.
Full textAbstract:
Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Butera, Robert; Committee Member: Minch, Bradley; Committee Member: Taylor, David. Part of the SMARTech Electronic Thesis and Dissertation Collection.
6
Hu, Zongqi. "Analog integrated circuit design of hypertrellis decoders /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20HU.
Full text
7
Hong, Seong-Kwan. "Performance driven analog layout compiler." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.
Full text
8
Bhattacharya, Sambuddha. "Template-driven parasitic-aware optimization of analog/RF IC layouts /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6121.
Full text
9
Luo, Ji. "Circuit design and routing for field programmable analog arrays." College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/3167.
Full textAbstract:
Thesis (Ph. D.) -- University of Maryland, College Park, 2005.Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
10
Serrano, Guillermo J. "High Performance Analog Circuit Design Using Floating-Gate Techniques." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19819.
Full textAbstract:
The programmability property of floating-gate transistors is exploited in this work to compensate for mismatch and device parameter variations in various high performance analog circuits. A careful look is taken at the characteristics and behavior of floating-gate transistors; issues such as programming, precision, accuracy, and charge retention are addressed. An alternate approach to reduce the offset voltage of the amplifier is presented. The proposed approach uses floating-gate transistors as programmable current sources that provide offset compensation while being a part of the amplifier of interest during normal operation. This results in an offset voltage cancelation that is independent of other amplifier parameters and does not dissipate additional power. Two compact programmable architectures that implement a voltage reference based on the charge difference between two floating-gate transistors are introduced. The references exhibit a low temperature coefficient (TC) as all the transistors temperature dependencies are canceled. Programming the charge on the floating-gate transistors provides the flexibility of an arbitrary accurate voltage reference with a single design and allows for a high initial accuracy of the reference. Also, this work presents a novel programmable temperature compensated current reference. The proposed circuit achieves a first order temperature compensation by canceling the negative TC of an on-chip poly resistor with the positive TC of a MOS transistor operating in the ohmic region. Programmability of the ohmic resistor enables optimal temperature compensation while programmability of the reference voltage allows for an accurate current reference for a wide range of values. Finally, this work combines the already established DAC design techniques with floating-gate circuits to obtain a high precision converter. This approach enables higher accuracy along with a substantial decrease of the die size.
11
Fei, Haibo. "High linearity analog and mixed-signal integrated circuit design." [Ames, Iowa : Iowa State University], 2007.
Find full text
12
Mitros, Piotr 1979. "Constraint satisfaction modules : a methodology for analog circuit design." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/42237.
Full textAbstract:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 119-122).
This dissertation describes a methodology for solving convex constraint problems using analog circuits. It demonstrates how this methodology can be used to design circuits that solve function-fitting problems through iterated gradient descent. In particular, it shows how to build a small circuit that can model a nonlinearity by observation, and predistort to compensate for this nonlinearity. The system fits into a broader effort to investigate non-traditional approaches to circuit design. First, it breaks the traditional input-output abstraction barrier; all ports are bidirectional. Second, it uses a different methodology for proving system stability with local rather than global properties. Such stability arguments can be scaled to much more complex systems than traditional stability criteria.
by Piotr Mitros.
Ph.D.
13
Patenaude, Jean-Marc G. (Jean-Marc Guy) Carleton University Dissertation Engineering Electronics. "A Methodology for analog circuit design and knowledge transfer." Ottawa, 1996.
Find full text
14
Fayed, Ayman Adel. "Adaptive techniques for analog and mixed signal integrated circuits." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1097519730.
Full textAbstract:
Thesis (Ph. D.)--Ohio State University, 2004.Title from first page of PDF file. Document formatted into pages; contains xix, 232 p.; also includes graphics (some col.). Includes bibliographical references (p. 222-230).
15
Cheung, Wing-tai. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39558526.
Full text
16
Xia, Bo. "Analog-to-digital interface design in wireless receivers." Texas A&M University, 2004. http://hdl.handle.net/1969.1/3260.
Full textAbstract:
As one of the major building blocks in a wireless receiver, the Analog-to-Digital Interface (ADI) provides link and transition between the analog Radio Frequency (RF) frontend and the baseband Digital Signal Processing (DSP) module. The rapid development of the radio technologies raises new design challenges for the receiver ADI implementation. Requirements, such as power consumption optimization, multi-standard compatibility, fast settling capability and wide signal bandwidth capacity, are often encountered in a low voltage ADI design environment. Previous research offers ADI design schemes that emphasize individual merit. A systematic ADI design methodology is, however, not suffciently studied. In this work, the ADI design for two receiver systems are employed as research vehicles to provide solutions for different ADI design issues.
A zero-crossing demodulator ADI is designed in the 0.35µm CMOS technology for the Bluetooth receiver to provide fast settling. Architectural level modification improves the process variation and the Local Oscillation (LO) frequency offset immunity of the demodulator. A 16.2dB Signal-to-Noise Ratio (SNR) at 0.1% Bit Error Rate (BER) is achieved with less than 9mW power dissipation in the lab measurement. For ADI in the 802.11b/Bluetooth dual-mode receiver, a configurable time-interleaved pipeline Analog-to-Digital-Converter (ADC) structure is adopted to provide the required multi-standard compatibility. An online digital calibration scheme is also proposed to compensate process variation and mismatching. The prototype chip is fabricated in the 0.25µm BiCMOS technology. Experimentally, an SNR of 60dB and 64dB are obtained under the 802.11b and Bluetooth receiving modes, respectively. The power consumption of the ADI is 20.2mW under the 802.11b receiving mode and 14.8mW under the Bluetooth mode.
In this dissertation, each step of the receiver ADI design procedure, from system level optimization to the transistor level implementation and lab measurement, is illustrated in detail. The observations are carefully studied to provide insight on receiver ADI design issues. The ADI design for the Ultra-Wide Band (UWB) receiver is also studied at system level. Potential ADI structure is proposed to satisfy the wide signal bandwidth and high speed requirement for future applications.
17
Le, Huy X. P. "Characterization of hot-carrier reliability in analog sub-circuit design." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/41379.
Full textAbstract:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.Includes bibliographical references (leaves 52-54).
by Huy X.P. Le.
M.Eng.
18
Monzon, Joshua Jen C. "Analog VLSI circuit design of spike-timing-dependent synaptic plasticity." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/54636.
Full textAbstract:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 61-63).
Synaptic plasticity is the ability of a synaptic connection to change in strength and is believed to be the basis for learning and memory. Currently, two types of synaptic plasticity exist. First is the spike-timing-dependent-plasticity (STDP), a timing-based protocol that suggests that the efficacy of synaptic connections is modulated by the relative timing between presynaptic and postsynaptic stimuli. The second type is the Bienenstock-Cooper-Munro (BCM) learning rule, a classical ratebased protocol which states that the rate of presynaptic stimulation modulates the synaptic strength. Several theoretical models were developed to explain the two forms of plasticity but none of these models came close in identifying the biophysical mechanism of plasticity. Other studies focused instead on developing neuromorphic systems of synaptic plasticity. These systems used simple curve fitting methods that were able to reproduce some types of STDP but still failed to shed light on the biophysical basis of STDP. Furthermore, none of these neuromorphic systems were able to reproduce the various forms of STDP and relate them to the BCM rule. However, a recent discovery resulted in a new unified model that explains the general biophysical process governing synaptic plasticity using fundamental ideas regarding the biochemical reactions and kinetics within the synapse. This brilliant model considers all types of STDP and relates them to the BCM rule, giving us a fresh new approach to construct a unique system that overcomes all the challenges that existing neuromorphic systems faced. Here, we propose a novel analog verylarge- scale-integration (aVLSI) circuit that successfully and accurately captures the whole picture of synaptic plasticity based from the results of this latest unified model. Our circuit was tested for all types of STDP and for each of these tests, our design was able to reproduce the results predicted by the new-found model. Two inputs are required by the system, a glutamate signal that carries information about the presynaptic stimuli and a dendritic action potential signal that contains information about the postsynaptic stimuli. These two inputs give rise to changes in the excitatory postsynaptic current which represents the modifiable synaptic efficacy output. Finally, we also present several techniques and alternative circuit designs that will further improve the performance of our neuromorphic system.
by Joshua Jen C. Monzon.
M.Eng.
19
Pradhan, Almitra. "Accurate Analog Synthesis Based On Circuit Matrix Models." University of Cincinnati / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1258661691.
Full text
20
Su, Wenjun. "Design and development of high CMRR wide bandwidth instrumentation amplifiers." Thesis, Oxford Brookes University, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.364097.
Full text
21
Gay, Nicolas [Verfasser]. "Analog Circuit Design based on Organic Field-Effect Transistors / Nicolas Gay." Aachen : Shaker, 2007. http://d-nb.info/1166509966/34.
Full text
22
張永泰 and Wing-tai Cheung. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39558526.
Full text
23
Sobe, Udo, Karl-Heinz Rooch, and Dietmar Mörtl. "Simulation and Analysis of Analog Circuit and PCM (Process Control Monitor) Test Structures in Circuit Design." Universitätsbibliothek Chemnitz, 2007. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200700919.
Full textAbstract:
PCM test structures are commonly used to check the produced wafers from the standpoint of the technologist. In general
these structures are managed inside the FAB and are focused on standard device properties. Hence their development and
analysis is not driven by analog circuit blocks, which are sensitive or often used. Especially for DFM/Y of analog circuits
the correlation between design and technology has to be defined. The knowledge of electrical behavior of test structures
helps to improve the designer's sensitivity to technological questions.
This paper presents a method to bring the PCM methodology into the analog circuit design to improve design performance,
yield estimation and technology correlation. We show how both analog circuit and PCM blocks can be simulated and
analyzed in the design phase.
24
Zhang, Chenglong. "LOW-POWER LOW-VOLTAGE ANALOG CIRCUIT TECHNIQUES FOR WIRELESS SENSORS." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/982.
Full textAbstract:
This research investigates lower-power lower-voltage analog circuit techniques suitable for wireless sensor applications. Wireless sensors have been used in a wide range of applications and will become ubiquitous with the revolution of internet of things (IoT). Due to the demand of low cost, miniature desirable size and long operating cycle, passive wireless sensors which don't require battery are more preferred. Such sensors harvest energy from energy sources in the environment such as radio frequency (RF) waves, vibration, thermal sources, etc. As a result, the obtained energy is very limited. This creates strong demand for low power, lower voltage circuits. The RF and analog circuits in the wireless sensor usually consume most of the power. This motivates the research presented in the dissertation. Specially, the research focuses on the design of a low power high efficiency regulator, low power Resistance to Digital Converter (RDC), low power Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with parasitic error reduction and a low power low voltage Low Dropout (LDO) regulator. This dissertation includes a low power analog circuit design for the RFID wireless sensor which consists of the energy harvest circuits (an optimized rectifier and a regulator with high current efficiency) and a sensor measurement circuit (RDC), a single end sampling SAR ADC with no error induced by the parasitic capacitance and a digital loop LDO whose line and load variation response is improved. These techniques will boost the design of the wireless sensor and they can also be used in other similar low power design.
25
Shana'a, Osama K. "Circuit Implementation of a High-speed Continuous-time Current-mode Field Programmable Analog Array (FPAA)." PDXScholar, 1996. https://pdxscholar.library.pdx.edu/open_access_etds/5103.
Full textAbstract:
The growing interest in programmable analog circuits has led to the development of Field Programmable Analog Arrays (FPAAs). An FPAA consists of: 1) a programmable cell that can be reconfigured to perform several analog functions. 2) an architecture that interconnects a number of copies of the programmable cell. In this thesis, the full monolithic circuit implementation of the analog part of the programmable cell is presented. Chapter I gives an introduction to the idea of FPAA and introduces the FPAA architecture and the cell block diagram. Chapter II deals with the design and verification of a differential current-mode four-quadrant multiplier. The weighting-summing circuit with the normalizing stage is discussed in Chapter III. Chapter IV presents the design of a current-mode low-voltage programmable integratorgain circuit. Programmability was achieved by changing the bias current in the designed circuits; no analog switches were used in the signal path. This shows no effect on the performance of the circuits. The presented programming method, however, relies on the availability of a programmable current source with a storage capability. The design of this current source is discussed in chapter V. Conclusions are summarized in Chapter VI. The presented designs throughout the whole thesis were supported by detailed analytical derivations with the necessary SPICE simulations to verify the performance.
26
Ozalevli, Erhan. "Exploiting Floating-Gate Transistor Properties in Analog and Mixed-Signal Circuit Design." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14048.
Full textAbstract:
With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment.
Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques.
These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented
in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic
architecture.
27
Wemple, Ivan L. "Parasitic substrate modeling for monolithic mixed analog/digital circuit design and verification /." Thesis, Connect to this title online; UW restricted, 1996. http://hdl.handle.net/1773/5944.
Full text
28
Ale, Anil Kumar. "Comparison and Evaluation of Existing Analog Circuit Simulator using Sigma-Delta Modulator." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5422/.
Full textAbstract:
In the world of VLSI (very large scale integration) technology, there are many different types of circuit simulators that are used to design and predict the circuit behavior before actual fabrication of the circuit. In this thesis, I compared and evaluated existing circuit simulators by considering standard benchmark circuits. The circuit simulators which I evaluated and explored are Ngspice, Tclspice, Winspice (open source) and Spectre® (commercial). I also tested standard benchmarks using these circuit simulators and compared their outputs. The simulators are evaluated using design metrics in order to quantify their performance and identify efficient circuit simulators. In addition, I designed a sigma-delta modulator and its individual components using the analog behavioral language Verilog-A. Initially, I performed simulations of individual components of the sigma-delta modulator and later of the whole system. Finally, CMOS (complementary metal-oxide semiconductor) transistor-level circuits were designed for the differential amplifier, operational amplifier and comparator of the modulator.
29
Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.
Full textAbstract:
The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.
30
Hernandez, Garduno David. "Analog integrated circuit design techniques for high-speed signal processing in communications systems." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1104.
Full text
31
Huynh, Sam DuPhat. "Testability analysis for mixed analog/digital circuit test generation and design for test /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6134.
Full text
32
Rohrer, Todd Edward Bloomquist. "An Electrometer Design and Characterization for a CubeSat Neutral Pressure Instrument." Thesis, Virginia Tech, 2017. http://hdl.handle.net/10919/74916.
Full textAbstract:
Neutral gas pressure measurements in low Earth orbit (LEO) can facilitate the monitoring of atmospheric gravity waves, which can trigger instabilities that severely disrupt radio frequency communication signals. The Space Neutral Pressure Instrument (SNeuPI) is a low-power instrument detecting neutral gas density in order to determine neutral gas pressure. SNeuPI consists of an ionization chamber and a logarithmic electrometer circuit. The Rev. 1 SNeuPI electrometer prototype does not function as designed. A Rev. 2 electrometer circuit must be designed and its performance characterized across specified operating temperature and input current ranges.
This document presents a design topology for the Rev. 2 electrometer and a derivation of the theoretical circuit transfer function. Component selection and layout are discussed. A range of predicted operating input currents is calculated using modeled neutral density data for a range of local times, altitudes, and latitudes corresponding to the conditions expected for the Lower Atmosphere/Ionosphere Coupling Experiment (LAICE) CubeSat mission. Laboratory test setups for measurements performed both under vacuum and at atmospheric pressure are documented in detail. Test procedures are presented to characterize the performance of the Rev. 2 electrometer at a range of controlled operating temperatures. The results of these tests are then extrapolated in order to predict the operation of the circuit at specified temperatures outside of the range controllable under laboratory test conditions. The logarithmic conformance, accuracy, sensitivity, power consumption, and deviations from expected response of the circuit are characterized. The results validate the electrometer for use under its expected flight conditions.Master of Science
33
Brenneman, Cody R. "Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-theses/423.
Full textAbstract:
As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.
34
huang, chfa, and 黃志發. "Analog filter circuit design." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/43740565617656547156.
Full textAbstract:
碩士國立中興大學
電機工程學系
91
This thesis described the design and implementation of analog filter design. We use non-opamp-based unity gain buffer to construct high-speed filter architecture. The experiment result show that we can arrive the cutoff frequency about 200Mhz.We also realize Gm-C filter with GaAs HBT technology. A high linear transconductance is used by 4:1 emitter ratio topology and we use negative resistance to improve the output impedance of transconductance. The measurement result show that we realize a 3rd order Butterworth filter by cascading method .The cutoff frequency is about 10Mhz.We also use LC ladder signal-flow to realize 5th order Elliptic filter, which is suit for baseband frequency application. The transconductance is realized in rail-to-rail topology. In the chapter six we will realize a polyphase filter to reject the image signal . The principle of a polyphase filter is different to symmetric analog filter .We use the transformation from LP to BP to realize the image rejection. The measured results verify our design and implementation of analog filter . They also provide theory and implementation
35
Liang, Guojin. "Current mode analog and digital circuit design." Thesis, 1990. http://hdl.handle.net/1957/37923.
Full textAbstract:
In this dissertation, two important current mode circuit design subjects have
been explored. In the first part, the switched-current circuit technique has been
investigated. The fundamental performance and limitations of this technique are
explored. One of the major limitations, the signal distortion caused by clock
feedthrough has been substantially reduced by a newly developed clock
feedthrough cancellation technique. In addition, a filter synthesis technique has
been developed by directly simulating the structure of digital filter. Several
experimental CMOS prototypes have been designed and fabricated. The measured
frequency and phase responses demonstrated the feasibility of this synthesis
technique. In the second part, a new logic family called current-steering logic has
been developed. The fundamental performance and characteristics of this technique
have been discussed including the basic inverter and NOR gate with DC analysis,
transient analysis and power-delay product. It has been shown that the current-steering
logic has, a much smaller current spike than conventional CMOS logic
circuits, which is especially desirable in mixed-mode applications. Several
experimental prototypes have verified the functionality and performance of this new
technique.Graduation date: 1991
36
Silva, Bruno. "Analog Circuit Design With Transparent Electrics." Dissertação, 2013. http://hdl.handle.net/10216/75619.
Full text
37
Hsu, Chun-Chen, and 許鈞程. "CMOS Analog Circuit Layout Design Automation." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/62541285242114704365.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
91
Layout design is a very important step in the analog CMOS IC design flow. Good layout quality should feature low susceptibility to digital noise and low sensitivity to process variation. It has historically been a time-consuming, manual task. The fast growth of complexity of VLSI systems and recent advances in System-On-Chip (SOC) developments, make it necessary to have powerful Computer-Aided-Design (CAD) tools to speed up the design process. This issue is especially important for analog circuit layout design. In this thesis, we present a tool to automate analog layout design with analog basic considerations (matching, symmetry, and noise coupling). It covers from device level module generation to block level placement and routing. Fist, we provide a module generator to transfer partitioned netlists to physical layout with matching consideration. Placement tool then places all cells with symmetric, wire length, and area constraints. Obstacle-avoiding shortest finding algorithm is used for our basic routing algorithm and we propose an approach to avoiding noise coupling between noisy and sensitive nets. According to experimental results, our tool can handle analog circuit layout with user specified constraints in the reasonable time and make analog layout design more efficient.
38
Silva, Bruno Filipe Guedes da. "Analog Circuit Design With Transparent Electrics." Master's thesis, 2013. https://repositorio-aberto.up.pt/handle/10216/67737.
Full text
39
Silva, Bruno Filipe Guedes da. "Analog Circuit Design With Transparent Electrics." Dissertação, 2013. https://repositorio-aberto.up.pt/handle/10216/67737.
Full text
40
LU, CHAO-YING, and 呂昭穎. "Analog circuit design automation for operatioanl amplifier." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/5pvfz5.
Full textAbstract:
碩士國立臺北科技大學
電子工程系
107
In this paper we will discuss how to automate the analog circuit design of an op amp. Automation will be divided into using the annealing algorithm to find solutions, and using the scripting language Tcl script for program control. In circuit design, we will discuss the operation. The theoretical specifications of the amplifier, which will help to achieve better results for the convergence of the entire algorithm in the subsequent automation, while the circuit design automation uses Neocircuit and Cadence Spectre. We hope that through this automated process, multiple available results can be automatically generated, so that other analog circuits can be found in an op amp-related application. We finally succeeded in producing a number of available operational amplifiers, each with a different specification. The gain can be as high as 130 dB or the current consumption of some specifications is as low as 700 uA. In the end of this paper, we will compare the results produced and compare the time taken to obtain the results under different methods.
41
"Placement techniques in automatic analog layout generation." Thesis, 2012. http://library.cuhk.edu.hk/record=b5549170.
Full textAbstract:
模擬電路版圖設計是一個非常複雜和耗時的過程。通常情況下，設計一個高質量的模擬電路版圖需要電子工程師花費幾週甚至更長的時間。模擬電路的電子特性對於電路的細節設計非常敏感，因此，減小電路中的失配現象成為模擬電路版圖設計中一個非常重要的課題。在本論文中，我們提出了一系列實際的佈局技術，來降低電路的失配並提高繞線的成功率。我們可以非常容易的將這些技術整合至一個完整的模擬佈局和佈線的工具中，此工具可以在幾分鐘內生成一個完整的、高質量的模擬電路版圖。同時，該版圖能夠通過設計規則驗證（DRC）和佈局與電路設計一致性檢測（LVS）。模擬結果顯示，它的電路性能能夠與達到甚至超出手工設計的電路版圖。我們的論文主要作出了以下兩方面貢獻。
1. 平衡佈局：對於模擬電路中的電子元器件，如電容、電阻、晶體管等進行一維和二維的平衡佈局。電子工程師可以根據不同的設計需求，通過選擇不同的佈局參數來改變電路的佈局排列方式。同時，在模擬退火算法中，我們著重考慮了器件間的匹配以生成高質量的模擬電路佈局。
2. 消除阻塞的電路佈局：在模擬電路設計中，我們期望盡量避免在電子元器件密度較高的區域進行繞線。因此，我們需要在電路佈局設計過程中在電子元器件間留有足夠的佈線空間。為達到這個目標，我們提出了更精確的阻塞估計方法和版圖拓展方法，使其能夠生成一個高質量、高繞線成功率的電路佈局結果。
為了驗證生成的電路版圖的質量和匹配特性，我們利用蒙地卡羅方法來模擬電路中的製程偏差和失配特性。實驗結果顯示，我們的工具可以在幾分鐘內自動生成高質量的電路版圖，與人工設計通常需要花費數日至數週相比，設計時間大幅縮短，同時電路的匹配特性得以提升。
Analog layout design is a complicated and time-consuming process. It often takes couples of weeks for the layout designers to generate a qualied layout. The elec-trical properties of analog circuit are very sensitive to the layout details, and mis-match reduction becomes a very important issue in analog layout design.
In this thesis, we will present some practical placement techniques to reduce mismatch and improve routability. These techniques can be easily integrated into a complete analog placement and routing ow, which can produce in just a few min-utes a complete and high quality layout for analog circuits that passes the design rule check, layout-schematic check and with performance veried by simulations. The contents of this thesis will focus on the following two issues:
(1) Symmetry Placement: We consider symmetric placement of transistors, re-sistors and capacitors, which includes 1-D symmetry and 2-D symmetry (or called common centroid). Different symmetric placement congurations, derived accord-ing to the practical needs in analog design, are considered for the matching devices in the simulated annealing engine of the placer in order to generate a placement with high quality.
(2) Congestion-driven Placement: In analog design, wires are preferred not be routed over active devices, so we need to leave enough spaces properly for routing between the devices during the placement process. To achieve this, we explore congestion estimation and layout expansion during the placement step in order to produce a good and routable solution.
In order to verify the quality of the generated layouts in terms of mismatch, we will run Monte Carlo simulations on them with variations in process and mismatch. Experiments show that our methodology can generate high quality layout automatically in just a few minutes while manual design may take couples of days.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Cui, Guxin.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2012.
Abstracts also in Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Background --- p.1
Chapter 1.2 --- Physical Design --- p.2
Chapter 1.3 --- Analog Placement --- p.4
Chapter 1.3.1 --- Methodologies of Analog Placement --- p.4
Chapter 1.3.2 --- Symmetry Constraints of Analog Placement --- p.5
Chapter 1.4 --- Process Variation and Layout Mismatch --- p.6
Chapter 1.4.1 --- Process Variation --- p.6
Chapter 1.4.2 --- Random Mismatch and Systematic Mismatch --- p.7
Chapter 1.5 --- Monte Carlo Simulation Procedure --- p.9
Chapter 1.6 --- Problem Formulation of Placement --- p.9
Chapter 1.7 --- Motivations --- p.10
Chapter 1.8 --- Contributions --- p.11
Chapter 1.9 --- Thesis Organization --- p.12
Chapter 2 --- Literature Review on Analog Placement --- p.13
Chapter 2.1 --- Topological Representations Handling Symmetry Constraints --- p.14
Chapter 2.1.1 --- Symmetry within the Sequence-Pair (SP) Representation . --- p.14
Chapter 2.1.2 --- Block Placement with Symmetry Constraints Based on the O-Tree Non-Slicing Representation --- p.16
Chapter 2.1.3 --- Placement with Symmetry Constraints for Analog Layout Design Using TCG-S --- p.17
Chapter 2.1.4 --- Modeling Non-Slicing Floorplans with Binary Trees --- p.19
Chapter 2.1.5 --- Segment Trees Handle Symmetry Constraints --- p.20
Chapter 2.1.6 --- Center-based Corner Block List --- p.22
Chapter 2.2 --- Other Works on Analog Placement Constraints --- p.25
Chapter 2.2.1 --- Deterministic Analog Placement with Hierarchically Bounded Enumeration and Enhanced Shape Functions --- p.25
Chapter 2.2.2 --- Analog Placement Based on Symmetry-Island Formulation --- p.27
Chapter 2.2.3 --- Heterogeneous B*-Trees for Analog Placement with Symmetry and Regularity Considerations --- p.28
Chapter 2.3 --- Summary --- p.31
Chapter 3 --- Common-Centroid Analog Placement --- p.32
Chapter 3.1 --- Problem Formulation --- p.33
Chapter 3.2 --- Overview of Our Work --- p.35
Chapter 3.3 --- Handling Common Centroid Constraints in Different Devices --- p.37
Chapter 3.3.1 --- Common Centroid Placement of Resistors --- p.38
Chapter 3.3.2 --- Common Centroid Placement of Transistors --- p.44
Chapter 3.3.3 --- Common Centroid Placement of Capacitors --- p.47
Chapter 3.4 --- Congestion Estimation and Layout Expansion --- p.50
Chapter 3.4.1 --- Blockage-Aware Congestion Estimation --- p.51
Chapter 3.4.2 --- Layout Expansion --- p.56
Chapter 3.5 --- Simulated Annealing --- p.59
Chapter 3.5.1 --- Types of Moves --- p.59
Chapter 3.5.2 --- Handling Devices in Symmetry Group --- p.59
Chapter 3.5.3 --- Cost Function of Simulated Annealing --- p.61
Chapter 3.6 --- Summary --- p.62
Chapter 4 --- Experimental Results and Monte-Carlo Simulations --- p.64
Chapter 4.1 --- Study of Congestion-driven Layout Expansion --- p.64
Chapter 4.2 --- Monte Carlo Simulations --- p.70
Chapter 4.2.1 --- Devices Modeling --- p.70
Chapter 4.2.2 --- Study of Layouts with and without Symmetry Groups --- p.71
Chapter 4.2.3 --- Study of Layouts with and without Self-Symmetry Devices --- p.73
Chapter 4.2.4 --- Study of Layouts with Different Number of Symmetry Groups --- p.74
Chapter 4.2.5 --- Study of Large and Small Size Capacitors Array --- p.76
Chapter 4.3 --- Comparison of Automatic and Manual Layouts using Monte Carlo Simulations --- p.79
Chapter 5 --- Conclusion --- p.86
Bibliography --- p.87
42
Gupta, Rakhee. "Analog integrated circuit design using GaAs C-HFETs." Thesis, 1992. http://hdl.handle.net/1957/37042.
Full textAbstract:
Present day data processing technology requires very high speed signal processing and data conversion rates. One such application which requires high speed is switched capacitor circuits used in Sigma-Delta modulators. A major active component of switched capacitor circuits is the monolithic operational amplifier(opamp). Because of the relatively poor speed performance of the currently available silicon based technology, such high speed circuits can not be designed. GaAs technology appears to be a promising alternative technology for high speed switched capacitor circuits.
One problem with GaAs is the lack of complementary technology. Until now, most of the design of GaAs analog integrated circuits has been implemented using depletion mode n-MESFETs, where operational amplifiers and switched capacitors have been developed by various groups. This thesis develops the techniques for implementation of analog integrated circuits using complementary GaAs Heterojunction Field Effect Transistors(HFETs). Several operational amplifiers have been designed and their performance studied via simulation. The designs studied predict superior high frequency performance for C-HFETs over conventional GaAs MESFET and Silicon CMOS technology. The opamp designs are currently being implemented at Oregon State University for fabrication in the future.Graduation date: 1993
43
Elsayed, Mohamed. "Time-Mode Analog Circuit Design for Nanometric Technologies." Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10424.
Full textAbstract:
Rapid scaling in technology has introduced new challenges in the realm of traditional analog design. Scaling of supply voltage directly impacts the available voltage-dynamic-range. On the other hand, nanometric technologies with fT in the hundreds of GHz range open opportunities for time-resolution-based signal processing. With reduced available voltage-dynamic-range and improved timing resolution, it is more convenient to devise analog circuits whose performance depends on edge-timing precision rather than voltage levels. Thus, instead of representing the data/information in the voltage-mode, as a difference between two node voltages, it should be represented in time-mode as a time-difference between two rising and/or falling edges. This dissertation addresses the feasibility of employing time-mode analog circuit design in different applications. Specifically: 1) Time-mode-based quanitzer and feedback DAC of SigmaDelta ADC. 2) Time-mode-based low-THD 10MHz oscillator, 3) A Spur-Frequency Boosting PLL with -74dBc Reference-Spur Rejection in 90nm Digital CMOS.
In the first project, a new architectural solution is proposed to replace the DAC and the quantizer by a Time-to-Digital converter. The architecture has been fabricated in 65nm and shows that this technology node is capable of achieving a time-matching of 800fs which has never been reported. In addition, a competitive figure-of-merit is achieved.
In the low-THD oscillator, I proposed a new architectural solution for synthesizing a highly-linear sinusoidal signal using a novel harmonic rejection approach. The chip is fabricated in 130nm technology and shows an outstanding performance compared to the state of the art. The designed consumes 80% less power; consumes less area; provides much higher amplitude while being composed of purely digital circuits and passive elements.
Last but not least, the spur-frequency boosting PLL employs a novel technique that eliminates the reference spurs. Instead of adding additional filtering at the reference frequency, the spur frequency is boosted to higher frequency which is, naturally, has higher filtering effects. The prototype is fabricated in 90nm digital CMOS and proved to provide the lowest normalized reference spurs ever reported.
44
Yang, Chih-Hsiung, and 楊智雄. "Integration of RFID analog circuit and antenna design." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/88175471023113960601.
Full textAbstract:
碩士樹德科技大學
電腦與通訊研究所
95
In this thesis, we study the integration of analog circuit of radio frequency identification systems (RFID) and signal test for antennas of different size. RFID comprise tag, reader and antenna. The results of test of integration show the analog circuit is functioning. The reader of RFID system transports signal from the reader’s coil to the tag’s coil by EM coupling. If the dimension of these two coils is not compatible, the signal received by the tag will be weak. This is due to the coupling coefficient of the two coil is small. We propose an RFID system additionally comprises an intermediate device that includes a first and second antenna coils connected together in a close loop format. In this intermediate device, the first coil can be optimized for communication with a reader, while the second coil can be optimized for communication with a tag. By this configuration, the dimension of the reader antenna coil and the tag antenna coil can be completely independent of each other and still keep the transmission of signal fluent. The results indicate the transmission distance between tag and reader could be extend to about 30mm.
45
Chen, Chun-Hao, and 陳春豪. "Analog baseband circuit design for direct conversion receiver." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/17655369005105974293.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
91
This paper presents a circuit design and implantation for the analogous filter and amplifier sections of a direct conversion receiver. It is designed for 5GHz wireless LAN fabricated in a TSMC 0.35-µm SiGe BiCMOS technology. The design includes a first order low pass channel selection filter, a fifth order Butterworth filter, two stage programmable gain amplifiers (PGA), dc offset cancellation circuit, and a PTAT current source. The Gm-C channel selection filter can be programmable to two different bandwidths from 10 to 20MHz radio frequency (RF) spacing. The overall PGA varies from 8dB to 56dB with 2dB per step.
46
Wu, Jean Shin, and 吳建興. "The Circuit Design and Application in Analog Field." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/72367718382466596116.
Full text
47
Wang, Binan. "Device characterization and analog circuit design for heterojunction FETs." Thesis, 1993. http://hdl.handle.net/1957/37049.
Full textAbstract:
Present day data processing technology requires very high speed signal processing
and data conversion rates. Traditionally, these circuits have been implemented in silicon
MOS technology, whose high speed performance is limited, due to inherent material properties.
Though relatively immature compared to silicon technology, GaAs integrated circuit
technology appears to be a potential vehicle for realizing high-speed circuits because
of its high electron mobility and low parasitic capacitance. One major drawback of GaAs
technology has been the lack of complementary technology in contrast to silicon where
CMOS technology has greatly facilitated the development of analog ICs.
This thesis investigates the suitability of complementary GaAs Heterojunction FET
integrated circuit technology for the realization of high sample-rate switched-capacitor
circuits. In order to yield an accurate device model for the design work, model parameters
of both n and p GaAs Heterojunction FET devices are extracted from measurement results.
Based on the extraction results, a set of analog building blocks are presented. These
circuits include a high bandwidth operational amplifier and a fast settling switch which are
essential for high sample-rate circuits. A second order switched-capacitor low pass filter
sampling at a clock rate of 100MHz is designed using the above building blocks. The designs
studied predict better high frequency performance for C-HFETs compared to Si
CMOS technology.Graduation date: 1994
48
Yu, Jingjing. "Electromagnetic Interference (EMI) Resisting Analog Integrated Circuit Design Tutorial." Thesis, 2012. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11687.
Full textAbstract:
This work introduces fundamental knowledge of EMI, and presents three basic features correlated to EMI susceptibility: nonlinear distortion, asymmetric slew rate (SR) and parasitic capacitance. Different existing EMI-resisting techniques are analyzed and compared to each other in terms of EMI-Induced input offset voltage and other important specifications such as current consumption.
In this work, EMI-robust analog circuits are proposed, of which the architecture is based on source-buffered differential pair in the previous publications. The EMI performance of the proposed topologies has been verified within a test IC which was fabricated in NCSU 0.5um CMOS technology. Experimental results are presented when an EMI disturbance signal of 400mV and 800mV amplitude was injected at the input terminals, and compared with a conventional and an existing topology. The tested maximal EMI-induced input offset voltage corresponds to -222mV for the new structure, which is compared to -712mV for the conventional one and -368mV for the one using existing source-buffered technique in literature. Furthermore the overall performances of the circuits such as current consumption or input referred noise are also provided with the corresponding simulation results.
49
Shang-FuHsieh and 謝尚甫. "Analog Circuit and System Design for DC/AC Inverter." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/68893388614302608576.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
98
The research and invention of a DC/AC inverter controller chip for renewable sources generation system is presented in this thesis. It is different from the conventional approach which using microprocessor and discrete components for implementation. A novel solution is proposed for integrated circuit design of renewable sources generation system DC/AC inverter controller. The analog circuit is implemented with the simple control algorithm which is combined grid-connected mode and stand-alone mode control and reaches the high conversion efficiency and low current total harmonic distortion. It reduces the algorithm complexity, hardware cost and calculating operations. Unlike the circuits implemented for normal DC/DC converter, many innovative and high performance circuits are proposed for the purpose of solving the large voltage variation in output sinusoidal waveform. This work is designed for inverters operating in 200V input voltage. Further, the ultra high voltage BCD process can be combined with the proposed techniques in the future. The DC/AC inverter controller is fabricated by TSMC 0.18?m 1P6M 1.8V/3.3V Mixed-Signal CMOS process. The total die area is about 1x0.97mm2, which is smaller than the conventional approach by microprocessors. This inverter is expected to reach 96.5% conversion efficiency and 2.5% current total harmonic distortions. Compared with the state-of-the-art approaches, this work archives the smallest area, the lowest cost and best performance in the world.
50
Chuang, Kai-Hsiang, and 莊凱翔. "Analog Front-End Circuit Design for 10GBASE-T Ethernet." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/65527640507815318659.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
95
Since the Internet expands rapidly, the data rate of the local area network reaches 10 Gb/s. The optical systems with the data rate of 10 Gb/s have been proposed and implemented a few years ago. However, for the cost point of view, it is desired to implement the system with data rate of 10 Gb/s on the copper twisted-pair. In this thesis, an analog front-end circuit suitable for 10 GBASE-T Ethernet system has been designed and implemented using CMOS technology. The analog front-end circuit includes a baseline wander (BLW) cancellation loop, a programmable gain amplifier (PGA), a low-pass filter (LPF) and a gain amplifier. The baseline wander cancellation loop compensates the BLW by a feedback loop using a digital-to-analog converter (DAC). The programmable gain amplifier compensates the signal loss due to different channel length. The low-pass filter suppresses the alien crosstalk. The gain amplifier increases the overall gain of the entire analog front-end to satisfy the system requirement. Moreover, a frequency tuning loop which controls the frequency response of the low-pass filter is implemented in this design. The chip is fabricated using 0.18μm 1P6M CMOS technology. According to the post-layout simulations, this AFE has gain range from 4.9dB to 13.9dB with 1.5dB gain step and 293MHz bandwidth. The chip area is 0.88 x 0.82 mm2. The power consumption is 48mW under 1.8 V supply voltage. The chip is designed and verified with post-layout simulations. Testing considerations and experimental results are also presented.