Journal articles: 'Analog circuit design'

1

Hurst, S. L. "Analog circuit design." Microelectronics Journal 28, no. 2 (February 1997): 200–201. http://dx.doi.org/10.1016/s0026-2692(97)83458-1.

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Stojcev, M. "Analog circuit design." Microelectronics Journal 29, no. 12 (December 1998): 1039–40. http://dx.doi.org/10.1016/s0026-2692(98)00057-3.

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WANG, WEIZHI, and DONGMING JIN. "CMOS DESIGN OF ANALOG FUZZY SYSTEM." Journal of Circuits, Systems and Computers 14, no. 06 (December 2005): 1101–12. http://dx.doi.org/10.1142/s0218126605002830.

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This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high precision.

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Kushwah, Ravindra Singh, and Shyam Akashe. "FinFET Based Tunable Analog Circuit: Design and Analysis at 45 nm Technology." Chinese Journal of Engineering 2013 (October 24, 2013): 1–8. http://dx.doi.org/10.1155/2013/165945.

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We included a designing of low power tunable analog circuits built using independently driven FinFETs devices, where the controlling of the back gate provide the output on the front gate. We show that this could be an effective solution to conveniently tune the output of bulk CMOS analog circuits particularly for Schmitt trigger and operational transconductance amplifier circuits. FinFET devices can be used to increase the performance by reducing the leakage current and power dissipation, because front and back gates both are independently controlled. FinFET device has a higher controllability, resulting relatively high Ion/Ioff ratio. In this paper, we proposed a tunable analog circuit such as CMOS amplifier circuit, Schmitt trigger circuit, and operational transconductance amplifier circuit, these circuit blocks are necessary for low noise high performance ICs for analog applications. Gain, phase, group delay, and output response of analog tunable circuits have been discussed in this paper. The proposed FinFET based analog tunable circuits have been designed using Cadence Virtuoso tool at 45 nm.

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WAWRYN, KRZYSZTOF. "AN ARTIFICIAL INTELLIGENCE APPROACH TO ANALOG CIRCUIT DESIGN." Journal of Circuits, Systems and Computers 01, no. 02 (June 1991): 149–76. http://dx.doi.org/10.1142/s0218126691000033.

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This article deals with a new approach to an intelligent analog circuit design. The iterative closed loop design methodology adopts an expert system approach to provide topological synthesis, the SPICE circuit simulator to evaluate the circuit performance and a new approach of the diagnostic expert system to provide advice on how to improve the design. Unlike previous design methods, this approach introduces formal circuit representation for both numerical and heuristic knowledge of the design system. The predicate logic circuit representation is proposed to introduce a new concept of a formal analog circuit description language. The language syntax and semantics provide precise symbolic description of analog circuits functionality at different levels of hierarchy and connectivities together with transistor sizes of CMOS circuits at the transistor level. Different levels of hierarchy with circuit structures and performance parameters are presented in detail. It is shown how sentence conversion rules of language grammar can be used to derive transistor level circuits from input performance specifications through all intermediate levels of hierarchy. The implementation of the methodology and associated experimental results for CMOS operational amplifier designs are presented.

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Gao, Sirui. "Analog integrated circuit design with machine learning." Theoretical and Natural Science 5, no. 1 (May 25, 2023): 788–95. http://dx.doi.org/10.54254/2753-8818/5/20230495.

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Due to the widespread application of semiconductor technology in integrated circuits, more and more design studies on analog integrated circuits are gradually being implemented. However, due to the nature of analog integrated circuits, it is time-consuming and inefficient. Therefore, there are lots of experts studying how to reduce the design cycle of analog ICs. The use of machine learning in analog circuits stands out, as machine learning-based design methods have significantly reduced the analog cycle time. This review report will first introduce the algorithms related to machine learning, and the second half will outline the existing applications of machine learning in an analog integrated circuit and compare them.

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Jiao, Su Min, Cai Hong Wang, and Xue Mei Wang. "Large-Scale Analog Circuit Evolutionary Design Using a Real-Coded Scheme." Applied Mechanics and Materials 220-223 (November 2012): 2036–39. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.2036.

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Analog circuits are of great importance in electronic system design. Recent evolutionary design results are usually small-scale analog circuits. This paper proposes a real-coded mechanism and uses it in the large-scale analog circuit evolutionary design. The proposed scheme evolves the circuit topology and size to a uniformed continuous space, in which the circuit representation is closed and of causality. Experimental results show that the proposed scheme can work successfully on many analog circuits with different kinds of characteristics. Comparing with other evolutionary methods before, the proposed scheme performs better on large-scale problems of circuit synthesis with higher search efficiency, lower computational complexity, and less computing time.

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Hurst, Stanley L. "Analog integrated circuit design." Microelectronics Journal 29, no. 6 (June 1998): 361–62. http://dx.doi.org/10.1016/s0026-2692(97)00051-7.

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Liu, Xiaoxin, Lanqing Zou, Chenyang Huang, Na Bai, Kanhao Xue, Huajun Sun, and Xiangshui Miao. "Analog Memristor-Based Dynamic Programmable Analog Filter." Journal of Physics: Conference Series 2356, no. 1 (October 1, 2022): 012008. http://dx.doi.org/10.1088/1742-6596/2356/1/012008.

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The memristor study now generally exhibit threshold voltage characteristics. The memristance changes when the voltage across the memristor is greater than the threshold voltage. Otherwise, the memristance is almost constant. Based on this feature, we design a general-purpose memristor programmable circuit that is simple to operate. In the field of communication and signal processing, programmable analog filters are required, and memristors with multi-valued characteristic are suitable as programmable impedance elements for such circuits. Through simulation and physics experiments, we demonstrate a memristor-based programmable low-pass filter using the designed programmable circuit to realize the dynamic adjustment of circuit parameters.

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Prajapati, Pankaj P., Anilkumar J. Kshatriya, Sureshbhai L. Bharvad, and Abhay B. Upadhyay. "Performance analysis of CMOS based analog circuit design with PVR variation." Bulletin of Electrical Engineering and Informatics 12, no. 1 (February 1, 2023): 141–48. http://dx.doi.org/10.11591/eei.v12i1.4357.

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Process, supply voltage, and temperature (PVT) are three important factors which contribute to performance variation of the complementary metal–oxide–semiconductor (CMOS) based analog circuits. In this paper, CMOS based analog circuit design with the PVT variation effects are explored. The effects of the PVT variation on the performance of CMOS based analog circuits are introduced. The optimization of CMOS based analog circuits such as differential amplifier (DA) and two-stage operational amplifier (op amp) circuits with PVT variations with different algorithms such as cockoo search (CS), particle swam optimization (PSO), hybrid CSPSO, and differential evaluation (DE) algorithms is presented. Each algorithm is implemented using the C programming language, interfaced with Ngspice circuit simulator, and tested on the Intel®core™ i5, 2.40 GHz processor with 8 GB internal RAM using the Ubuntu operating system (OS). The result shows PVT variation affects the performance of CMOS circuit.

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Bhupatprasad, Chourasia Ashish, and Kelkar Deepali Shrikant. "A circuit design of a cyclic voltage generator." Chemistry & Chemical Technology 2, no. 3 (September 15, 2008): 235–38. http://dx.doi.org/10.23939/chcht02.03.235.

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The present paper describes a simple circuit for construction of a cyclic voltage generator, which can be used in electrochemical synthesis of conducting polymer films like polyaniline(PANI), polythiophene, polypyrrol etc. The circuit consists of a clock generator; its frequency is converted into digital voltage which is further converted to analog form using digital to analog converter (DAC). This analog voltage, after boosting, is used as a source of voltage in the synthesis of conducting polymer. Since the oxidation potential for a polymer is unknown, the circuit developed has a facility to change output in cyclic fashion from initial to final value at a rate of 45 mV/s and return back to the initial position. The designed circuit can also hold the potential at any desired value and hence can also be used in the potentiostatic configuration as a potentiostat for synthesizing a conducting polymer.

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12

Manganaro, G. "Analog circuit design [Book Review]." IEEE Circuits and Devices Magazine 17, no. 4 (July 2001): 34. http://dx.doi.org/10.1109/mcd.2001.950058.

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Chen, Shen Li, and C. K. Lee. "A Single-Chip Design for the Three-Phase BDCM System." Applied Mechanics and Materials 271-272 (December 2012): 742–46. http://dx.doi.org/10.4028/www.scientific.net/amm.271-272.742.

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In this work, we present a sensorless single-chip design for the three-phase brushless DC motors (BDCM) system, and which is implemented by a 0.35um CMOS process. A mixed-signal IC will be accomplished by the implementation of analog circuit and digital circuit in the same chip. Eventually, this chip system includes an analog circuit (Hall signal amplifier), a digital circuit (logic process block), and a frequency voltage converter (FVC) to complete the control & driving circuits. Experimental results are included to verify the proposed scheme.

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Khalifa, Yaser M. A., Badar Khan, and Faisal Taha. "Multiobjective Optimization Tool for a Free Structure Analog Circuits Design Using Genetic Algorithms and Incorporating Parasitics." Journal of Artificial Evolution and Applications 2008 (September 8, 2008): 1–9. http://dx.doi.org/10.1155/2008/761380.

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This paper presents a novel approach for a free structure analog circuit design using genetic algorithms (GAs). A major problem in a free structure circuit is its sensitivity calculations as a polynomial approximation for the design is not available. A further problem is the effect of parasitic elements on the resulting circuit's performance. In a single design stage, circuits that are produced satisfy a specific frequency response specifications using circuit structures that are unrestricted and with component values that are chosen from a set of preferred values including their parasitic effects. The sensitivity to component variations for the resulting designs is performed using a novel technique and is incorporated in the fitness evaluation function. The extra degrees of freedom resulting form unbounded circuit structures create a huge search space. The application chosen is an RLC ladder filters circuit design.

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Mina, Rayan, Chadi Jabbour, and George E. Sakr. "A Review of Machine Learning Techniques in Analog Integrated Circuit Design Automation." Electronics 11, no. 3 (January 31, 2022): 435. http://dx.doi.org/10.3390/electronics11030435.

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Analog integrated circuit design is widely considered a time-consuming task due to the acute dependence of analog performance on the transistors’ and passives’ dimensions. An important research effort has been conducted in the past decade to reduce the front-end design cycles of analog circuits by means of various automation approaches. On the other hand, the significant progress in high-performance computing hardware has made machine learning an attractive and accessible solution for everyone. The objectives of this paper were: (1) to provide a comprehensive overview of the existing state-of-the-art machine learning techniques used in analog circuit sizing and analyze their effectiveness in achieving the desired goals; (2) to point out the remaining open challenges, as well as the most relevant research directions to be explored. Finally, the different analog circuits on which machine learning techniques were applied are also presented and their results discussed from a circuit designer perspective.

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Lukić, Jelena, and Dragan Denić. "A Novel Design Of An NTC Thermistor Linearization Circuit." Metrology and Measurement Systems 22, no. 3 (September 1, 2015): 351–62. http://dx.doi.org/10.1515/mms-2015-0035.

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Abstract A novel design of a circuit used for NTC thermistor linearization is proposed. The novelty of the proposed design consists in a specific combination of two linearization circuits, a serial-parallel resistive voltage divider and a two-stage piecewise linear analog-to-digital converter. At the output of the first linearization circuit the quasi-linear voltage is obtained. To remove the residual voltage nonlinearity, the second linearization circuit, i.e., a two-stage piecewise linear analog-to-digital converter is employed. This circuit is composed of two flash analog-to-digital converters. The first analog-to-digital converter is piecewise linear and it is actually performing the linearization, while the second analog-to-digital converter is linear and it is performing the reduction of the quantization error introduced by the first converter. After the linearization is performed, the maximal absolute value of a difference between the measured and real temperatures is 0.014°C for the temperature range between −25 and 75°C, and 0.001°C for the temperature range between 10 and 40°C.

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Dieste-Velasco, M. Isabel. "Application of a Fuzzy Inference System for Optimization of an Amplifier Design." Mathematics 9, no. 17 (September 5, 2021): 2168. http://dx.doi.org/10.3390/math9172168.

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Simulation programs are widely used in the design of analog electronic circuits to analyze their behavior and to predict the response of a circuit to variations in the circuit components. A fuzzy inference system (FIS) in combination with these simulation tools can be applied to identify both the main and interaction effects of circuit parameters on the response variables, which can help to optimize them. This paper describes an application of fuzzy inference systems to modeling the behavior of analog electronic circuits for further optimization. First, a Monte Carlo analysis, generated from the tolerances of the circuit components, is performed. Once the Monte Carlo results are obtained for each of the response variables, the fuzzy inference systems are generated and then optimized using a particle swarm optimization (PSO) algorithm. These fuzzy inference systems are used to determine the influence of the circuit components on the response variables and to select them to optimize the amplifier design. The methodology proposed in this study can be used as the basis for optimizing the design of similar analog electronic circuits.

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Thakral, Bindu, Arti Vaish, and Rama Koteswara Rao Alla. "Design of Squarer Circuit in Sub-threshold Mode." International Journal of Engineering & Technology 7, no. 2.11 (April 3, 2018): 38. http://dx.doi.org/10.14419/ijet.v7i2.11.11004.

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Historically, analog designs have been assumed as a voltage mode based signal processing. However, the necessity of high speed circuits operating at reduced supply voltage has lead to a development of new circuit topology referred as current-mode designs. For low power low voltage designs the applications using translinear principle based circuits has become an area of research and interest. It has wide application in nonlinear signal processing and to build basic active elements. Mode of MOS transistor used in analog circuit realization of is important parameter deciding the performance of the circuit. In this paper, a squarer circuit is proposed based on sub threshold-mode MOS transistors exhibiting the exponential current-voltage characteristic. The simulations have been performed on model files of TSMC 0.18 micrometer technology with the help of ELDO Simulator.

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Rojec, Žiga, Iztok Fajfar, and Árpád Burmen. "Evolutionary Synthesis of Failure-Resilient Analog Circuits." Mathematics 10, no. 1 (January 5, 2022): 156. http://dx.doi.org/10.3390/math10010156.

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Analog circuit design requires large amounts of human knowledge. A special case of circuit design is the synthesis of robust and failure-resilient electronics. Evolutionary algorithms can aid designers in exploring topologies with new properties. Here, we show how to encode a circuit topology with an upper-triangular incident matrix and use the NSGA-II algorithm to find computational circuits that are robust to component failure. Techniques for robustness evaluation and evolutionary algorithm guidances are described. As a result, we evolve square root and natural logarithm computational circuits that are robust to high-impedance or short-circuit malfunction of an arbitrary rectifying diode. We confirm the simulation results by hardware circuit implementation and measurements. We think that our research will inspire further searches for failure-resilient topologies.

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Nguyen, Hoang Trong, and Trang Hoang. "A Novel Framework of Genetic Algorithm and Spectre to Optimize Delay and Power Consumption in Designing Dynamic Comparators." Electronics 12, no. 16 (August 9, 2023): 3392. http://dx.doi.org/10.3390/electronics12163392.

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In integrated circuit (IC) design, analog circuits contribute significantly as the interface between real and digital world signals. Although they make up a relatively small portion of the overall circuit, their design process is often most time-consuming, mostly from the phase of manual iteration of circuit parameters to meet design specifications. Therefore, the design automation of analog circuits with the help of efficient optimization techniques arises as a promising candidate to address the issue. Among optimization algorithms, while the genetic algorithm (GA) has been shown to be effective in finding near-optimal solutions, it has not been extensively applied to the field of analog circuit design. Hence, this paper proposes a method to utilize GA in the optimization of a widely used circuit topology, namely the comparator. The comparator is considered the fundamental block in the design of most analog-to-digital converters (ADCs). For high-speed ADCs, dynamic comparators are usually chosen for the purpose of high speed and power efficiency. In summary, this paper introduces an innovative GA-Spectre architecture to optimize the dynamic comparator with respect to delay and power consumption. The post-optimized results are optimistic with a 72.61 ps delay and 3.11 µW power dissipation.

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Rutkowski, Jerzy. "Identification of Circuit Parameters for the Specified or Measured Performances." International Journal of Electronics and Telecommunications 61, no. 1 (March 1, 2015): 95–100. http://dx.doi.org/10.1515/eletel-2015-0012.

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Abstract Extension of the method of analog circuit parameter identification for the specified design performances, originally presented by the same author in 1982, is described. These parameters are designated by means of PSpice simulation of the adjoint circuit to the original one. In this adjoint circuit, elements of the original circuit, described by the sized parameters, are replaced by controlled sources. Each such source is controlled by the differential voltage or current, difference between the calculated voltage or current and the specified one, with infinitely large gain. The method is applicable to both linear and nonlinear DC circuits and AC circuits and can be used in many fields of analog circuit design, such as: finding of acceptability region, analog fault diagnosis, postproduction identification and tuning. In the later cases, design performances are replaced by measurements of Circuit Under Test (CUT). Simplicity, extremely low computational complexity and high accuracy are the main benefits of the proposed, basic Circuit Theory based, approach - the solution is found after a single PSpice simulation. For better understanding of the presented methodology, five practical examples are discussed

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Prajapati, Pankaj P., and Mihir V. Shah. "Automatic Circuit Design of CMOS Miller OTA Using Cuckoo Search Algorithm." International Journal of Applied Metaheuristic Computing 11, no. 1 (January 2020): 36–44. http://dx.doi.org/10.4018/ijamc.2020010103.

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The circuit design of the CMOS based analog part of a mixed-signal integrated circuit (IC) needs a large fraction of the overall design cycle time. The automatic design of an analog circuit is inevitable, seeing recently development of System-on-Chip (SOC) design. This brings about the need to develop computer aided design (CAD) tools for automatic design of CMOS based analog circuits. In this article, a Cuckoo Search (CS) algorithm is presented for automatic design of a CMOS Miller Operational Transconductance Amplifier (OTA). The source code of the CS algorithm is developed using the C language. The Ngspice circuit simulator has been used as a fitness function creator and evaluator. A script file is written to provide an interface between the CS algorithm and the Ngspice simulator. BSIM3v3 MOSFET models with 0.18 µm and 0.35 µm CMOS technology have been used to simulate this circuit. The simulation results of this work are presented and compared with previous works reported in the literature. The experimental simulation results obtained by the CS algorithm satisfy all desired specifications for this circuit.

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SAMAKI, Akira. "Analog circuit design using CAD system." Circuit Technology 2, no. 3 (1987): 182–87. http://dx.doi.org/10.5104/jiep1986.2.182.

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Hatfield, John. "Book Review: CMOS Analog Circuit Design." International Journal of Electrical Engineering & Education 25, no. 2 (April 1988): 183. http://dx.doi.org/10.1177/002072098802500223.

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Skattebol, L. "Book Review: Analog Electronic Circuit Design." International Journal of Electrical Engineering & Education 30, no. 3 (July 1993): 275–76. http://dx.doi.org/10.1177/002072099303000312.

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Sedighi, Behnam, Xiaobo Sharon Hu, Huichu Liu, Joseph J. Nahas, and Michael Niemier. "Analog Circuit Design Using Tunnel-FETs." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 1 (January 2015): 39–48. http://dx.doi.org/10.1109/tcsi.2014.2342371.

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Rajput, S. S., and S. S. Jamuar. "Low voltage analog circuit design techniques." IEEE Circuits and Systems Magazine 2, no. 1 (2002): 24–42. http://dx.doi.org/10.1109/mcas.2002.999703.

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Johns, D. A., K. Martin, and J. Wiley. "Analog integrated circuit design [Book Review]." IEEE Circuits and Devices Magazine 16, no. 5 (September 2000): 39–40. http://dx.doi.org/10.1109/mcd.2000.876905.

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Ravender, Goyal, and Dragiša P. Milovanović. "High-frequency analog integrated circuit design." Microelectronics Reliability 37, no. 5 (May 1997): 873. http://dx.doi.org/10.1016/s0026-2714(96)00280-6.

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Milovanović, Dragiša P. "High-frequency analog integrated circuit design." Microelectronics Journal 28, no. 5 (June 1997): 598. http://dx.doi.org/10.1016/s0026-2692(97)80953-6.

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Sayandeep, Nag. "Analog Versus Digital Design: When and Where to Make the Cut." Mapana - Journal of Sciences 1, no. 1 (August 15, 2002): 69–80. http://dx.doi.org/10.12723/mjs.1.7.

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System designers are frequently asked to create circuits that measure and control the analog world. One of the the challenges in these types of designs is to know when to convert the signal signal from the analog domain to the digital domain. In the analog domain, signal conditioning techniques such as gain, offset, and filtering are used to quickly modify the incoming signal. Alternatively, mathematical algorithms are used in the digital domain to implement similar functions. Every system design is unique and requires custom solutions for each case, but there are some general guidelines that can help the designer make the right decisions concerning where to draw the line. Two circuit scenarios will be discussed in this paper. With each of the two systems, the question of when and where to use analog signal conditioning strategies as opposed to digital techniques will be answered. The first scenario that will be used in this discussion is a simple RTD(Resistance Temperature Detectors) temperature sensing circuit. With this system, digital versus analog calibration, gain and offset techniques will be under evaluation.Filtering techniques is the second scenario that will be evaluated. Discussions will show that all circuit designs require a degree of analog filtering whether or not the input analog signal is DC or AC. From this premise, the advantages of analog versus digital filter designs will be investigated.

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Bae, Woorham. "CMOS Inverter as Analog Circuit: An Overview." Journal of Low Power Electronics and Applications 9, no. 3 (August 20, 2019): 26. http://dx.doi.org/10.3390/jlpea9030026.

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Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.

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FLYNN, MICHAEL P., SUNGHYUN PARK, and CHUN C. LEE. "ACHIEVING ANALOG ACCURACY IN NANOMETER CMOS." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 255–75. http://dx.doi.org/10.1142/s0129156405003193.

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This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that VT matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.

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Li, Bo, and Guoyong Shi. "A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits." ACM Transactions on Design Automation of Electronic Systems 27, no. 1 (January 31, 2022): 1–24. http://dx.doi.org/10.1145/3474364.

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Since the memristor emerged as a programmable analog storage device, it has stimulated research on the design of analog/mixed-signal circuits with the memristor as the enabler of in-memory computation. Due to the difficulty in evaluating the circuit-level nonidealities of both memristors and CMOS devices, SPICE-accuracy simulation tools are necessary for perfecting the art of neuromorphic analog/mixed-signal circuit design. This article is dedicated to a native SPICE implementation of the memristor device models published in the open literature and develops case studies of applying such a circuit simulation with MOSFET models to study how device-level imperfections can make adversarial effects on the analog circuits that implement neuromorphic analog signal processing. Methods on memristor stamping in the framework of modified nodal analysis formulation are presented, and implementation results are reported. Furthermore, functional simulations on neuromorphic signal processing circuits including memristors and CMOS devices are carried out to validate the effectiveness of the native SPICE implementation of memristor models from the perspectives of simulation accuracy, efficiency, and convergence for large-scale simulation tasks.

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Odame, K., and P. E. Hasler. "Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping." VLSI Design 2010 (March 18, 2010): 1–8. http://dx.doi.org/10.1155/2010/687498.

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Nonlinear signal processing is necessary in many emerging applications where form factor and power are at a premium. In order to make such complex computation feasible under these constraints, it is necessary to implement the signal processors as analog circuits. Since analog circuit design is largely based on a linear systems perspective, new tools are being introduced to circuit designers that allow them to understand and exploit circuit nonlinearity for useful processing. This paper discusses two such tools, which represent nonlinear circuit behavior in a graphical way, making it easy to develop a qualitative appreciation for the circuits under study.

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Sanabria-Borbón, Adriana, Sergio Soto-Aguilar, Johan Estrada-López, Douglas Allaire, and Edgar Sánchez-Sinencio. "Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design." Electronics 9, no. 4 (April 23, 2020): 685. http://dx.doi.org/10.3390/electronics9040685.

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Optimization algorithms have been successfully applied to the automatic design of analog integrated circuits. However, many of the existing solutions rely on expensive circuit simulations or use fully customized surrogate models for each particular circuit and technology. Therefore, the development of an easily adaptable low-cost and efficient tool that guarantees resiliency to variations of the resulting design, remains an open research area. In this work, we propose a computationally low-cost surrogate model for multi-objective optimization-based automated analog integrated circuit (IC) design. The surrogate has three main components: a set of Gaussian process regression models of the technology’s parameters, a physics-based model of the MOSFET device, and a set of equations of the performance metrics of the circuit under design. The surrogate model is inserted into two different state-of-the-art optimization algorithms to prove its flexibility. The efficacy of our surrogate is demonstrated through simulation validation across process corners in three different CMOS technologies, using three representative circuit building-blocks that are commonly encountered in mainstream analog/RF ICs. The proposed surrogate is 69 X to 470 X faster at evaluation compared with circuit simulations.

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Barari, Mansour, Hamid Reza Karimi, and Farhad Razaghian. "Analog Circuit Design Optimization Based on Evolutionary Algorithms." Mathematical Problems in Engineering 2014 (2014): 1–12. http://dx.doi.org/10.1155/2014/593684.

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This paper investigates an evolutionary-based designing system for automated sizing of analog integrated circuits (ICs). Two evolutionary algorithms, genetic algorithm and PSO (Parswal particle swarm optimization) algorithm, are proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through specific electrical simulation, to the optimization system in the MATLAB environment, for the selected topology. The system has been tested by typical and hard-to-design cases, such as complex analog blocks with stringent design requirements. The results show that the design specifications are closely met. Comparisons with available methods like genetic algorithms show that the proposed algorithm offers important advantages in terms of optimization quality and robustness. Moreover, the algorithm is shown to be efficient.

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Negishi, Takayuki, Naoki Arai, Nobukazu Takai, Masato Kato, Hiroaki Seki, and Haruo Kobayashi. "Automatic Synthesis of Comparator Circuit Using Genetic Algorithm and SPICE Optimizing Function." Key Engineering Materials 643 (May 2015): 131–40. http://dx.doi.org/10.4028/www.scientific.net/kem.643.131.

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This Paper Describes our Challenge of Automatic Analog Circuit Design by Focusingon a Comparator Circuit which is One of the Important Analog Building Blocks. the Geneticalgorithm Chooses the Optimal Circuit Topology and HSPICE Optimizing Function Obtains Theiroptimal Parameter Values Automatically. Automatic Design for Analog Circuit has Not Beenrealized yet, even though Automatic Design is being Used in Digital Circuit Design; the Reasonbehind this is that the Number of Parameters to Be Considered in an Analog Circuit Designis much Larger than Digital Circuit Design. Nowadays it is Extremely Difficult to Design Icsmanually due to their Large Scale Integration and Hence their Automatic Design is Demanded. Wepresent our Automatic Circuit Design Owchart Programmed with Java Language which Realizes1-Click Automatic Synthesis of the Comparator, and Shows that our Method can Obtain a Betterperformance Comparator Compared to an Initially-Set Comparator.

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Khan, Noor Mohmmed, Shubhangi Patil, Tushar Diggewadi, and Anand Gudnavar. "Cinch and Sterling Analog Circuits for Laboratory." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 6, no. 01 (June 25, 2017): 51–58. http://dx.doi.org/10.15662/ijareeie.2017.0601007.

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As we know that there is ever increasing demand for compact circuits and less complex wirings over the board, a technological boon evolved for such demand is Printed Circuit Board (PCB). A PCB will mechanically supports and electrically connects electronic components using conductive tracks, pads. These boards will have minimal chances for short circuits, components on the board are fixed; another advantage is creation of multiple boards using single design. Taking this technology forward to our everyday life, we implemented analog communication laboratory circuit, Schmitt trigger.

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Koseoglu, Murat, Furkan Nur Deniz, Baris Baykant Alagoz, Ali Yuce, and Nusret Tan. "An experimental analog circuit realization of Matsuda’s approximate fractional-order integral operators for industrial electronics." Engineering Research Express 3, no. 4 (December 1, 2021): 045041. http://dx.doi.org/10.1088/2631-8695/ac3e11.

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Abstract Analog circuit realization of fractional order (FO) elements is a significant step for the industrialization of FO control systems because of enabling a low-cost, electric circuit realization by means of standard industrial electronics components. This study demonstrates an effective operational amplifier-based analog circuit realization of approximate FO integral elements for industrial electronics. To this end, approximate transfer function models of FO integral elements, which are calculated by using Matsuda’s approximation method, are decomposed into the sum of low-pass filter forms according to the partial fraction expansion. Each partial fraction term is implemented by using low-pass filters and amplifier circuits, and these circuits are combined with a summing amplifier to compose the approximate FO integral circuits. Widely used low-cost industrial electronics components, which are LF347N opamps, resistor and capacitor components, are used to achieve a discrete, easy-to-build analog realization of the approximate FO integral elements. The performance of designed circuit is compared with performance of Krishna’s FO circuit design and performance improvements are shown. The study presents design, performance validation and experimental verification of this straightforward approximate FO integral realization method.

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Krishnan, R. Rohith, S. Krishnakumar, and Reza Hashemian. "Fixator-Norator Pair Based Design of Feedback Networks for Analog Amplifier Circuits." Journal of Circuits, Systems and Computers 27, no. 03 (October 30, 2017): 1850050. http://dx.doi.org/10.1142/s0218126618500500.

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Feedback is an integral part of many analog circuits. This paper presents a method for the design of feedback networks for analog amplifiers based on Fixator–Norator Pair (FNP). The design process for required transfer function includes inserting proper FNPs to the equivalent small signal model of the target circuit, with norators lying along the feedback path, and helps to design the feedback network components. Care must be taken to ensure that the added feedback should not alter the original DC biasing of the circuit. A number of examples are worked out in this paper using the proposed method and the results are verified. The FNP approach gives a one-step solution for the design problems which otherwise require tedious analysis and calculations. Although the scope of this paper is limited to design of feedback for amplifiers, a skillful designer can extend the proposed method to other areas of analog circuits.

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Takai, Nobukazu. "Realization of a design-less system for analog integrated circuits." Impact 2020, no. 1 (February 27, 2020): 9–11. http://dx.doi.org/10.21820/23987073.2020.1.9.

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The 21st century has given rise to a digital world which has significantly impacted on the ways in which humans go about their everyday lives. From being able to speak with whomever you want, whenever you want, wherever you are on your smartphone, to tapping away on your laptop, through to spending hours each day on the internet, the world we live in is firmly digital and it now shapes the way we experience life. When it comes to circuits, analog still has a hugely important role to play. Circuit designer Associate Professor Nobukazu Takai is leading a team of researchers who are applying machine learning to analog circuit design. They are the first team to do this anywhere in the world and, using their method, computers are able to learn how to improve their own circuit specifications.

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KILIC, RECAI. "UNIVERSAL PROGRAMMABLE CHAOS GENERATOR: DESIGN AND IMPLEMENTATION ISSUES." International Journal of Bifurcation and Chaos 20, no. 02 (February 2010): 419–35. http://dx.doi.org/10.1142/s021812741002551x.

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Chaos generators are generally designed and implemented by using analog circuit design techniques. Analog implementations require a variety of circuitry that comprises different passive and active electronic components like individual op-amps, comparators, analog multipliers, trigonometric function generators. Anyone who wants to experimentally investigate different structurally chaotic systems has to provide a significant amount of circuit hardware. This process may be hard and time consuming. At this stage, the question to be asked: Is there a unique analog component for implementing a universal analog chaos generator which is capable of generating the chaotic signals of nearly all analog-based chaotic systems. Fortunately, we can now answer this question positively. This analog device is FPAA (Field-Programmable Analog Array). FPAA is the analog equivalent of the FPGA (Field-Programmable Gate Array) used as programmable device in digital signal processing. FPAA is a programmable device for implementing a rich variety of systems including analog functions via dynamic reconfiguration. FPAA can be configured in real time which allows the designers to modify the design or make completely new design in real time. In this paper, we aim to show how FPAA device can be used as universal device for design and implementation of programmable analog chaos generators. For this purpose, we will introduce three FPAA-based design examples: autonomous Chua's circuit, nonautonomous MLC (Murali–Lakshmanan–Chua) circuit and a chaotic system based on a PLL (Phase Locked Loop) model.

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LIU, YAN, YI-FEI PU, JI-LIU ZHOU, and XIAO-DONG SHEN. "DESIGN OF -1/2n ORDER ANALOG FRACTANCE APPROXIMATION CIRCUIT USING CONTINUED FRACTIONS DECOMPOSITION." Journal of Circuits, Systems and Computers 21, no. 04 (June 2012): 1250035. http://dx.doi.org/10.1142/s0218126612500351.

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In order to solve the most important problem of the fractional calculus (FC) application, the realization of analog circuit of fractance, continued fraction theory is applied to design the -1/2n order analog fractance approximation circuit. The author presents a network function of ideal fractance and decomposes it in continued fractions (CFs) form to obtain the corresponding analog fractance approximation circuit. The new circuit consists of ordinary passive RC component through network synthesis method. Simulations are performed for the verification of the new circuit. Experimental evidence has proved that the performance of novel -1/2n order analog fractance approximation circuit is good in both amplitude-frequency response and phase-frequency response.

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Lima, Evelyn Cristina de Oliveira, André Borges Cavalcante, and João Viana Da Fonseca Neto. "Optimization of amplifier circuits by using gradient boosted trees and probability annealing policy." Journal of Integrated Circuits and Systems 15, no. 3 (December 3, 2020): 1–5. http://dx.doi.org/10.29292/jics.v15i3.184.

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One important step of the optimization of analog circuits is to properly size circuit components. Since the quantities that define specification may compete for different circuit parameter values, the optimization of analog circuits befits a hard and costly optimization problem. In this work, we propose two contributions to design automation methodologies based on machine learning. Firstly, we propose a probability annealing policy to boost early data collection and restrict electronic simulations later on in the optimization. Secondly, we employ multiple gradient boosted trees to predict design superiority, which reduces overfitting to learned designs. When compared to the state-of-the art, our approach reduces the number of electronic simulations, the number of queries made to the machine learning module required to finish the optimization.

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Kobayashi, Haruo, and Anna Kuwana. "Study of analog-to-digital mixed integrated circuit configuration using number theory." Impact 2022, no. 3 (June 30, 2022): 9–11. http://dx.doi.org/10.21820/23987073.2022.3.9.

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Electronic circuits form the basis of much of the technology we use today. Professor Haruo Kobayashi and Assistant Professor Anna Kuwana, Division of Electronics and Informatics, Gunma University, Japan, are utilising classical mathematics, including theorems such as number theory and control theory in their design of circuits that contain elements of analogue signalling. Analogue circuit planning is regarded as an art as these circuits are typically designed based on mature designers' intuition and experiences in a process that is less systematic for coming up with new architectures and more designing than digital circuit design and Kobayashi and Kuwana firmly believe that 'beautiful' mathematics can facilitate truly great circuit design. Additional mathematics techniques employed by Kobayashi and the team are statistics, coding theory, modulation and signal processing algorithms and pairing pure mathematics theorems with electrical engineering is a key feature of the researchers' work. The team utilises theoretical analysis and simulations such as the circuit simulator (SPICE) and system simulator (MATLAB) to test its work and collaborates with semiconductor companies and electronic measurement instrument companies in Japan for smart circuit design and effective circuit testing. So far, results include that using SAR ADC configurations with Fibonacci sequence weights can improve the speeds and reliability of the SAR ADC. Also several new DAC architecutures and waveform sampling methods are derived based on mathematics.

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Alahdal, Abdulrahman, Anis Ammous, and Kaiçar Ammous. "Design and realization of an analog integrated circuit for maximum power point tracking of photovoltaic panels." EPJ Photovoltaics 13 (2022): 6. http://dx.doi.org/10.1051/epjpv/2022002.

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The tracking of the maximum power point (MPP) of a photovoltaic (PV) solar panel is an important part of a PV generation chain. In order to track maximum power from the solar arrays, it is necessary to control the output impedance of the PV panel, so that the circuit can be operated at its Maximum Power Point (MPP), despite the unavoidable changes in the climate conditions such as temperature and Irradiance. A new MPPT analog technique to track the Maximum Power Point (MPP) of PV arrays is proposed. This new technique uses simple and classical functions of electronic circuits. An Off-Grid PV system was considered to apply and validate the proposed new technique. The entire circuit was implemented in circuit-oriented simulator Proteus-ISIS. We present the results associated with the design, the realization, and the experimentation of a PV system equipped with a new analog MPPT command. The obtained results have shown good efficiency of analog technique (more than 98.5%). The second part of the paper consists of the description of the design and the realization of the novel analog MPPT integrated chip. The integrated circuit (IC) was designed and realized using HV CMOS technology 0.35-µm.

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BŰRMEN, ÁRPÁD, TADEJ TUMA, and IZTOK FAJFAR. "A COMBINED SIMPLEX–TRUST-REGION METHOD FOR ANALOG CIRCUIT OPTIMIZATION." Journal of Circuits, Systems and Computers 17, no. 01 (February 2008): 123–40. http://dx.doi.org/10.1142/s0218126608004125.

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The analog-integrated circuits industry is exerting increasing pressure to shorten the analog circuit design time. This pressure is put primarily on the analog circuit designers that in turn demand automated circuit design tools evermore vigorously. Such tools already exist in the form of circuit optimization software packages but they all suffer a common ailment — slow convergence. Even taking into account the increasing computational power of modern computers the convergence times of such optimization tools can range from a few days to even weeks. Different authors have tried diverse approaches for speeding up the convergence with varying success. In this paper authors propose a combined optimization algorithm that attempts to improve the speed of convergence by exploiting the positive properties of the underlying optimization methods. The proposed algorithm is tested on a number of test cases and the convergence results are discussed.

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Yang, Yu Jun, Wei Hu, Jun Liu, Zhou Yu, Dong Bing Fu, and Guang Bing Chen. "Design of a 10 Bit 2GHz Digital to Analog Converter Circuit." Applied Mechanics and Materials 713-715 (January 2015): 942–45. http://dx.doi.org/10.4028/www.scientific.net/amm.713-715.942.

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This paper presents the design of a 10 bit 2GHz digital to analog converter circuit. The digital to analog converter circuit adopts the design simulation of HBT process, able to work at a sampling frequency of 2 GHz, the highest sampling frequency can reach about 4 GHz. The SFDR of the digital to analog converter circuit can reach 62dB (simulation work at 2 GHz), the SFDR can reach 45 dB (simulation work at 4 GHz). Early product parameters of the digital to analog converter circuit (working in 1 GHz sampling frequency) are as follows: the narrowband SFDR parameter can be achieved 81 dB, broadband SFDR parameters can reach 46 dB.

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CAPONETTO, RICCARDO, ANDREA DI MAURO, LUIGI FORTUNA, and MATTIA FRASCA. "FIELD PROGRAMMABLE ANALOG ARRAY TO IMPLEMENT A PROGRAMMABLE CHUA'S CIRCUIT." International Journal of Bifurcation and Chaos 15, no. 05 (May 2005): 1829–36. http://dx.doi.org/10.1142/s0218127405012806.

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This paper introduces a new application of the Field Programmable Analog Array. Ease of design and reprogrammability are the advantages offered by this class of analog circuits, making them an ideal environment for the implementation of chaotic circuits and their experimental characterization. Chua's circuit, a well-known paradigm of nonlinear circuits, has been used as an example of application. Experimental results show the suitability of the approach, highlighting the features of the new implementation: a fully on the fly programmable Chua's circuit has been obtained.

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Journal articles on the topic 'Analog circuit design'

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