Dissertations / Theses on the topic 'Analog circuit'
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Kuznetsov, Eugene. "Trust in analog : analog circuit techniques for reducing the risk of malicious circuits and software." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66431.
Full textCataloged from PDF version of thesis.
Includes bibliographical references (p. 47).
Malicious circuits and software present a significant security risk, especially in control applications. This work is concerned with increasing the trustworthiness of control circuitry by reducing its complexity. The security benefits of substituting analog control techniques in place of digital control are analyzed, and both discrete and integrated circuit designs are demonstrated.
by Eugene Kuznetsov.
M.Eng.
Hong, Seong-Kwan. "Performance driven analog layout compiler." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.
Full textWang, Xiaoying [Verfasser]. "Analog Circuit Design Approaches / Xiaoying Wang." München : Verlag Dr. Hut, 2014. http://d-nb.info/1053859848/34.
Full textMitros, Piotr 1979. "A framework for analog circuit optimization." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/28447.
Full textIncludes bibliographical references (p. 49-50).
This thesis presents a system for optimization of analog circuit topologies and component values. The topology is optimized using simulated annealing, while the component values are optimized using gradient descent. Local minima are avoided and constraints are kept through the use of coordinate transformations, as well as the use of default starting points for component values. The system is targeted for use in 3D integrated circuit design. The architecture is extendable, and is designed to eventually include capabilities for automated layout and mixed-signal design.
by Piotr Mitros.
M.Eng.
Lui, Siu-hong. "Analog circuit design by nonconvex polynomial optimization two design examples /." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39557418.
Full textSeda, Steven J. "Symbolic analysis for analog circuit design automation /." Zürich, 1993. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=10058.
Full textHe, Lizhong. "1-Ghz CMOS Analog Signal Squaring Circuit." Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1472476550.
Full textPradhan, Almitra. "Accurate analog synthesis with circuit matrix models." Cincinnati, Ohio : University of Cincinnati, 2009. http://rave.ohiolink.edu/etdc/view.cgi?acc_num=ucin1258661691.
Full textAdvisor: Ranga Vemuri. Title from electronic thesis title page (viewed Jan. 19, 2010). Keywords: VLSI; Analog circuit synthesis; Circuit Matrix; Fast model evaluations; Parasitic aware design. Includes abstract. Includes bibliographical references.
Odame, Kofi. "Exploiting device nonlinearity in analog circuit design." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29751.
Full textCommittee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Butera, Robert; Committee Member: Minch, Bradley; Committee Member: Taylor, David. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Hu, Zongqi. "Analog integrated circuit design of hypertrellis decoders /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20HU.
Full textBhattacharya, Sambuddha. "Template-driven parasitic-aware optimization of analog/RF IC layouts /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6121.
Full textFayed, Ayman Adel. "Adaptive techniques for analog and mixed signal integrated circuits." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1097519730.
Full textTitle from first page of PDF file. Document formatted into pages; contains xix, 232 p.; also includes graphics (some col.). Includes bibliographical references (p. 222-230).
Lui, Siu-hong, and 呂小康. "Analog circuit design by nonconvex polynomial optimization: two design examples." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39557418.
Full textCakir, Sinan. "Tolerance Based Reliability Of An Analog Electric Circuit." Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12612929/index.pdf.
Full textWorst Case Circuit Tolerance Analysis&rdquo
(WCCTA) and &ldquo
Failure Modes and Effects Analysis&rdquo
(FMEA). WCCTA involves the analysis of the circuit operation under varying parameters in their tolerance bands. These parameters include the resistances of the resistors, operating temperature and voltage input value. The operation of FPDC is checked and the most critical parameters are determined in the worst case conditions. While performing WCCTA, a method that guarantees the exact worst case conditions is used rather than probabilistic methods like Monte Carlo analysis. The results showed that the parameter variations do not affect the circuit operation unfavorably
operating temperature, voltage input variation and tolerance bands for the resistances are fairly compatible with the circuit operation. FMEA is implemented according to the short circuit and open circuit failures of all the electronic components used in FPDC. The components whose failure has catastrophic effect on the circuit operation have been determined and some preventive actions have been offered for some catastrophic failures.
Pradhan, Almitra. "Accurate Analog Synthesis Based On Circuit Matrix Models." University of Cincinnati / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1258661691.
Full textCheung, Wing-tai. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39558526.
Full textLuo, Ji. "Circuit design and routing for field programmable analog arrays." College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/3167.
Full textThesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
Serrano, Guillermo J. "High Performance Analog Circuit Design Using Floating-Gate Techniques." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19819.
Full textYildirim, Egemen. "Development Of Multi-layered Circuit Analog Radar Absorbing Structures." Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12614314/index.pdf.
Full texts knowledge, designed absorbers are superior in terms of frequency bandwidth to similar studies conducted so far in the literature. For broadband scattering characterization of periodic structures, numerical codes are developed. The introduced method is improved with the employment of developed FDTD codes to the proposed method. By taking the limitations regarding production facilities into consideration, a five-layered circuit analog absorber is designed and manufactured. It is shown that the manufactured structure is capable of 15 dB reflectivity minimization in a frequency band of 3.2-12 GHz for normal incidence case with an overall thickness of 14.2 mm.
Fei, Haibo. "High linearity analog and mixed-signal integrated circuit design." [Ames, Iowa : Iowa State University], 2007.
Find full textAggarwal, Varun. "Analog circuit optimization using evolutionary algorithms and convex optimization." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40525.
Full textIncludes bibliographical references (p. 83-88).
In this thesis, we analyze state-of-art techniques for analog circuit sizing and compare them on various metrics. We ascertain that a methodology which improves the accuracy of sizing without increasing the run time or the designer effort is a contribution. We argue that the accuracy of geometric programming can be improved without adversely influencing the run time or increasing the designer's effort. This is facilitated by decomposition of geometric programming modeling into two steps, which decouples accuracy of models and run-time of geometric programming. We design a new algorithm for producing accurate posynomial models for MOS transistor parameters, which is the first step of the decomposition. The new algorithm can generate posynomial models with variable number of terms and real-valued exponents. The algorithm is a hybrid of a genetic algorithm and a convex optimization technique. We study the performance of the algorithm on artificially created benchmark problems. We show that the accuracy of posynomial models of MOS parameters is improved by a considerable amount by using the new algorithm. The new posynomial modeling algorithm can be used in any application of geometric programming and is not limited to MOS parameter modeling. In the last chapter, we discuss various ideas to improve the state-of-art in circuit sizing.
by Varun Aggarwal.
S.M.
Mitros, Piotr 1979. "Constraint satisfaction modules : a methodology for analog circuit design." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/42237.
Full textIncludes bibliographical references (p. 119-122).
This dissertation describes a methodology for solving convex constraint problems using analog circuits. It demonstrates how this methodology can be used to design circuits that solve function-fitting problems through iterated gradient descent. In particular, it shows how to build a small circuit that can model a nonlinearity by observation, and predistort to compensate for this nonlinearity. The system fits into a broader effort to investigate non-traditional approaches to circuit design. First, it breaks the traditional input-output abstraction barrier; all ports are bidirectional. Second, it uses a different methodology for proving system stability with local rather than global properties. Such stability arguments can be scaled to much more complex systems than traditional stability criteria.
by Piotr Mitros.
Ph.D.
Bagheri, Rajeoni Alireza. "ANALOG CIRCUIT SIZING USING MACHINE LEARNING BASED TRANSISTORCIRCUIT MODEL." University of Akron / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=akron1609428170125214.
Full textWOLFE, GLENN A. "PERFORMANCE MACRO-MODELING TECHNIQUES FOR FAST ANALOG CIRCUIT SYNTHESIS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100027722.
Full textTung, Kenny W. L. Carleton University Dissertation Engineering Electronics. "A technique for on-chip analog VLSI circuit testing." Ottawa, 1993.
Find full textPatenaude, Jean-Marc G. (Jean-Marc Guy) Carleton University Dissertation Engineering Electronics. "A Methodology for analog circuit design and knowledge transfer." Ottawa, 1996.
Find full textAle, Anil Kumar. "Comparison and Evaluation of Existing Analog Circuit Simulator using Sigma-Delta Modulator." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5422/.
Full textChoi, Pyung. "An equivalent circuit structure macromodel for analog phase locked loops." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/14875.
Full textLe, Huy X. P. "Characterization of hot-carrier reliability in analog sub-circuit design." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/41379.
Full textIncludes bibliographical references (leaves 52-54).
by Huy X.P. Le.
M.Eng.
Monzon, Joshua Jen C. "Analog VLSI circuit design of spike-timing-dependent synaptic plasticity." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/54636.
Full textCataloged from PDF version of thesis.
Includes bibliographical references (p. 61-63).
Synaptic plasticity is the ability of a synaptic connection to change in strength and is believed to be the basis for learning and memory. Currently, two types of synaptic plasticity exist. First is the spike-timing-dependent-plasticity (STDP), a timing-based protocol that suggests that the efficacy of synaptic connections is modulated by the relative timing between presynaptic and postsynaptic stimuli. The second type is the Bienenstock-Cooper-Munro (BCM) learning rule, a classical ratebased protocol which states that the rate of presynaptic stimulation modulates the synaptic strength. Several theoretical models were developed to explain the two forms of plasticity but none of these models came close in identifying the biophysical mechanism of plasticity. Other studies focused instead on developing neuromorphic systems of synaptic plasticity. These systems used simple curve fitting methods that were able to reproduce some types of STDP but still failed to shed light on the biophysical basis of STDP. Furthermore, none of these neuromorphic systems were able to reproduce the various forms of STDP and relate them to the BCM rule. However, a recent discovery resulted in a new unified model that explains the general biophysical process governing synaptic plasticity using fundamental ideas regarding the biochemical reactions and kinetics within the synapse. This brilliant model considers all types of STDP and relates them to the BCM rule, giving us a fresh new approach to construct a unique system that overcomes all the challenges that existing neuromorphic systems faced. Here, we propose a novel analog verylarge- scale-integration (aVLSI) circuit that successfully and accurately captures the whole picture of synaptic plasticity based from the results of this latest unified model. Our circuit was tested for all types of STDP and for each of these tests, our design was able to reproduce the results predicted by the new-found model. Two inputs are required by the system, a glutamate signal that carries information about the presynaptic stimuli and a dendritic action potential signal that contains information about the postsynaptic stimuli. These two inputs give rise to changes in the excitatory postsynaptic current which represents the modifiable synaptic efficacy output. Finally, we also present several techniques and alternative circuit designs that will further improve the performance of our neuromorphic system.
by Joshua Jen C. Monzon.
M.Eng.
YANG, HUIYING. "SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS." University of Cincinnati / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1167665537.
Full textZhang, Chenglong. "LOW-POWER LOW-VOLTAGE ANALOG CIRCUIT TECHNIQUES FOR WIRELESS SENSORS." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/982.
Full textSobe, Udo, Karl-Heinz Rooch, and Dietmar Mörtl. "Simulation and Analysis of Analog Circuit and PCM (Process Control Monitor) Test Structures in Circuit Design." Universitätsbibliothek Chemnitz, 2007. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200700919.
Full textXia, Bo. "Analog-to-digital interface design in wireless receivers." Texas A&M University, 2004. http://hdl.handle.net/1969.1/3260.
Full textShana'a, Osama K. "Circuit Implementation of a High-speed Continuous-time Current-mode Field Programmable Analog Array (FPAA)." PDXScholar, 1996. https://pdxscholar.library.pdx.edu/open_access_etds/5103.
Full text張永泰 and Wing-tai Cheung. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39558526.
Full textLiang, Guojin. "Current mode analog and digital circuit design." Thesis, 1990. http://hdl.handle.net/1957/37923.
Full textGraduation date: 1991
Lin, Po-Hung, and 林柏宏. "Hierarchical Analog Circuit Placement." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/54362270604288177198.
Full text國立臺灣大學
電子工程學研究所
97
In modern analog layout design, it is very important to consider layout design hierarchy for better layout quality and circuit performance especially when conducting analog device placement. To reduce unwanted parasitic effects arising from device mismatches and circuit sensitivities due to thermal gradients and process variation, it is also essential to consider device matching, device symmetry, and device proximity in each hierarchy. In addition, when integrating power and non-power devices on the same chip, the preferred thermal profile should be further considered for better thermal device matching. In this dissertation, we present a hierarchical analog placement approach with the consideration of layout design hierarchy by introducing the novel hierarchical B*-tree (HB*-tree) and automatically symmetric-feasible B*-tree (ASF-B*-tree) floorplan representations. To further achieve the most important layout constraints including, device matching, (hierarchical) device symmetry, and (hierarchical) device proximity, as well as the preferred thermal profile, we propose: (1) a pattern-based matching placement and routing approach to facilitate the layout generation of matching device groups, such as current mirrors, (2) the first linear-time packing algorithm for analog placement with symmetry constraints by introducing the symmetry-island formulation for symmetry device groups, such as differential circuits, (3) the first analog placement approach based on hierarchical circuit clustering by exploring the correlation between the proximity constraints and properties of HB*-trees, and (4) the first thermal-driven analog placement considering thermal device matching by directly optimizing the thermal profile on the chip. Experimental results based on the analog benchmark circuits show that our hierarchical analog placement approach is the most effective one to handle analog placement with matching, (hierarchical) symmetry, and (hierarchical) proximity constraints. It can achieve the best published runtime efficiency and analog circuit performance/accuracy with the least impact due to the thermal gradient.
Weng, Yu-Cheng, and 翁于正. "Analog Beamforming Circuit for." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/83995072798022030438.
Full text國立交通大學
電機學院電信學程
103
A phase compensation circuit is designed for self-steering antenna arrays. The approach is verified by a PCB module operated at 900 MHz. The advantages of the proposed design include improved phase detection without ambiguity of the arrival direction and with small tuning range of the phase shifting. The summed output power varies less than 0.5 dB in the measurement of sinusoidal input signals. Signals with 16-QAM modulation are also inspected with good phase compensation.
huang, chfa, and 黃志發. "Analog filter circuit design." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/43740565617656547156.
Full text國立中興大學
電機工程學系
91
This thesis described the design and implementation of analog filter design. We use non-opamp-based unity gain buffer to construct high-speed filter architecture. The experiment result show that we can arrive the cutoff frequency about 200Mhz.We also realize Gm-C filter with GaAs HBT technology. A high linear transconductance is used by 4:1 emitter ratio topology and we use negative resistance to improve the output impedance of transconductance. The measurement result show that we realize a 3rd order Butterworth filter by cascading method .The cutoff frequency is about 10Mhz.We also use LC ladder signal-flow to realize 5th order Elliptic filter, which is suit for baseband frequency application. The transconductance is realized in rail-to-rail topology. In the chapter six we will realize a polyphase filter to reject the image signal . The principle of a polyphase filter is different to symmetric analog filter .We use the transformation from LP to BP to realize the image rejection. The measured results verify our design and implementation of analog filter . They also provide theory and implementation
Chiang, Bo-Hao, and 姜博浩. "Analog Circuit Automatic Placement Tool." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/01456895177131173844.
Full text國立中正大學
資訊工程研究所
99
Semiconductor technology has made incredibly progress since the first electronic product was created. In contrast to digital circuits, however, the analog circuit automatic layout tool is in its comparative infancy. In order to shorten the development and design cycle of an analog layout, we propose an innovative approach to solve this issue and remedy the shortcoming of the previous work in this thesis. Our work can reduce the solution space of a floorplan and the thesis proposes the newly operation with respect to slicing tree structure. First, the sensitive MOSs are put together, and then applies a novel method to achieve global symmetry for non-sensitive MOSs in a circuit. The result shows that our approach is effective in improving the gain, bandwidth, and phase margin compared to the previous work.
SHEN, DING-HONG, and 沈定宏. "Integrated Circuit Layout Implementation of ECG Analog Front-end Circuits." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/w8d58k.
Full text中華大學
電機工程學系
107
This thesis complete pre-layout simulations and circuit layouts of a single-lead and a multi-lead ECG analog front-end circuits. Our proposed ECG analog front-end circuit includes an instrumentation amplifier, a band-pass filter, and a post-amplifier. Besides, we use a driving right Leg (DRL) circuit to filter out common mode interference. At first, we create an operational amplifier (OPA). Subsequently, we based on this OPA to construct a single-lead and a multi-lead ECG analog front-end circuit. We used the UMC 0.18um 2P6M CMOS process provided by National Applied Research Laboratories (NAR Labs) / Taiwan Semiconductor Research Institute (TSRI) to complete our proposed ECG analog front-end circuits. At present, pre-layout simulations and layout designs of single-lead and three-lead ECG analog front-end integrated circuits have completed. Integrating multi-lead ECG analog front-end integrated circuit components and embedded microcontrollers with built-in analog-to-digital converters to construct multi-lead ECG measurement systems can significantly reduce the volume of the systems. The results of our work will be a part of multi-lead ECG measurement system-on-chip (SoC) in the future.
嚴旭民. "Analysis and Integrated Circuit Layout of EEG Analog Front-end Circuits." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/92h33p.
Full text中華大學
電機工程學系
107
The purpose of this thesis is to design a better efficiency EEG analog front-end circuit with compact size. We used the UMC 0.18um 2P6M CMOS process provided by National Applied Research Laboratories (NAR Labs) / Taiwan Semiconductor Research Institute (TSRI) to implement the analog front-end circuit of EEG machines. Due to the reduction in the size of the circuit, it can be applied to a wearable EEG machine in the future. This thesis consists of two parts, the first part is design of operational amplifiers, and the second part is to use this design of operational amplifiers to construct EEG analog front-end circuits. In the future, we will add an analog-to-digital converter (ADC) to our EEG analog front-end circuits to convert the output into a digital signal. As a result, subsequent application systems will be made easier to design.
Silva, Bruno. "Analog Circuit Design With Transparent Electrics." Dissertação, 2013. http://hdl.handle.net/10216/75619.
Full textLiu, Kun-Lin, and 劉昆霖. "Observer Based Analog Circuit Fault Diagnosis." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/27955432084979015837.
Full text逢甲大學
電子工程所
96
In this thesis, observer-based analog circuit diagnosis is presented. A significant portion of the fault diagnosis of the analog circuits relies on the state variables obtained from the testing node. Unfortunately, in practice, not all the state variables are accessible, and in general only the outputs of the circuit under test (CUT) are measurable. Therefore, it is necessary to observe the states from information contained in the output as well as the input variables when not all states are accessible. The subsystem that performs the observation of the state variables based on information received from the measurements of the input and output is called a state observer. Moreover, a fault diagnosis methodology is proposed based on vector fitting (VF) to analyze the analog circuit. VF is used to process the circuit frequency responses and to build the fault dictionary. From the simulation results, we can find the proposed technique is succeeded in diagnosing and locating faults quickly and exactly.
Hsu, Chun-Chen, and 許鈞程. "CMOS Analog Circuit Layout Design Automation." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/62541285242114704365.
Full text國立成功大學
電機工程學系碩博士班
91
Layout design is a very important step in the analog CMOS IC design flow. Good layout quality should feature low susceptibility to digital noise and low sensitivity to process variation. It has historically been a time-consuming, manual task. The fast growth of complexity of VLSI systems and recent advances in System-On-Chip (SOC) developments, make it necessary to have powerful Computer-Aided-Design (CAD) tools to speed up the design process. This issue is especially important for analog circuit layout design. In this thesis, we present a tool to automate analog layout design with analog basic considerations (matching, symmetry, and noise coupling). It covers from device level module generation to block level placement and routing. Fist, we provide a module generator to transfer partitioned netlists to physical layout with matching consideration. Placement tool then places all cells with symmetric, wire length, and area constraints. Obstacle-avoiding shortest finding algorithm is used for our basic routing algorithm and we propose an approach to avoiding noise coupling between noisy and sensitive nets. According to experimental results, our tool can handle analog circuit layout with user specified constraints in the reasonable time and make analog layout design more efficient.
Silva, Bruno Filipe Guedes da. "Analog Circuit Design With Transparent Electrics." Master's thesis, 2013. https://repositorio-aberto.up.pt/handle/10216/67737.
Full textChen, Shih-Hung, and 陳世浤. "Virtual Bass with Analog Circuit Realization." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/86661687637049291454.
Full text國立成功大學
電機工程學系碩博士班
95
The goal of this thesis is to propose a new algorithm of virtual bass with analog circuits realization. The proposed method utilized the technique of psycho-acoustic to enhance low frequency parts of the audio signals without other costs in contrast with conventional methods which have trade-off in some performances. Poor low frequency response of small size speakers and headphones is a well-known problem. In this thesis, a new algorithm with proposed harmonics generator is first presented that we make use of theorem of missing fundamental to generate harmonics of fundamental frequency and replace it. Then the compensation followed by equal-loudness contour analysis is made to achieve the technique of loudness matching. The processed low frequency components of audio signals are then added with original high frequency components to replace the original audio signals. It is so-called virtual bass. The proposed harmonics generator includes a hysteresis comparison generator and a half-wave rectifier to generate odd and even harmonics. We also propose some simple architecture composed of analog circuits to realize the proposed algorithm which include the proposed full-wave rectifier, odd harmonics generator and even harmonics generator and use the switched-capacitor to replace the large resistance to realize filters. The detailed verification and performance will be described in the following chapters.
Yu-Chang, Wu, and 吳佑璋. "Analog Circuit Operational Amplifier Automatic Routing." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/55113232735025245215.
Full text國立中正大學
資訊工程研究所
101
Semiconductor technology has made incredibly progress since the first electronic product was created. In contrast to digital circuits, however the analog circuit automatic layout tool is in its comparative infancy. In order to shorten the development and design cycle of an analog layout, we approach to the experience of engineer to increase the performance of automatic layout. Our work proposed computing parasitic capacity as cost function and optimizing segments’ interconnections and optimizing nets’ bends in routing. We mandated the symmetry nets symmetry strictly to match matching and to ensure the performance of circuit by circuit parsing. In automatic placement, we continued and optimized the work [1] of our laboratory in 2011 by modifying symmetry constraints and Process migration from 350nm to 180nm. Our work could totally achieve the circuit specification in Gain. The result of our program could pass DRC, LVS verification without manual modified and short the design cycle of an analog layout efficiently. We improved the method in Rectilinear Steiner tree and rotated the instances to compact circuit area. Keyword: analog routing, symmetry matching, capacity matching.
Silva, Bruno Filipe Guedes da. "Analog Circuit Design With Transparent Electrics." Dissertação, 2013. https://repositorio-aberto.up.pt/handle/10216/67737.
Full text