Journal articles: 'Analog circuit'

1

Liu, Xiaoxin, Lanqing Zou, Chenyang Huang, Na Bai, Kanhao Xue, Huajun Sun, and Xiangshui Miao. "Analog Memristor-Based Dynamic Programmable Analog Filter." Journal of Physics: Conference Series 2356, no. 1 (October 1, 2022): 012008. http://dx.doi.org/10.1088/1742-6596/2356/1/012008.

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The memristor study now generally exhibit threshold voltage characteristics. The memristance changes when the voltage across the memristor is greater than the threshold voltage. Otherwise, the memristance is almost constant. Based on this feature, we design a general-purpose memristor programmable circuit that is simple to operate. In the field of communication and signal processing, programmable analog filters are required, and memristors with multi-valued characteristic are suitable as programmable impedance elements for such circuits. Through simulation and physics experiments, we demonstrate a memristor-based programmable low-pass filter using the designed programmable circuit to realize the dynamic adjustment of circuit parameters.

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Kushwah, Ravindra Singh, and Shyam Akashe. "FinFET Based Tunable Analog Circuit: Design and Analysis at 45 nm Technology." Chinese Journal of Engineering 2013 (October 24, 2013): 1–8. http://dx.doi.org/10.1155/2013/165945.

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We included a designing of low power tunable analog circuits built using independently driven FinFETs devices, where the controlling of the back gate provide the output on the front gate. We show that this could be an effective solution to conveniently tune the output of bulk CMOS analog circuits particularly for Schmitt trigger and operational transconductance amplifier circuits. FinFET devices can be used to increase the performance by reducing the leakage current and power dissipation, because front and back gates both are independently controlled. FinFET device has a higher controllability, resulting relatively high Ion/Ioff ratio. In this paper, we proposed a tunable analog circuit such as CMOS amplifier circuit, Schmitt trigger circuit, and operational transconductance amplifier circuit, these circuit blocks are necessary for low noise high performance ICs for analog applications. Gain, phase, group delay, and output response of analog tunable circuits have been discussed in this paper. The proposed FinFET based analog tunable circuits have been designed using Cadence Virtuoso tool at 45 nm.

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Jiao, Su Min, Cai Hong Wang, and Xue Mei Wang. "Large-Scale Analog Circuit Evolutionary Design Using a Real-Coded Scheme." Applied Mechanics and Materials 220-223 (November 2012): 2036–39. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.2036.

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Analog circuits are of great importance in electronic system design. Recent evolutionary design results are usually small-scale analog circuits. This paper proposes a real-coded mechanism and uses it in the large-scale analog circuit evolutionary design. The proposed scheme evolves the circuit topology and size to a uniformed continuous space, in which the circuit representation is closed and of causality. Experimental results show that the proposed scheme can work successfully on many analog circuits with different kinds of characteristics. Comparing with other evolutionary methods before, the proposed scheme performs better on large-scale problems of circuit synthesis with higher search efficiency, lower computational complexity, and less computing time.

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WANG, WEIZHI, and DONGMING JIN. "CMOS DESIGN OF ANALOG FUZZY SYSTEM." Journal of Circuits, Systems and Computers 14, no. 06 (December 2005): 1101–12. http://dx.doi.org/10.1142/s0218126605002830.

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This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high precision.

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SAKUL, CHAIWAT, and KOBCHAI DEJHAN. "FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS." Journal of Circuits, Systems and Computers 21, no. 03 (May 2012): 1250024. http://dx.doi.org/10.1142/s0218126612500247.

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This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.

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Wang, Yong Xi, and Mei Hu. "Analog Circuit Parameters Measurement System Based on Multiplier." Advanced Materials Research 989-994 (July 2014): 3041–44. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.3041.

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For the more complicated principles and the lower accuracy for the existing methods of the measurement of the analog circuit parameters, the paper constructs a measurement system for the analog circuits parameters based on the multiplier. The signal source generates two orthogonal sinusoidal analog signals with same frequency, and then one of the signals goes through the analog circuits. Then the multiplication and filtering are completed with the two DC signals. At last the phase and amplitude of the analog circuit are obtained through the DAQ and LabVIEW software. The amplitude and phase errors are less than 3%. The results show that the system has simple circuit, fast speed and high accuracy. So it is a feasible plan for the measurement system of the analog circuit parameters at present.

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7

Frank, Steve. "Brief Introduction to High Speed Analog Failure Analysis." EDFA Technical Articles 5, no. 3 (August 1, 2003): 23–28. http://dx.doi.org/10.31399/asm.edfa.2003-3.p023.

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Abstract This article provides a high level overview of high speed analog circuits and associated failure analysis techniques. It discusses the failure modes and mechanisms of voltage reference circuits, high speed op amps, and digital-to-analog and analog-to-digital converters, the fundamental building blocks used to create high speed analog devices. It also explains how to deal with difficulties involving circuit node access, circuit loading, and performance.

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Rojec, Žiga, Iztok Fajfar, and Árpád Burmen. "Evolutionary Synthesis of Failure-Resilient Analog Circuits." Mathematics 10, no. 1 (January 5, 2022): 156. http://dx.doi.org/10.3390/math10010156.

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Analog circuit design requires large amounts of human knowledge. A special case of circuit design is the synthesis of robust and failure-resilient electronics. Evolutionary algorithms can aid designers in exploring topologies with new properties. Here, we show how to encode a circuit topology with an upper-triangular incident matrix and use the NSGA-II algorithm to find computational circuits that are robust to component failure. Techniques for robustness evaluation and evolutionary algorithm guidances are described. As a result, we evolve square root and natural logarithm computational circuits that are robust to high-impedance or short-circuit malfunction of an arbitrary rectifying diode. We confirm the simulation results by hardware circuit implementation and measurements. We think that our research will inspire further searches for failure-resilient topologies.

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9

Hurst, S. L. "Analog circuit design." Microelectronics Journal 28, no. 2 (February 1997): 200–201. http://dx.doi.org/10.1016/s0026-2692(97)83458-1.

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10

Stojcev, M. "Analog circuit design." Microelectronics Journal 29, no. 12 (December 1998): 1039–40. http://dx.doi.org/10.1016/s0026-2692(98)00057-3.

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Milovanovi, Dragia P. "Analog integrated circuit." Microelectronics Journal 29, no. 8 (August 1998): 572–73. http://dx.doi.org/10.1016/s0026-2692(98)80020-7.

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WAWRYN, KRZYSZTOF. "AN ARTIFICIAL INTELLIGENCE APPROACH TO ANALOG CIRCUIT DESIGN." Journal of Circuits, Systems and Computers 01, no. 02 (June 1991): 149–76. http://dx.doi.org/10.1142/s0218126691000033.

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This article deals with a new approach to an intelligent analog circuit design. The iterative closed loop design methodology adopts an expert system approach to provide topological synthesis, the SPICE circuit simulator to evaluate the circuit performance and a new approach of the diagnostic expert system to provide advice on how to improve the design. Unlike previous design methods, this approach introduces formal circuit representation for both numerical and heuristic knowledge of the design system. The predicate logic circuit representation is proposed to introduce a new concept of a formal analog circuit description language. The language syntax and semantics provide precise symbolic description of analog circuits functionality at different levels of hierarchy and connectivities together with transistor sizes of CMOS circuits at the transistor level. Different levels of hierarchy with circuit structures and performance parameters are presented in detail. It is shown how sentence conversion rules of language grammar can be used to derive transistor level circuits from input performance specifications through all intermediate levels of hierarchy. The implementation of the methodology and associated experimental results for CMOS operational amplifier designs are presented.

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13

Bae, Woorham. "CMOS Inverter as Analog Circuit: An Overview." Journal of Low Power Electronics and Applications 9, no. 3 (August 20, 2019): 26. http://dx.doi.org/10.3390/jlpea9030026.

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Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.

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Bartolozzi, Chiara, and Giacomo Indiveri. "Synaptic Dynamics in Analog VLSI." Neural Computation 19, no. 10 (October 2007): 2581–603. http://dx.doi.org/10.1162/neco.2007.19.10.2581.

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Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.

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15

Grib, Alexandru, Zoltan Erdei, Mihaela Cristina Turcu, Alina Constantin, and Mihai Iordache. "Using Pathological Elements in Analog Circuit Analysis and Simulation." Carpathian Journal of Electronic and Computer Engineering 13, no. 2 (December 1, 2020): 1–6. http://dx.doi.org/10.2478/cjece-2020-0006.

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Abstract This paper is focused on some kind of mystery circuit nullator, nullor, current mirror, and voltage mirror, all of them known as pathological elements. These pathological elements can be used to perform circuit modelling, symbolic circuit analysis, circuit synthesis, circuit design and to develop applications that involve modern active devices. It is described a new modeling of nullor-based active devices from the circuit abstraction level. In this paper it is presented the way all types of equations which describe the circuit containing nullors can be directly formulated from the diagrams of these circuits if we took into account that a nullator is an over-determined two-port circuit element (zero voltage, zero current) and the norator is an undetermined two-port circuit element (any voltage and any current). To simulate the nullors with ideal voltage controlled voltage sources, ec = Ac_c uc, with the control gate an ideal independent current source, jC = 0.0 A and with the amplification (transfer) factor Ac_C very big (theoretically ∞), the analog circuits with nullors can be analyzed by using any of the existing simulation software. By this way, it was possible the elaboration of efficient algorithms for an automatic formulation of Kirchhoff’s equations, of loop equations, of modified nodal equations and of state equations for circuits with pathological elements. These procedures can be easily implemented in dedicated programs for the simulations of the complex analog circuits with pathological elements. The example presented in this paper validates the presented models for nullors.

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Malcher, Andrzej, and Piotr Falkowski. "Analog Reconfigurable Circuits." International Journal of Electronics and Telecommunications 60, no. 1 (March 1, 2014): 8–19. http://dx.doi.org/10.2478/eletel-2014-0002.

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Abstract The aim of this paper is to present an overview of a new branch of analog electronics represented by analog reconfigurable circuits. The reconfiguration of analog circuits has been known and used since the beginnings of electronics, but the universal reconfigurable circuits called Field Programmable Analog Arrays (FPAA) have been developed over the last two decades. This paper presents the classification of analog circuit reconfiguration, examples of FPAA solutions obtained as academic projects and commercially available ones, as well as some application examples of the dynamic reconfiguration of FPAA

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Prajapati, Pankaj P., Anilkumar J. Kshatriya, Sureshbhai L. Bharvad, and Abhay B. Upadhyay. "Performance analysis of CMOS based analog circuit design with PVR variation." Bulletin of Electrical Engineering and Informatics 12, no. 1 (February 1, 2023): 141–48. http://dx.doi.org/10.11591/eei.v12i1.4357.

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Process, supply voltage, and temperature (PVT) are three important factors which contribute to performance variation of the complementary metal–oxide–semiconductor (CMOS) based analog circuits. In this paper, CMOS based analog circuit design with the PVT variation effects are explored. The effects of the PVT variation on the performance of CMOS based analog circuits are introduced. The optimization of CMOS based analog circuits such as differential amplifier (DA) and two-stage operational amplifier (op amp) circuits with PVT variations with different algorithms such as cockoo search (CS), particle swam optimization (PSO), hybrid CSPSO, and differential evaluation (DE) algorithms is presented. Each algorithm is implemented using the C programming language, interfaced with Ngspice circuit simulator, and tested on the Intel®core™ i5, 2.40 GHz processor with 8 GB internal RAM using the Ubuntu operating system (OS). The result shows PVT variation affects the performance of CMOS circuit.

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Alt, Samantha, Malgorzata Marek-Sadowska, and Li C. Wang. "Circuit Partitioning for Behavioral Full Chip Simulation Modeling of Analog and Mixed Signal Circuits." International Journal of Modeling and Optimization 4, no. 1 (2014): 74–80. http://dx.doi.org/10.7763/ijmo.2014.v4.350.

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Kinsht, Nikolay V., and Natalia N. Petrun’ko. "A Way to Chips Diagnosis by Short Circuits." Advanced Materials Research 918 (April 2014): 307–12. http://dx.doi.org/10.4028/www.scientific.net/amr.918.307.

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The various formulations of the technical diagnostics problem are possible when creation and use of analog circuits. One approach allows deviation a sufficiently large set of the elements parameters. The results of this diagnosis can be used to improve the technology of analog circuits or predict their behavior depending on the time of exposure or destabilizing factors. The power sources (current sources and emf) commonly used as a testing influence on circuit in realization test diagnosis. A short circuit approach of the testing experiments organization with active analog circuits with partly inaccessible nodes is considered.

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OKUBO, NAOFUMI. "Notice the Analog Circuit Technology. RF Systems Need Analog Circuit Technologies." Journal of the Institute of Electrical Engineers of Japan 118, no. 7/8 (1998): 422–25. http://dx.doi.org/10.1541/ieejjournal.118.422.

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OKAMOTO, HIROSHI. "Notice the Analog Circuit Technology. Largest Analog Circuit-Electric Power Systems." Journal of the Institute of Electrical Engineers of Japan 118, no. 7/8 (1998): 426–29. http://dx.doi.org/10.1541/ieejjournal.118.426.

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FLYNN, MICHAEL P., SUNGHYUN PARK, and CHUN C. LEE. "ACHIEVING ANALOG ACCURACY IN NANOMETER CMOS." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 255–75. http://dx.doi.org/10.1142/s0129156405003193.

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This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that VT matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.

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Nasser, Ahmed R., Ahmad Taher Azar, Amjad J. Humaidi, Ammar K. Al-Mhdawi, and Ibraheem Kasim Ibraheem. "Intelligent Fault Detection and Identification Approach for Analog Electronic Circuits Based on Fuzzy Logic Classifier." Electronics 10, no. 23 (November 23, 2021): 2888. http://dx.doi.org/10.3390/electronics10232888.

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Analog electronic circuits play an essential role in many industrial applications and control systems. The traditional way of diagnosing failures in such circuits can be an inaccurate and time-consuming process; therefore, it can affect the industrial outcome negatively. In this paper, an intelligent fault diagnosis and identification approach for analog electronic circuits is proposed and investigated. The proposed method relies on a simple statistical analysis approach of the frequency response of the analog circuit and a simple rule-based fuzzy logic classification model to detect and identify the faulty component in the circuit. The proposed approach is tested and evaluated using a commonly used low-pass filter circuit. The test result of the presented approach shows that it can identify the fault and detect the faulty component in the circuit with an average of 98% F-score accuracy. The proposed approach shows comparable performance to more intricate related works.

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Odame, K., and P. E. Hasler. "Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping." VLSI Design 2010 (March 18, 2010): 1–8. http://dx.doi.org/10.1155/2010/687498.

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Nonlinear signal processing is necessary in many emerging applications where form factor and power are at a premium. In order to make such complex computation feasible under these constraints, it is necessary to implement the signal processors as analog circuits. Since analog circuit design is largely based on a linear systems perspective, new tools are being introduced to circuit designers that allow them to understand and exploit circuit nonlinearity for useful processing. This paper discusses two such tools, which represent nonlinear circuit behavior in a graphical way, making it easy to develop a qualitative appreciation for the circuits under study.

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Li, Bo, and Guoyong Shi. "A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits." ACM Transactions on Design Automation of Electronic Systems 27, no. 1 (January 31, 2022): 1–24. http://dx.doi.org/10.1145/3474364.

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Since the memristor emerged as a programmable analog storage device, it has stimulated research on the design of analog/mixed-signal circuits with the memristor as the enabler of in-memory computation. Due to the difficulty in evaluating the circuit-level nonidealities of both memristors and CMOS devices, SPICE-accuracy simulation tools are necessary for perfecting the art of neuromorphic analog/mixed-signal circuit design. This article is dedicated to a native SPICE implementation of the memristor device models published in the open literature and develops case studies of applying such a circuit simulation with MOSFET models to study how device-level imperfections can make adversarial effects on the analog circuits that implement neuromorphic analog signal processing. Methods on memristor stamping in the framework of modified nodal analysis formulation are presented, and implementation results are reported. Furthermore, functional simulations on neuromorphic signal processing circuits including memristors and CMOS devices are carried out to validate the effectiveness of the native SPICE implementation of memristor models from the perspectives of simulation accuracy, efficiency, and convergence for large-scale simulation tasks.

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Rutkowski, Jerzy. "Identification of Circuit Parameters for the Specified or Measured Performances." International Journal of Electronics and Telecommunications 61, no. 1 (March 1, 2015): 95–100. http://dx.doi.org/10.1515/eletel-2015-0012.

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Abstract Extension of the method of analog circuit parameter identification for the specified design performances, originally presented by the same author in 1982, is described. These parameters are designated by means of PSpice simulation of the adjoint circuit to the original one. In this adjoint circuit, elements of the original circuit, described by the sized parameters, are replaced by controlled sources. Each such source is controlled by the differential voltage or current, difference between the calculated voltage or current and the specified one, with infinitely large gain. The method is applicable to both linear and nonlinear DC circuits and AC circuits and can be used in many fields of analog circuit design, such as: finding of acceptability region, analog fault diagnosis, postproduction identification and tuning. In the later cases, design performances are replaced by measurements of Circuit Under Test (CUT). Simplicity, extremely low computational complexity and high accuracy are the main benefits of the proposed, basic Circuit Theory based, approach - the solution is found after a single PSpice simulation. For better understanding of the presented methodology, five practical examples are discussed

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Mina, Rayan, Chadi Jabbour, and George E. Sakr. "A Review of Machine Learning Techniques in Analog Integrated Circuit Design Automation." Electronics 11, no. 3 (January 31, 2022): 435. http://dx.doi.org/10.3390/electronics11030435.

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Analog integrated circuit design is widely considered a time-consuming task due to the acute dependence of analog performance on the transistors’ and passives’ dimensions. An important research effort has been conducted in the past decade to reduce the front-end design cycles of analog circuits by means of various automation approaches. On the other hand, the significant progress in high-performance computing hardware has made machine learning an attractive and accessible solution for everyone. The objectives of this paper were: (1) to provide a comprehensive overview of the existing state-of-the-art machine learning techniques used in analog circuit sizing and analyze their effectiveness in achieving the desired goals; (2) to point out the remaining open challenges, as well as the most relevant research directions to be explored. Finally, the different analog circuits on which machine learning techniques were applied are also presented and their results discussed from a circuit designer perspective.

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Dieste-Velasco, M. Isabel. "Application of a Fuzzy Inference System for Optimization of an Amplifier Design." Mathematics 9, no. 17 (September 5, 2021): 2168. http://dx.doi.org/10.3390/math9172168.

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Simulation programs are widely used in the design of analog electronic circuits to analyze their behavior and to predict the response of a circuit to variations in the circuit components. A fuzzy inference system (FIS) in combination with these simulation tools can be applied to identify both the main and interaction effects of circuit parameters on the response variables, which can help to optimize them. This paper describes an application of fuzzy inference systems to modeling the behavior of analog electronic circuits for further optimization. First, a Monte Carlo analysis, generated from the tolerances of the circuit components, is performed. Once the Monte Carlo results are obtained for each of the response variables, the fuzzy inference systems are generated and then optimized using a particle swarm optimization (PSO) algorithm. These fuzzy inference systems are used to determine the influence of the circuit components on the response variables and to select them to optimize the amplifier design. The methodology proposed in this study can be used as the basis for optimizing the design of similar analog electronic circuits.

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Khan, Noor Mohmmed, Shubhangi Patil, Tushar Diggewadi, and Anand Gudnavar. "Cinch and Sterling Analog Circuits for Laboratory." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 6, no. 01 (June 25, 2017): 51–58. http://dx.doi.org/10.15662/ijareeie.2017.0601007.

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As we know that there is ever increasing demand for compact circuits and less complex wirings over the board, a technological boon evolved for such demand is Printed Circuit Board (PCB). A PCB will mechanically supports and electrically connects electronic components using conductive tracks, pads. These boards will have minimal chances for short circuits, components on the board are fixed; another advantage is creation of multiple boards using single design. Taking this technology forward to our everyday life, we implemented analog communication laboratory circuit, Schmitt trigger.

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Lu, Xinmiao, Cunfang Yang, Qiong Wu, Jiaxu Wang, Zihan Lu, Shuai Sun, Kaiyi Liu, and Dan Shao. "Research on Analog Circuit Soft Fault Diagnosis Method Based on Mathematical Morphology Fractal Dimension." Electronics 12, no. 1 (December 30, 2022): 184. http://dx.doi.org/10.3390/electronics12010184.

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It is difficult for traditional circuit-fault feature-extraction methods to accurately distinguish between nonlinear analog-circuit faults and analog-circuit faults with high fault rates and high diagnostic costs. To solve this problem, this paper proposes a method of mathematical morphology fractal dimension (VMD-MMFD) based on variational mode decomposition for soft-fault feature extraction in analog circuits. First, the signal is decomposed into variational modes to suppress the influence of environmental noise, and multiple high-dimensional eigenmode functions with different center frequencies are obtained. The fractal dimension of the signal feature information component IMF is calculated, and then, KPCA (Kernel Principal Component Analysis) is used to remove the overlapping and redundant parts of the data. The fault set obtained is used as the basis for judging the working state and the fault type of the circuit. The experimental results of the simulation circuits show that this method can be effectively used for circuit-fault diagnosis.

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Wang, Yuehai, Yongzheng Yan, and Qinyong Wang. "Wavelet-Based Feature Extraction in Fault Diagnosis for Biquad High-Pass Filter Circuit." Mathematical Problems in Engineering 2016 (2016): 1–13. http://dx.doi.org/10.1155/2016/5682847.

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Fault diagnosis for analog circuit has become a prominent factor in improving the reliability of integrated circuit due to its irreplaceability in modern integrated circuits. In fact fault diagnosis based on intelligent algorithms has become a popular research topic as efficient feature extraction and selection are a critical and intricate task in analog fault diagnosis. Further, it is extremely important to propose some general guidelines for the optimal feature extraction and selection. In this paper, based on wavelet analysis, we will study the problems of mother wavelets selection, number of decomposition levels, and candidate coefficients selection by using a four-op-amp biquad filter circuit. After conducting several comparative experiments, some general guidelines for feature extraction for this type of analog circuits fault diagnosis are derived.

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Xiang, Qing. "Analog Circuit Course Teaching Method Based on the Analysis of Classic Application Circuits." International Journal for Innovation Education and Research 8, no. 9 (September 1, 2020): 197–204. http://dx.doi.org/10.31686/ijier.vol8.iss9.2612.

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Analog circuit course is a compulsory professional basic course for engineering majors such as automation and electronic information engineering. Since traditional teaching methods cannot enable students to effectively master the knowledge of analog circuits, this article proposes a teaching method of analog circuits based on the analysis of classic application circuits, including the idea of selecting classic application circuits, "seeing pictures, impression enhancement method of “reading, drawing and memorizing circuit diagram" and hands-on implementation of classic circuits. Through the practice of teaching reform for one semester, the results show that the teaching method enhances students' enthusiasm for learning, enables students to integrate theoretical knowledge, deeply understand application circuits, and then carry out practical applications or innovate on this basis.

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Harjani, R., and B. Vinnakota. "Analog circuit observer blocks." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 44, no. 3 (March 1997): 154–63. http://dx.doi.org/10.1109/82.558450.

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Hurst, Stanley L. "Analog integrated circuit design." Microelectronics Journal 29, no. 6 (June 1998): 361–62. http://dx.doi.org/10.1016/s0026-2692(97)00051-7.

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Chen, Shen Li, and C. K. Lee. "A Single-Chip Design for the Three-Phase BDCM System." Applied Mechanics and Materials 271-272 (December 2012): 742–46. http://dx.doi.org/10.4028/www.scientific.net/amm.271-272.742.

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In this work, we present a sensorless single-chip design for the three-phase brushless DC motors (BDCM) system, and which is implemented by a 0.35um CMOS process. A mixed-signal IC will be accomplished by the implementation of analog circuit and digital circuit in the same chip. Eventually, this chip system includes an analog circuit (Hall signal amplifier), a digital circuit (logic process block), and a frequency voltage converter (FVC) to complete the control & driving circuits. Experimental results are included to verify the proposed scheme.

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Koseoglu, Murat, Furkan Nur Deniz, Baris Baykant Alagoz, Ali Yuce, and Nusret Tan. "An experimental analog circuit realization of Matsuda’s approximate fractional-order integral operators for industrial electronics." Engineering Research Express 3, no. 4 (December 1, 2021): 045041. http://dx.doi.org/10.1088/2631-8695/ac3e11.

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Abstract Analog circuit realization of fractional order (FO) elements is a significant step for the industrialization of FO control systems because of enabling a low-cost, electric circuit realization by means of standard industrial electronics components. This study demonstrates an effective operational amplifier-based analog circuit realization of approximate FO integral elements for industrial electronics. To this end, approximate transfer function models of FO integral elements, which are calculated by using Matsuda’s approximation method, are decomposed into the sum of low-pass filter forms according to the partial fraction expansion. Each partial fraction term is implemented by using low-pass filters and amplifier circuits, and these circuits are combined with a summing amplifier to compose the approximate FO integral circuits. Widely used low-cost industrial electronics components, which are LF347N opamps, resistor and capacitor components, are used to achieve a discrete, easy-to-build analog realization of the approximate FO integral elements. The performance of designed circuit is compared with performance of Krishna’s FO circuit design and performance improvements are shown. The study presents design, performance validation and experimental verification of this straightforward approximate FO integral realization method.

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CAPONETTO, RICCARDO, ANDREA DI MAURO, LUIGI FORTUNA, and MATTIA FRASCA. "FIELD PROGRAMMABLE ANALOG ARRAY TO IMPLEMENT A PROGRAMMABLE CHUA'S CIRCUIT." International Journal of Bifurcation and Chaos 15, no. 05 (May 2005): 1829–36. http://dx.doi.org/10.1142/s0218127405012806.

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This paper introduces a new application of the Field Programmable Analog Array. Ease of design and reprogrammability are the advantages offered by this class of analog circuits, making them an ideal environment for the implementation of chaotic circuits and their experimental characterization. Chua's circuit, a well-known paradigm of nonlinear circuits, has been used as an example of application. Experimental results show the suitability of the approach, highlighting the features of the new implementation: a fully on the fly programmable Chua's circuit has been obtained.

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GYÖRÖK, György. "FUNCTIONAL SWITCHING MATRIX FOR AUTOMATIC ANALOG CIRCUIT SYNTHESIS." Acta Electrotechnica et Informatica 14, no. 3 (September 1, 2014): 61–65. http://dx.doi.org/10.15546/aeei-2014-0031.

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Lukić, Jelena, and Dragan Denić. "A Novel Design Of An NTC Thermistor Linearization Circuit." Metrology and Measurement Systems 22, no. 3 (September 1, 2015): 351–62. http://dx.doi.org/10.1515/mms-2015-0035.

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Abstract A novel design of a circuit used for NTC thermistor linearization is proposed. The novelty of the proposed design consists in a specific combination of two linearization circuits, a serial-parallel resistive voltage divider and a two-stage piecewise linear analog-to-digital converter. At the output of the first linearization circuit the quasi-linear voltage is obtained. To remove the residual voltage nonlinearity, the second linearization circuit, i.e., a two-stage piecewise linear analog-to-digital converter is employed. This circuit is composed of two flash analog-to-digital converters. The first analog-to-digital converter is piecewise linear and it is actually performing the linearization, while the second analog-to-digital converter is linear and it is performing the reduction of the quantization error introduced by the first converter. After the linearization is performed, the maximal absolute value of a difference between the measured and real temperatures is 0.014°C for the temperature range between −25 and 75°C, and 0.001°C for the temperature range between 10 and 40°C.

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Zhou, Jingyu, Shulin Tian, and Chenglin Yang. "A Novel Prediction Method about Single Components of Analog Circuits Based on Complex Field Modeling." Scientific World Journal 2014 (2014): 1–14. http://dx.doi.org/10.1155/2014/530942.

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Few researches pay attention to prediction about analog circuits. The few methods lack the correlation with circuit analysis during extracting and calculating features so that FI (fault indicator) calculation often lack rationality, thus affecting prognostic performance. To solve the above problem, this paper proposes a novel prediction method about single components of analog circuits based on complex field modeling. Aiming at the feature that faults of single components hold the largest number in analog circuits, the method starts with circuit structure, analyzes transfer function of circuits, and implements complex field modeling. Then, by an established parameter scanning model related to complex field, it analyzes the relationship between parameter variation and degeneration of single components in the model in order to obtain a more reasonable FI feature set via calculation. According to the obtained FI feature set, it establishes a novel model about degeneration trend of analog circuits’ single components. At last, it uses particle filter (PF) to update parameters for the model and predicts remaining useful performance (RUP) of analog circuits’ single components. Since calculation about the FI feature set is more reasonable, accuracy of prediction is improved to some extent. Finally, the foregoing conclusions are verified by experiments.

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Khalifa, Yaser M. A., Badar Khan, and Faisal Taha. "Multiobjective Optimization Tool for a Free Structure Analog Circuits Design Using Genetic Algorithms and Incorporating Parasitics." Journal of Artificial Evolution and Applications 2008 (September 8, 2008): 1–9. http://dx.doi.org/10.1155/2008/761380.

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This paper presents a novel approach for a free structure analog circuit design using genetic algorithms (GAs). A major problem in a free structure circuit is its sensitivity calculations as a polynomial approximation for the design is not available. A further problem is the effect of parasitic elements on the resulting circuit's performance. In a single design stage, circuits that are produced satisfy a specific frequency response specifications using circuit structures that are unrestricted and with component values that are chosen from a set of preferred values including their parasitic effects. The sensitivity to component variations for the resulting designs is performed using a novel technique and is incorporated in the fitness evaluation function. The extra degrees of freedom resulting form unbounded circuit structures create a huge search space. The application chosen is an RLC ladder filters circuit design.

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FUJII, NOBUO. "Notice the Analog Circuit Technology. Every Circuit Technique Stands on the Analog Technology." Journal of the Institute of Electrical Engineers of Japan 118, no. 7/8 (1998): 411–14. http://dx.doi.org/10.1541/ieejjournal.118.411.

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Babu, N. S. C., and V. C. Prasad. "Radial Basis Function Networks for Analog Circuit Fault Isolation." Journal of Circuits, Systems and Computers 07, no. 06 (December 1997): 643–55. http://dx.doi.org/10.1142/s0218126697000462.

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The application of a radial basis function neural network (RBFN) for analog circuit fault isolation is presented. In this method the RBFN replaces the fault dictionary of analog circuits. The proposed method for analog circuit fault isolation takes the advantage of extremely fast training of RBFN compared to earlier neural network methods. A method is suggested to select centers and widths of RBF units. This selection procedure accounts for the component tolerances. The effectiveness of the RBFN for the fault isolation problem is demonstrated with an illustrative example. RBFN performed well even when the input patterns are drawn directly from the test node voltages of the analog circuit under consideration. A method is suggested to modify the RBF network in the event of occurrence of a new fault. The suggested modifications do not affect the previous training.

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CARD, HOWARD C., DEAN K. McNEILL, CHRISTIAN R. SCHNEIDER, ROLAND S. SCHNEIDER, and BRION K. DOLENKO. "TOLERANCE OF ON-CHIP LEARNING TO VARIOUS CIRCUIT INACCURACIES." Journal of Circuits, Systems and Computers 08, no. 02 (April 1998): 315–27. http://dx.doi.org/10.1142/s0218126698000146.

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An investigation is made of the tolerance of various in-circuit learning algorithms to component imprecision and other circuit limitations in artificial neural networks. In contrast with most previous work, the various circuit limitations are treated separately for their effects on learning. Supervised learning mechanisms including backpropagation and contrastive Hebbian learning, and unsupervised soft competitive learning were found to be sufficiently tolerant of those levels of arithmetic inaccuracy, noise, nonlinearity, weight decay, and statistical variation from fabrication that we have experienced in 1.2 μm analog CMOS circuits employing Gilbert multipliers as the primary computational element. These learning circuits also function properly in the presence of offset errors in analog multipliers and adders, provided that the computed weight updates are constrained by the circuitry to be made only when they exceed certain minimum or threshold values. These results may also be relevant for other analog circuit approaches and for compact (low bit rate) digital implementations, although in this case, the minimum weight increment defined by the bit precision could necessitate stochastic updating.

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Thakral, Bindu, Arti Vaish, and Rama Koteswara Rao Alla. "Design of Squarer Circuit in Sub-threshold Mode." International Journal of Engineering & Technology 7, no. 2.11 (April 3, 2018): 38. http://dx.doi.org/10.14419/ijet.v7i2.11.11004.

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Historically, analog designs have been assumed as a voltage mode based signal processing. However, the necessity of high speed circuits operating at reduced supply voltage has lead to a development of new circuit topology referred as current-mode designs. For low power low voltage designs the applications using translinear principle based circuits has become an area of research and interest. It has wide application in nonlinear signal processing and to build basic active elements. Mode of MOS transistor used in analog circuit realization of is important parameter deciding the performance of the circuit. In this paper, a squarer circuit is proposed based on sub threshold-mode MOS transistors exhibiting the exponential current-voltage characteristic. The simulations have been performed on model files of TSMC 0.18 micrometer technology with the help of ELDO Simulator.

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BŰRMEN, ÁRPÁD, TADEJ TUMA, and IZTOK FAJFAR. "A COMBINED SIMPLEX–TRUST-REGION METHOD FOR ANALOG CIRCUIT OPTIMIZATION." Journal of Circuits, Systems and Computers 17, no. 01 (February 2008): 123–40. http://dx.doi.org/10.1142/s0218126608004125.

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The analog-integrated circuits industry is exerting increasing pressure to shorten the analog circuit design time. This pressure is put primarily on the analog circuit designers that in turn demand automated circuit design tools evermore vigorously. Such tools already exist in the form of circuit optimization software packages but they all suffer a common ailment — slow convergence. Even taking into account the increasing computational power of modern computers the convergence times of such optimization tools can range from a few days to even weeks. Different authors have tried diverse approaches for speeding up the convergence with varying success. In this paper authors propose a combined optimization algorithm that attempts to improve the speed of convergence by exploiting the positive properties of the underlying optimization methods. The proposed algorithm is tested on a number of test cases and the convergence results are discussed.

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Xu, Chen Xi, and Xian Zhi Zhang. "Fault Diagnosis for Nonlinear Analog Circuit Based on Harmonic Decomposition and Coherent Measurement." Applied Mechanics and Materials 40-41 (November 2010): 245–51. http://dx.doi.org/10.4028/www.scientific.net/amm.40-41.245.

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This paper, a fault diagnosis approach for nonlinear dynamic circuit is presented based on harmonic decomposition and coherent measurement. According to the separability of Volterra spectral in weakly nonlinear circuit under AM stimulation, the Volterra response can decompose into linear sub-circuits based on ARMA harmonic decomposition firstly. In linear sub-circuits, the mapping relationship between the fault characteristics and fault states will become more clearly. Then, the dynamic linear sub-circuit is transformed into static circuit by coherent measurement, and the diagnosis equation is created with circuit node-equation. The fault diagnosis can be implemented by calculating the nodes’ fault-current. Finally, with an example to illuminate the proposed is available.

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CARD, HOWARD. "ANALOG CIRCUITS FOR RELAXATION NETWORKS." International Journal of Neural Systems 04, no. 04 (December 1993): 359–79. http://dx.doi.org/10.1142/s0129065793000304.

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Selected examples are presented of recent advances, primarily from the U.S. and Canada, in analog circuits for relaxation networks. Relaxation networks having feedback connections exhibit potentially greater computational power per neuron than feedforward networks. They are also more poorly understood especially with respect to learning algorithms. Examples are described of analog circuits for (i) supervised learning in deterministic Boltzmann machines, (ii) unsupervised competitive learning and feature maps and (iii) networks with resistive grids for vision and audition tasks. We also discuss recent progress on in-circuit learning and synaptic weight storage mechanisms.

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Prajapati, Pankaj P., and Mihir V. Shah. "Automatic Circuit Design of CMOS Miller OTA Using Cuckoo Search Algorithm." International Journal of Applied Metaheuristic Computing 11, no. 1 (January 2020): 36–44. http://dx.doi.org/10.4018/ijamc.2020010103.

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The circuit design of the CMOS based analog part of a mixed-signal integrated circuit (IC) needs a large fraction of the overall design cycle time. The automatic design of an analog circuit is inevitable, seeing recently development of System-on-Chip (SOC) design. This brings about the need to develop computer aided design (CAD) tools for automatic design of CMOS based analog circuits. In this article, a Cuckoo Search (CS) algorithm is presented for automatic design of a CMOS Miller Operational Transconductance Amplifier (OTA). The source code of the CS algorithm is developed using the C language. The Ngspice circuit simulator has been used as a fitness function creator and evaluator. A script file is written to provide an interface between the CS algorithm and the Ngspice simulator. BSIM3v3 MOSFET models with 0.18 µm and 0.35 µm CMOS technology have been used to simulate this circuit. The simulation results of this work are presented and compared with previous works reported in the literature. The experimental simulation results obtained by the CS algorithm satisfy all desired specifications for this circuit.

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Pota, Hemanshu R. "Circuit Theory and Analog Electronics — Computer Aided Teaching." International Journal of Electrical Engineering & Education 34, no. 2 (April 1997): 141–60. http://dx.doi.org/10.1177/002072099703400205.

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A computer aided approach to teaching undergraduate courses in circuit theory and electronics is discussed. It is shown that symbolic manipulation packages like MAPLE give an additional insight into the analysis — complementing the analysis using a numerical simulation package like SPICE — enabling the students to understand complicated circuits.

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Journal articles on the topic 'Analog circuit'

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