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1
Fayed, Ayman Adel. "Adaptive techniques for analog and mixed signal integrated circuits." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1097519730.
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Thesis (Ph. D.)--Ohio State University, 2004.Title from first page of PDF file. Document formatted into pages; contains xix, 232 p.; also includes graphics (some col.). Includes bibliographical references (p. 222-230).
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Wang, Zhenhua. "Current-mode analog integrated circuits and linearization techniques in CMOS technology /." [S.l.] : [s.n.], 1990. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=9188.
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Layton, Kent D. "Low-voltage analog CMOS architectures and design methods /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd2141.pdf.
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Kasturi, Prasan. "A CAD tool for analog and mixed signal CMOS circuits /." View online ; access limited to URI, 2006. http://0-digitalcommons.uri.edu.helin.uri.edu/dissertations/AAI3248232.
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Massier, Tobias [Verfasser]. "On the Structural Analysis of CMOS and Bipolar Analog Integrated Circuits / Tobias Massier." Aachen : Shaker, 2010. http://d-nb.info/1081885688/34.
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Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.
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Carr, Richard D. "Analog preprocessing in a SNS 2 [mu] low-noise CMOS folding ADC." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1994. http://handle.dtic.mil/100.2/ADA293356.
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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 1994."December 1994." Thesis advisor(s): Phillip E. Pace, Douglas J. Fouts. Bibliography: p. 103. Also available online.
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Kilic, Yavuz. "Testing techniques and fault simulation for analogue CMOS integrated circuits." Thesis, University of Southampton, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.390727.
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Killens, Jacob. "Utilizing standard CMOS process floating gate devices for analog design." Master's thesis, Mississippi State : Mississippi State University, 2001. http://library.msstate.edu/etd/show.asp?etd=etd-04092001-110957.
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Tavakoli, Hosseinabadi Ahmad Reza. "Fully integrated cmos phase shifter/vco for mimo/ism application." [College Station, Tex. : Texas A&M University, 2007. http://hdl.handle.net/1969.1/ETD-TAMU-2502.
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Hooper, Mark S. "Submicron CMOS programmable analog floating-gate circuits and arrays using DC-DC converters." Diss., Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-12032004-155022/unrestricted/Hooper%5FMark%5FS%5F200505%5Fphd.pdf.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.Kucic, Matthew, Committee Member ; Hasler, Paul, Committee Chair ; Heck, Bonnie, Committee Member ; Cressler, John, Committee Member ; Anderson, David, Committee Member. Vita. Includes bibliographical references.
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Loikkanen, M. (Mikko). "Design and compensation of high performance class AB amplifiers." Doctoral thesis, University of Oulu, 2010. http://urn.fi/urn:isbn:9789514261770.
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Abstract
Class A and class AB operational amplifiers are an essential part of a mixed- signal chip, where they are used as active filter sub-blocks, compensators, reference current generators and voltage buffers, to name just a few of many applications. For analog circuits such as operational amplifiers a mixed-signal chip is a very unfriendly operating environment, where the power supply is often corrupted by high current switching circuits. In addition, power supply voltages for analog blocks are shrinking, because of the deployment of new battery technologies and fine line length integrated circuit processes, which can reduce the amplifier dynamic range a problem requiring supply insensitive low voltage compatible amplifier topologies and other analog blocks.
The aims of this thesis were to further develop the low voltage compatible class AB amplifier topologies published earlier by other authors, to improve their bandwidth efficiency by means of re-examining two- and three-stage amplifier compensation techniques and to find solutions for enhancing the high frequency power supply noise rejection performance of class A and class AB amplifiers without degrading their signal path stability.
The class AB amplifier cores presented here improve the amplifier’s power supply noise insensitivity at high frequencies and increase bandwidth efficiency when compared to the commonly used two-stage Miller compensated amplifier, enabling the construction of better buffers and more power-efficient and reliable low voltage mixed signal chips.
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Zhu, Yongdong. "Parasitic-aware design and layout for RF CMOS analogue integrated circuits." Thesis, University of Essex, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.442535.
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Michal, Vratislav. "Design of CMOS analog integrated circuits as readout electronics for High-TC superconductor and semiconductor terahertz bolometric sensors." Phd thesis, Université Pierre et Marie Curie - Paris VI, 2006. http://tel.archives-ouvertes.fr/tel-00417838.
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Cette thèse porte sur la conception d'un circuit intégré CMOS pour l'électronique de lecture de capteurs bolométriques à base de semiconducteurs ou supraconducteurs haute-température. Dans ce manuscrit, une chaîne de traitement du signal est étudiée. Elle est composée d'un amplificateur différentiel à gain fixé pour des températures de 40 à 400K, ainsi que d'un filtre de fréquence passe-bas actif à haute dynamique. Une architecture optimale d'amplificateur est définie sans contre-réaction, permettant d'atteindre une large bande passante (17MHz pour un gain de 40dB), une consommation réduite (Iq = 2mA) et une haute impédance d'entrée. Afin de fixer le gain avec précision dans la structure CMOS, deux méthodes différentes sont présentées et vérifiées sur un circuit intégré. Par la suite, le comportement des filtres dans la bande d'atténuation est étudié afin d'augmenter la fréquence de coupure maximale. Deux structures avec une faible influence des éléments actifs « réels » sont conçues: le filtre Sallen-Key amélioré et la structure basée sur un convoyeur du courant CCII-. Enfin, nous présentons un CCII- intégré en CMOS ayant une très faible impédance de sortie.
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Oliveira, Vlademir de Jesus Silva [UNESP]. "Desenvolvimento de um sintetizador de freqüência de baixo custo em tecnologia CMOS." Universidade Estadual Paulista (UNESP), 2009. http://hdl.handle.net/11449/100280.
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Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS...
In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture
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Xiong, Zhijie. "Radio Frequency Low Noise and High Q Integrated Filters in Digital CMOS Processes." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5043.
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Radio Frequency Low Noise and High Q
Integrated Filters in Digital CMOS Processes
Zhijie Xiong
149 pages
Directed by Dr. Phillip E. Allen
Presented in this work is a novel design technique for CMOS integration of RF high Q integrated filters using positive feedback and current mode approach. Two circuits are designed in this work: a 100MHz low-noise and high Q bandpass filter suited for an FM radio front-end, and a 2.4GHz low-noise and high-Q bandpass filter suited for a Bluetooth front-end. Current-mode approach and positive feedback design techniques are successfully used in the design of both circuits. Both circuits are fabricated through a 0.18um CMOS process provided by National Semiconductor Corp.
The 100MHz circuit achieves 3.15uV RF sensitivity with 26dB SNR, and the total current consumption is 12mA. The center frequency of the filter is tunable from 80MHz to 110MHz, and the Q value is tunable from 0.5 to 28.9. 1 dB compression point is measured as -34.0dBm, combined with noise measurement results, a dynamic range of 54.1 dB results. Silicon area of the core circuit is 0.4 square millimeters.
The center frequency of the 2.4GHz circuit is tunable from 2.4GHz to 2.5GHz, and the Q value is tunable from 20 to 120. The 1 dB compression dynamic range of the circuit is 50dB. Integrated spiral inductors are developed for this design. Patterned ground shields are laid out to reduce inductor loss through substrate, especially eddy current loss when the circuit is fabricated on epi wafers. Accumulation mode MOS varactors are designed to tune the frequency response. Silicon area of the core circuit is 1 square millimeter.
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Karagounis, Michael Athanassios [Verfasser]. "Analog Integrated CMOS Circuits for the Readout and Powering of Highly Segmented Detectors in Particle Physics Applications / Michael Athanassios Karagounis." Hagen : Fernuniversität Hagen, 2010. http://d-nb.info/1009326414/34.
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Larsen, Frode. "Bipolar device characterization and design in CMOS technologies for the design of high-performance low-cost BiCMOS analog integrated circuits /." The Ohio State University, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487857546387163.
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Brotman, Susan Rose. "The Evaluation of Device Model Dependence in the Design of a High-Frequency, Analog, CMOS Transconductance-C Filter." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4701.
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It is important to have the ability to predict the effects of device model variation when designing integrated transconductance-C type active filters. Applying these filters to integrated circuit design has become increasingly popular due to its ease of implementation in monolithic form. With the introduction of fully automated design tools, predictable behavior of high-level variables becomes still more important. The purpose of this study is to evaluate the process parameter spread of analog device models to determine the effect on the design parameters of an active filter. This information's significant contribution directly effects the feasibility and realization of automating analog filter design. In order to explore the dependence of filter performance on the device v model parameter spread, a fifth-order inverse Chebyshev filter is designed and simulated using a two year history of process models. It has not been observed that higher order filters have been successfully designed using fully automated design tools. This filter was realized using automated filter design currently being developed in parallel with this study. A single-ended input to single-ended output transconductance amplifier is chosen for this design for its simplicity and small size. Differential performance is easily adapted with exact duplication which is demonstrated in the measurements of the fabricated filter. Simulation of the design is performed using MOSIS SCNA device parameters. Filter performance data such as cutoff frequency, stopband attenuation, and phase response is collected. Experimental results from the fabricated device are compared to simulation and the original prototype. 2 It is shown that the most predicable effect on the design parameters of a filter is caused by the parasitic output conductance parameter g0. This process dependent variable causes both a deviation in the cutoff frequency, and a decrease in the filter quality factor. In addition, it is also shown that the practice employed to predistort for absorption of parasitic capacitors in a MOS technology is a very effective tool in the reduction of capacitive process dependence.n software
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Song, Tae Joong. "A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/34760.
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This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.
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Oliveira, Vlademir de Jesus Silva. "Desenvolvimento de um sintetizador de freqüência de baixo custo em tecnologia CMOS /." Ilha Solteira : [s.n.], 2009. http://hdl.handle.net/11449/100280.
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Orientador: Nobuo OkiBanca: Suely Cunha Amaro Mantovani
Banca: Jozué Vieira Filho
Banca: Marcelo Arturo Jara Perez
Banca: Paulo Augusto Dal fabbro
Resumo: Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS... (Resumo completo, clicar acesso eletrônico abaixo)
Abstract: In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture
Doutor
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Douglas, Dale Scott. "Flicker noise in cmos lc oscillators." Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26550.
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Sources of flicker noise generation in the cross-coupled negative resistance oscillator (NMOS, PMOS, and CMOS) are explored. Also, prior and current work in the area of phase noise modeling is reviewed, including the work of Leeson, Hajimiri, Hegazi, and others, seeking the mechanisms by which flicker noise is upconverted.
A Figure of Merit (FOM) methodology suitable to the 1/f3 phase noise region is also developed, which allows a new quantity, FOM1, to be defined. FOM1 is proportional to flicker noise upconverted, thus allowing the effectiveness of flicker noise upconversion suppression techniques to be evaluated, despite possibly changing bias points or tank Q, which would change phase noise and FOM in the 1/f2 region.
The work of Hajimiri is extended with a simple Amplitude ISF DC component estimator for the special case of LC CMOS oscillators. A method of adaptive control of an oscillator core is presented, as well, comprised of a CMOS oscillator with a digitally adjustable N and P width, and a circuit (which is essentially a tracking ADC) which repeatedly adjusts the relative N to P width dependent on the estimate to maintain the condition of minimum flicker noise upconversion. A fixed calibration constant is sufficient to allow convergence to within 0.7dB of optimal FOM1 for all cases of N width, for a varactorless oscillator test cell.
Finally, a circuit is proposed which would allow the flicker noise reduction technique of cycling to accumulation to be applied to continuous time oscillators, but is not rigorously vetted.
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Sumesaglam, Taner. "Automatic tuning of continuous-time filters." Diss., Texas A&M University, 2004. http://hdl.handle.net/1969.1/1055.
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Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.
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Massier, Tobias [Verfasser], Ulf [Akademischer Betreuer] Schlichtmann, Ulf [Gutachter] Schlichtmann, and Doris [Gutachter] Schmitt-Landsiedel. "On the Structural Analysis of CMOS and Bipolar Analog Integrated Circuits / Tobias Massier ; Gutachter: Ulf Schlichtmann, Doris Schmitt-Landsiedel ; Betreuer: Ulf Schlichtmann." München : Universitätsbibliothek der TU München, 2010. http://d-nb.info/1194547699/34.
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Oliveira, Vlademir de Jesus Silva [UNESP]. "Sintetizador analógico de sinais ortogonais: projeto e construção usando tecnologia CMOS." Universidade Estadual Paulista (UNESP), 2004. http://hdl.handle.net/11449/90796.
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Nesse trabalho, propõe-se o projeto e implementação de um sintetizador de sinais ortogonais utilizando técnicas de circuito integrado e processo CMOS. O circuito do sintetizador baseia-se em um modelo matemático que utiliza multiplicadores e integradores analógicos, para geração de bases de funções ortogonais, tais como os polinômios de Legendre, as funções de base coseno e seno, a smoothed-cosine basis e os polinômios de Hermite. Funções ortogonais são bastante empregadas em processamento de sinais, e a implementação deste método matemático é capaz de gerar vários tipos de funções em um mesmo circuito integrado. O projeto proposto utiliza blocos analógicos funcionais para implementar o sintetizador. Os blocos que compõem o sintetizador foram projetados utilizando circuitos diferenciais, processamento em modo de corrente e técnicas de low-voltage. Algumas topologias utilizadas estão descritas na literatura, sendo que algumas foram adaptadas e mesmo modificadas, como no caso do multiplicador de corrente. Outras tiveram que ser propostas. As simulações e os resultados experimentais mostraram que o sintetizador é capaz de gerar funções ortogonais com amplitude e distorções satisfatórias. O sintetizador pode ser alimentado em 3V, tal qual foi projetado, tem faixa de entrada de ±20 μA e apresenta DHT (distorção harmônica total) inferior a 4% no quinto e último estágio em cascata.
In this work, a design and implementation of a synthesizer of orthogonal signals using CMOS technology and design technique for integrated circuits is proposed. The synthesizer circuit used analog multipliers and integrators for produce orthogonal functions such as Legendre polynomials, cosine and sine basis of functions, smoothed-cosine basis and Hermite polynomials. Orthogonal functions can be employed in signal processing and the implementation proposed can generate several kinds of functions in the same integrated circuit. In the synthesizer design building blocks was employed. The synthesizer’s blocks were design using differential circuits, low-voltage and current-mode techniques. Some topologies from papers were adapted or modified, as in the case of the current multiplier. Other topologies had to be proposed. The simulation and experimental results have shown that the synthesizer is able to produce orthogonal functions with satisfactory quality in distortions and amplitude. The synthesizer has a 3V supply voltage, a input current range of ±20 μA and it presents less than 4% of THD (Total Harmonic Distortion) in the last output in cascade.
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Qureshi, Muhammad Shakeel. "Integrated front-end analog circuits for mems sensors in ultrasound imaging and optical grating based microphone." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29613.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Hasler, Paul; Committee Co-Chair: Degertekin, Levent; Committee Member: Anderson, David; Committee Member: Ayazi, Farrokh; Committee Member: Brand, Oliver; Committee Member: Hesketh, Peter. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Sebastian, Johny. "A Temperature stabilised CMOS VCO based on amplitude control." Diss., University of Pretoria, 2013. http://hdl.handle.net/2263/33447.
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Speed, power and reliability of analogue integrated circuits (IC) exhibit temperature dependency through the modulation of one or several of the following variables: band gap energy of the semiconductor, mobility, carrier diffusion, current density, threshold voltage, interconnect resistance, and variability in passive components. Some of the adverse effects of temperature variations are observed in current and voltage reference circuits, and frequency drift in oscillators. Thermal instability of a voltage-controlled oscillator (VCO) is a critical design factor for radio frequency ICs, such as transceiver circuits in communication networks, data link protocols, medical wireless sensor networks and microelectromechanical resonators. For example, frequency drift in a transceiver system results in severe inter-symbol interference in a digital communications system. Minimum transconductance required to sustain oscillation is specified by Barkhausen’s stability criterion. However it is common practice to design oscillators with much more transconductance enabling self-startup. As temperature is increased, several of the variables mentioned induce additional transconductance to the oscillator. This in turn translates to a negative frequency drift.
Conventional approaches in temperature compensation involve temperature-insensitive biasing proportional-to-absolute temperature, modifying the control voltage terminal of the VCO using an appropriately generated voltage. Improved frequency stability is reported when compensation voltage closely follows the frequency drift profile of the VCO. However, several published articles link the close association between oscillation amplitude and oscillation frequency. To the knowledge of this author, few published journal articles have focused on amplitude control techniques to reduce frequency drift. This dissertation focuses on reducing the frequency drift resulting from temperature variations based on amplitude control. A corresponding hypothesis is formulated, where the research outcome proposes improved frequency stability in response to temperature variations.
In order to validate this principle, a temperature compensated VCO is designed in schematic and in layout, verified using a simulation program with integrated circuit emphasis tool using the corresponding process design kit provided by the foundry, and prototyped using standard complementary metal oxide semiconductor technology. Periodic steady state (PSS) analysis is performed using the open loop VCO with temperature as the parametric variable in five equal intervals from 0 – 125 °C. A consistent negative frequency shift is observed in every temperature interval (≈ 11 MHz), with an overall frequency drift of 57 MHz. However similar PSS analysis performed using a VCO in the temperature stabilised loop demonstrates a reduced negative frequency drift of 3.8 MHz in the first temperature interval. During the remaining temperature intervals the closed loop action of the amplitude control loop overcompensates for the negative frequency drift, resulting in an overall frequency spread of 4.8 MHz. The negative frequency drift in the first temperature interval of 0 to 25 °C is due to the fact that amplitude control is not fully effective, as the oscillation amplitude is still building up. Using the temperature stabilised loop, the overall frequency stability has improved to 16 parts per million (ppm)/°C from an uncompensated value of 189 ppm/°C.
The results obtained are critically evaluated and conclusions are drawn. Temperature stabilised VCOs are applicable in applications or technologies such as high speed-universal serial bus, serial advanced technology attachment where frequency stability requirements are less stringent. The implications of this study for the existing body of knowledge are that better temperature compensation can be obtained if any of the conventional compensation schemes is preceded by amplitude control.Dissertation (MEng)--University of Pretoria, 2013.
Electrical, Electronic and Computer Engineering
unrestricted
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Amaral, Wellington Avelino do. "Referencia de tensão CMOS com correção de curvatura." [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260213.
Full textAbstract:
Orientador: Jose Antonio Siqueira DiasTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: Este trabalho teve como finalidade o projeto e prototipagem de uma referência de tensão CMOS (Complementary Metal Oxide Semiconductor) baseada na tensão de limiar do transistor MOS (Metal Oxide Semiconductor). A inovação apresentada neste trabalho é a utilização de uma arquitetura original e com alto desempenho. Nas medidas realizadas em laboratório o circuito apresentou uma variação de 11ppm/0C. Desempenho este comparável às referências do tipo bandgap. Também foi projetado um sensor de temperatura com coeficiente térmico igual a 1mV/0C. Portanto, dois circuitos foram enviados para fabricação (o circuito ceinv35 e o circuito ceinv66). O circuito ceinv35, utilizando suas estruturas de trimmer, pode operar como referência de tensão ou como sensor de temperatura. O circuito ceinv66 foi a principal configuração estudada. Ele utiliza um circuito extrator de Vth, um circuito de start-up e um amplificador operacional. O circuito extrator de Vth utiliza uma topologia inovadora. Nos dois circuitos (ceinv35 e ceinv66) foram utilizadas estruturas de trimmer para possibilitar ajustes externos. No capítulo de introdução é apresentado um "overview" dos circuitos utilizados como referência de tensão. São analisadas algumas referências do tipo bandgap e algumas técnicas usualmente utilizada para o projeto de referências de tensão CMOS. No capítulo 2 são analisados o princípio de funcionamento e todo o equacionamento do circuito proposto. No capítulo 3 são apresentados os resultados de simulação. O circuito ceinv35 apresentou um coeficiente térmico igual a 1mV/0C, funcionando ele como sensor de temperatura. Já operando como referência de tensão, a variação apresentada foi de 4:06ppm/0C. O circuito ceinv66 apresentou uma variação de apenas 3:14ppm/0C. O capítulo 4 cobre o projeto dos layouts dos circuitos. Eles foram projetados utilizando a tecnologia da AMS (Austria Microsystems) de comprimento mínimo de canal igual a 0:35_m. No capítulo 5 são apresentados os resultados da extração de parasitas dos circuitos. Após esta análise foi verificada a necessidade de reajuste dos circuitos, utilizando as estruturas de trimmer. No capítulo 6 são fornecidos os resultados experimentais dos dois circuitos. No capítulo 7 é apresentada uma alternativa para o projeto da referência de tensão sem a necessidade da utilização do circuito de start-up. Neste mesmo capítulo também é apresentada uma proposta de metodologia para projeto dos trimmers do circuito. No capítulo 8 são discutidas as inovações propostas neste trabalho e algumas conclusões sobre o projeto apresentado.
Abstract: The objective of this work is to design and prototype a CMOS voltage reference based on the threshold voltage of the MOS transistor. The innovation presented in this work is the use of an original architecture with high performance. In the laboratory measurements the circuit presented 11ppm/0C of variation. This performance is comparable to the bandgap references. A temperature sensor was also designed and presented a temperature coefficient of 1mV/0C. Therefore, two circuits were prototyped (the ceinv35 circuit and the ceinv66 circuit). The circuit ceinv35, using the trimmer structures, can operate as a voltage reference or a temperature sensor. The circuit ceinv66 was the main topology studied. It uses a Vth extractor circuit, a start-up circuit and an operational amplifier. The Vth extractor circuit uses an original topology. In both circuits (ceinv35 and ceinv66) were used trimmer structures to make possible off-chip adjusts. In the introduction chapter is presented an overview of the circuits used as voltage references. Some bandgap references and some techniques used to design CMOS voltage references are analyzed. In chapter 2 are shown the operation principles and the equations extracted of the proposed circuit. In chapter 3 are shown the simulation results. The circuit ceinv35 presented a temperature coefficient of 1mV/0C, working as a temperature sensor. On the other side, working as a voltage reference, the variation presented was 4:06ppm/0C. The circuit ceinv66 presented a variation of just 3:14ppm/0C. The chapter 4 covers the layout design of the circuits. The AMS (Austria Microsystems) technology with a minimum channel length of 0:35_m was used. In chapter 5 are presented the parasitic extraction simulations. After this analyses new adjusts were made in the circuits. The trimmers structures were used for this adjusts. In chapter 6 are provided the experimental results of both circuits. In chapter 7 is presented an alternative for the voltage reference design without using a start-up circuit. In this chapter is also presented a methodology for the trimmers design. In chapter 8 are discussed the proposed innovations and some conclusions about the design presented.
Universidade Estadual de Campi
Eletrônica, Microeletrônica e Optoeletrônica
Doutor em Engenharia Elétrica
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Bonnard, Rémi. "Burst CMOS image sensor with on-chip analog to digital conversion." Thesis, Strasbourg, 2016. http://www.theses.fr/2016STRAD006/document.
Full textAbstract:
Ce travail vise à étudier l’apport des technologies d’intégration 3D à l’imagerie CMOS ultra-rapide. La gamme de vitesse d’acquisition considérée ici est du million au milliard d’images par seconde. Cependant au-delà d’une dizaine de milliers d’images par seconde, les architectures classiques de capteur d’images sont limitées par la bande passante des buffers de sortie. Pour atteindre des fréquences supérieures, une architecture d’imageur burst est utilisée où une séquence d’une centaine d’images est acquise et stockée dans le capteur. Les technologies d’intégration 3D ont connu un engouement depuis une dizaine d’années et sont considérées comme une solution complémentaire aux travaux menés sur les dispositifs (transistors, composants passifs) pour améliorer les performances des circuits intégrés. Notre choix s’est porté sur une technologie où les circuits intégrés sont directement empilés avant la mise en boitier (3D-SIC). La densité d’interconnexions entre les différents circuits est suffisante pour permettre l’implémentation d’interconnexions au niveau du pixel. L’intégration 3D offre d’intéressants avantages à l’imagerie intégrée car elle permet de déporter l’électronique de lecture sous le pixel. Elle permet ainsi de maximiser le facteur de remplissage du pixel tout en offrant une large place aux circuits de conditionnement du signal. Dans le cas de l’imagerie burst, cette technologie permet de consacrer une plus grande surface aux mémoires dédiées au stockage de la séquence d’image et ce au plus proche des pixels. Elle permet aussi de réaliser sur la puce la conversion analogique numérique des images acquisesThis work aims to study the inflows of the 3D integration technology to ultra-high speed CMOS imaging. The acquisition speed range considered here is between one million to one billion images per second. However above ten thousand images per second, classical image sensor architectures are limited by the data bandwidth of the output buffers. To reach higher acquisition frequencies, a burst architecture is used where a set of about one hundred images are acquired and stored on-chip. 3D integration technologies become popular more than ten years ago and are considered as a complementary solution to the technological improvements of the devices. We have chosen a technology where integrated circuits are stacked on the top of each other (3D-SIC). The interconnection density between the circuits is high enough to enable interconnections at the pixel level. The 3D integration offers some significant advantages because it allows deporting the readout electronic below the pixel. It thus increases the fill factor of the pixel while offering a wide area to the signal processing circuit. For burst imaging, this technology provides more room to the memory dedicated to the image storage while staying close to the pixel. It also allows implementing analog to digital converter on-chip
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Chong, Joseph. "CMOS Receiver Design for Optical Communications over the Data-Rate of 20 Gb/s." Diss., Virginia Tech, 2018. http://hdl.handle.net/10919/83608.
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Circuits to extend operation data-rate of a optical receiver is investigated in the dissertation. A new input-stage topology for a transimpedance amplifier (TIA) is designed to achieve 50% higher data-rate is presented, and a new architecture for clock recovery is proposed for 50% higher clock rate. The TIA is based on a gm-boosted common-gate amplifier. The input-resistance is reduced by modifying a transistor at input stage to be diode-connected, and therefore lowers R-C time constant at the input and yielding higher input pole frequency. It also allows removal of input inductor, which reduces design complexity. The proposed circuit was designed and fabricated in 32 nm CMOS SOI technology. Compared to TIAs which mostly operates at 50 GHz bandwidth or lower, the presented TIA stage achieves bandwidth of 74 GHz and gain of 37 dBohms while dissipating 16.5 mW under 1.5V supply voltage. For the clock recovery circuit, a phase-locked loop is designed consisting of a frequency doubling mechanism, a mixer-based phase detector and a 40 GHz voltage-controlled oscillator. The proposed frequency doubling mechanism is an all-analog architecture instead of the conventional digital XOR gate approach. This approach realizes clock-rate of 40 GHz, which is at least 50% higher than other circuits with mixer-based phase detector. Implemented with 0.13-μm CMOS technology, the clock recovery circuit presents peak-to-peak clock jitter of 2.38 ps while consuming 112 mW from a 1.8 V supply.Ph. D.
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Lasanen, K. (Kimmo). "Integrated analogue CMOS circuits and structures for heart rate detectors and other low-voltage, low-power applications." Doctoral thesis, Oulun yliopisto, 2011. http://urn.fi/urn:isbn:9789514294556.
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Abstract This thesis describes the development of low-voltage, low-power circuit blocks and structures for portable, battery-operated applications such as heart rate detectors, pacemakers and hearing-aid devices. In this work, the definition for low supply voltage operation is a voltage equal to or less than the minimum supply voltage needed to operate an analogue switch, i.e. VDD(min) ≤ 2VT + Vov, which enables the use of a single cell battery whose polar voltage is 1 – 1.5 V. The targeted power consumption is in a range of microwatts. The design restrictions for analogue circuit design caused by the low supply voltage requirement of the latest and future CMOS process technologies were considered and a few circuit blocks, namely two operational amplifiers, a Gm–C filter and a bandgap voltage reference circuit, were first designed to investigate their feasibility for the above-mentioned low-voltage and low-power environment. Two operational amplifiers with the same target specifications were designed with two different types of input stages, i.e. a floating-gate and a bulk-driven input stage, in order to compare their properties. Based on the experiences collected from the designed circuit blocks, an analogue CMOS preprocessing stage for a heart rate detector and a self-calibrating RC oscillator for clock and resistive/capacitive sensor applications were designed, manufactured and tested. The analogue preprocessing stage for a heart rate detector includes a continuous-time offset-compensated preamplifier with a gain of 40 dB, an 8th-order switched-opamp switched-capacitor bandpass filter, a 32-kHz crystal oscillator and a bias circuit, and it achieves the required performance with a supply voltage range of 1.0 – 1.8 V and a current consumption of 3 μA. The self-calibrating RC oscillator operates with supply voltages of 1.2 – 3.0 V and achieves a tunable frequency range of 0.2 – 150 MHz with a total accuracy of ±1% within a supply voltage range of 1.2 – 1.5 V, a temperature range from -20 to 60 °C and a current consumption of less than 70 μA @ 5 MHz with external high precision resistor and capacitor. The measurement results prove that the developed low-voltage low-power analogue circuit structures can achieve the required performance and therefore be successfully implemented with modern CMOS process technologies with limited supply voltagesTiivistelmä Tämä väitöskirja käsittelee matalan käyttöjännitteen pienitehoisten piirirakenteiden kehittämistä kannettaviin, paristokäyttöisiin sovelluksiin kuten esimerkiksi sykemittareihin, sydämen tahdistimiin ja kuulolaitteisiin. Matalalla käyttöjännitteellä tarkoitetaan jännitettä, joka on pienempi tai yhtäsuuri kuin analogisen kytkimen tarvitsema pienin mahdollinen käyttöjännite, VDD(min) ≤ 2VT + Vov, joka mahdollistaa piirin toiminnan yhdellä paristolla, jonka napajännite on 1 – 1,5 V. Tavoiteltu tehonkulutus on mikrowattiluokkaa. Piirirakenteiden suunnittelussa otettiin huomioon viimeisimpien ja lähitulevaisuuden CMOS-valmistusteknologioiden aiheuttamat matalan käyttöjännitteen erityisvaatimukset ja niiden pohjalta kehitettiin aluksi kaksi erilaista operaatiovahvistinta, GmC-suodatin, ja bandgap-jännitereferenssi. Operaatiovahvistimet toteutettiin samoin tavoitevaatimuksin kahdella eri tekniikalla käyttäen toisen vahvistimen tuloasteessa ns. kelluvahilaisia tulotransistoreita ja toisen tuloasteessa ns. allasohjattuja tulotransistoreita. Kehitetyistä rakenteista saatujen kokemusten pohjalta suunniteltiin, valmistettiin ja testattiin kaksi erilaista CMOS-teknologialla toteutettua mikropiiriä, jotka olivat analoginen esikäsittelypiiri sydämen sykkeen mittaukseen ja itsekalibroiva RC-oskillaattori resistiivisiin/kapasitiivisiin sensorisovelluksiin. Sydämen sykkeen esikäsittelypiiri sisältää jatkuva-aikaisen, offset-kompensoidun esivahvistimen, jonka vahvistus on 40 dB, kytketyistä kapasitansseista ja kytketyistä operaatiovahvistimista koostuvan kahdeksannen asteen kaistanpäästösuodattimen, 32 kHz kideoskillaattorin ja bias-piirin. Esikäsittelypiiri saavuttaa vaadittavan suorituskyvyn 1,0 – 1,8 V käyttöjännitteellä ja 3 μA virrankulutuksella. Itsekalibroivan RC-oskillaattorin käyttöjännitealue puolestaan on 1,2 – 3,0 V ja käyttökelpoinen taajuusalue 0,2 – 150 MHz. Ulkoista tarkkuusvastusta ja kondensaattoria käytettäessä oskillaattori saavuttaa ±1 % tarkkuuden 1,2 – 1,5 V käyttöjännitteillä ja -20 – 60 °C lämpötila-alueella virrankulutuksen jäädessä alle 70 μA @ 5 MHz. Mittaustulokset osoittavat, että kehitetyt matalan käyttöjännitteen pienitehoiset analogiset rakenteet saavuttavat vaadittavan suorituskyvyn ja voidaan näin ollen menestyksekkäästi valmistaa moderneilla matalan käyttöjännitteen CMOS-teknologioilla
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Oliveira, Vlademir de Jesus Silva. "Sintetizador analógico de sinais ortogonais : projeto e construção usando tecnologia CMOS /." Ilha Solteira : [s.n.], 2004. http://hdl.handle.net/11449/90796.
Full textAbstract:
Orientador: Nobuo OkiBanca: Saulo Finco
Banca: Cláudio Kitano
Resumo: Nesse trabalho, propõe-se o projeto e implementação de um sintetizador de sinais ortogonais utilizando técnicas de circuito integrado e processo CMOS. O circuito do sintetizador baseia-se em um modelo matemático que utiliza multiplicadores e integradores analógicos, para geração de bases de funções ortogonais, tais como os polinômios de Legendre, as funções de base coseno e seno, a smoothed-cosine basis e os polinômios de Hermite. Funções ortogonais são bastante empregadas em processamento de sinais, e a implementação deste método matemático é capaz de gerar vários tipos de funções em um mesmo circuito integrado. O projeto proposto utiliza blocos analógicos funcionais para implementar o sintetizador. Os blocos que compõem o sintetizador foram projetados utilizando circuitos diferenciais, processamento em modo de corrente e técnicas de low-voltage. Algumas topologias utilizadas estão descritas na literatura, sendo que algumas foram adaptadas e mesmo modificadas, como no caso do multiplicador de corrente. Outras tiveram que ser propostas. As simulações e os resultados experimentais mostraram que o sintetizador é capaz de gerar funções ortogonais com amplitude e distorções satisfatórias. O sintetizador pode ser alimentado em 3V, tal qual foi projetado, tem faixa de entrada de ±20 μA e apresenta DHT (distorção harmônica total) inferior a 4% no quinto e último estágio em cascata.
Abstract: In this work, a design and implementation of a synthesizer of orthogonal signals using CMOS technology and design technique for integrated circuits is proposed. The synthesizer circuit used analog multipliers and integrators for produce orthogonal functions such as Legendre polynomials, cosine and sine basis of functions, smoothed-cosine basis and Hermite polynomials. Orthogonal functions can be employed in signal processing and the implementation proposed can generate several kinds of functions in the same integrated circuit. In the synthesizer design building blocks was employed. The synthesizer's blocks were design using differential circuits, low-voltage and current-mode techniques. Some topologies from papers were adapted or modified, as in the case of the current multiplier. Other topologies had to be proposed. The simulation and experimental results have shown that the synthesizer is able to produce orthogonal functions with satisfactory quality in distortions and amplitude. The synthesizer has a 3V supply voltage, a input current range of ±20 μA and it presents less than 4% of THD (Total Harmonic Distortion) in the last output in cascade.
Mestre
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Levski, Deyan. "Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors." Thesis, University of Oxford, 2018. http://ora.ox.ac.uk/objects/uuid:31b9426f-8a7c-4c86-9471-32431f33ebe7.
Full textAbstract:
This thesis presents a study on solutions to high-speed analog-to-digital conversion in CMOS image sensors using time-interpolation methods. Data conversion is one of the few remaining speed bottlenecks in conventional 2D imagers. At the same time, as pixel dark current continues to improve, the resolution requirements on imaging data converters impose very high system-level design challenges. The focus of the presented investigations here is to shed light on methods in Time-to-Digital Converter interpolation of single-slope ADCs. By using high-factor time-interpolation, the resolution of single-slope converters can be increased without sacrificing conversion time or power. This work emphasizes on solutions for improvement of multiphase clock interpolation schemes, following an all-digital design paradigm. Presented is a digital calibration scheme which allows a complete elimination of analog clock generation blocks, such as PLL or DLL in Flash TDC-interpolated single-slope converters. To match the multiphase clocks in time-interpolated single-slope ADCs, the latter are generated by a conventional open-loop delay line. In order to correct the process voltage and temperature drift of the delay line, a digital backend calibration has been developed. It is also executed online, in-column, and at the end of each sample conversion. The introduced concept has been tested in silicon, and has showed promising results for its introduction in practical mass-production scenarios. Methods for reference voltage generation in single-slope ADCs have also been looked at. The origins of error and noise phenomenona, which occur during both the discrete and continuous-time conversion phases in a single-slope ADC have been mathematically formalized. A method for practical measurement of noise on the ramp reference voltage has also been presented. Multiphase clock interpolation schemes are difficult for implementation when high interpolation factors are used, due to their quadratic clock phase growth with resolution. To allow high interpolation factors a time-domain binary search concept with error calibration has been introduced. Although the study being conceptual, it shows promising results for highly efficient implementations, if a solution to stable column-level unit delays can be found. The latter is listed as a matter of future investigations.
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Kitchen, Alistair J. "CMOS digital pixel sensor array with time domain analogue to digital conversion." Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2004. https://ro.ecu.edu.au/theses/765.
Full textAbstract:
This thesis presents a digital pixel sensor array, which is the first stage of an ongoing project to produce a CMOS image sensor with on-chip image processing. The analogue to digital conversion is performed at the pixel level, with the result stored in pixel memory. This architecture allows fast, reliable access to the image data and simplifies the integration of the image array and the processing logic. Each pixel contains a photodiode sensor, a comparator, memory and addressing logic. The photodiode sensor operates in integrating mode, where the photodiode junction capacitance is first charged to an initial voltage, and then discharged by the photodiode leakage current, which is comprised mainly of optically generated carriers. The analogue to digital conversion is performed by measuring the time taken for the photodiode cathode voltage to fall from its initial voltage, to the comparator reference voltage. This triggers the 8-bit pixel memory, which stores a data value representative of the time. The trigger signal also resets the photodiode, which conserves the charge stored in the junction capacitance, and also prevents blooming. An on-chip control circuit generates the digital data that is distributed globally to the array. The control circuit compensates for the inverse relationship between the integration time and the photocurrent by adjusting the data clock timing. The period of the data clock is increased at the same rate as the integration time, resulting in a linear relationship between the digital data and the photocurrent. The design is realised as a 64 x 64 pixel array, manufactured in O.35µm 3.3 V CMOS technology. Each pixel occupies an area of 45µm x 45µm with a 12.3% fill factor, and the entire pixel array and control circuit measures 3.7mm x 3.9mm. Experimental results confirm the operation of the digital pixel, and the linearising control circuit. The digital pixel has a dynamic range of 85dB, and can be adapted to different lighting conditions by varying a single clock frequency. The data captured by the array can be randomly accessed, and is read from the array nondestructivcly.
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Arora, Rajan. "Trade-offs between performance and reliability of sub 100-nm RF-CMOS technologies." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50140.
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The objective of this research is to develop an understanding of the trade-offs between performance and reliability in sub 100-nm silicon-on-insulator (SOI) CMOS technologies. Such trade-offs can be used to demonstrate high performance reliable circuits in scaled technologies. Several CMOS reliability concerns such as hot-carrier stress, ionizing irradiation damage, RF stress, temperature effects, and single-event effects are studied. These reliability mechanisms can cause temporary or permanent damage to the semiconductor device and to the circuits using them. Several improvements are made to the device layout and process to achieve optimum performance. Parasitics are shown to play a dominant role in the performance and reliability of sub 100-nm devices. Various techniques are suggested to reduce these parasitics, such as the use of the following: a) optimum device-width, b) optimum gate-finger to gate-finger spacing, c) optimum source/drain metal contact spacing, and d) floating-body/body-contact. The major contributions from this research are summarized as follows: 1) Role of floating-body effects on the performance and reliability of sub 100-nm CMOS-on-SOI technologies is investigated for the first time [1], [2]. It is demonstrated through experimental data and TCAD simulations that floating-body devices have improved RF performance but degraded reliability compared to body-contacted devices. 2) Floating-body effects in a cascode core is studied. Cascode cores are demonstrated to achieve much larger reliability lifetimes than a single device. A variety of cascode topologies are studied to achieve the trade-o s between performance and reliability for high-power applications [2]. 3) The use of body-contact to modulate the performance of devices and single-poledouble- throw (SPDT) switches is studied. The SPDT switch performance is shown to improve with a negative body-bias. 4) The impact of device width on the RF performance and reliability is studied. Larger width devices are shown to have greater degradation, posing challenging questions for RF design in strained-Si technologies [3]. 5) A novel study showing the e ect of source/drain metal contact spacing and gate-finger to gate-finger spacing on the device RF performance is carried out. Further, the impact of above on the hot-carrier, RF stress, and total-dose irradiation tolerance is studied [3], [4]. 6) Latchup phenomenon in CMOS is shown to be possible at cryogenic temperatures (below 50 K), and its consequences are discussed [5]. 7) A time-dependent device degradation model has been developed in technology computer aided design (TCAD) to model reliability in CMOS and SiGe devices. 8) The total-dose irradiation tolerance and hot-carrier reliability of 32-nm CMOSon- SOI technology is reported for the first time. The impact of HfO2 based gate dielectric on the performance and reliability is studied [6]. 9) The impact of technology scaling from 65-nm to 32-nm on the performance and reliability of CMOS technologies is studied [6]. 10) Cryogenic performance and reliability of 45-nm nFETs is investigated. The RF performance improves significantly at 77 K. The hot-carrier device reliability is shown to improve at low temperatures in short-channel CMOS technologies.
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Marble, William Joel. "Design and Analysis of Charge-Transfer Amplifiers for Low-Power Analog-to-Digital Converter Applications." BYU ScholarsArchive, 2004. https://scholarsarchive.byu.edu/etd/35.
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The demand for low-power A/D conversion techniques has motivated the exploration of charge-transfer amplifiers (CTAs) to construct efficient, precise voltage comparators. Despite notable advantages over classical, continuous-time architectures, little is understood about the dynamic behavior of CTAs or their utility in precision A/D converters. Accordingly, this dissertation presents several advancements related to the design and analysis of charge-transfer amplifiers for low-power data conversion. First, an analysis methodology is proposed which leads to a deterministic model of the voltage transfer function. The model is generalized to any timing scheme and can be extended to account for nonlinear threshold modulation. The model is compared with simulation results and test chip measurements, and shows good agreement over a broad range of circuit parameters. Three new charge-transfer amplifier architectures are proposed to address the limitations of existing designs: first, a truly differential CTA which improves upon the pseudo-differential configuration; second, a CTA which achieves more than 10x reduction in input capacitance with a moderate reduction in common mode range; third, a CTA which combines elements of the first two but also operates without a precharge voltage and achieves nearly rail to rail input range. Results from test chips fabricated in 0.6 um CMOS are described. Power dissipation in CTAs is considered and an idealized power consumption model is compared with measured test chip results. Four figures of merit (FOMs) are also proposed, incorporating power dissipation, active area, input charging energy and accuracy. The FOMs are used to compare the relative benefits and costs of particular charge-transfer amplifiers with respect to flash A/D converter applications. The first 10-bit CTA-based A/D converter is reported. It consumes low dynamic power of 600 uW/MSPS from a 2.1 V supply, 40% less than the current state of the art of 1 mW/MSPS. This subranging type converter incorporates capacitive interpolation to achieve a nearly ideal comparator count and power consumption. A distributed sample-and-hold (S/H) eliminates the need for a separate S/H amplifier. A test chip, fabricated in 0.6 um 2P/3M CMOS, occupies 2.7 mm2 and exhibits 8.2 effective bits at 2 MSPS.
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Soukup, Luděk. "Návrh digitálně-analogového převodníku typu sigma-delta v technologii CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2012. http://www.nusl.cz/ntk/nusl-219761.
Full textAbstract:
This master’s thesis deals with the issue of digital to analog conversion and possibility of its realization in digital circuits. Goal of this project is to design sigma-delta digital to analog converter with resolution of 14 bits and frequency band (0 ÷ 20) kHz. Main functional blocks: interpolator and modulator sigma-delta will be realized like digital structures. Reconstruction filter will be realized like an analog structure. For design a check of parameters of designed converter programs MATLAB and Simulink are used. Designed digital structures will be described by VHDL language.
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Toledo, Pedro Filipe Leite Correia de. "Modelamento e análise do efeito de coeficiente nulo de temperatura (ZTC) do Mosfet para aplicações análogicas de baixa sensibilidade têrmica." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/140814.
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A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C.Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.
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Barazi, Yazan. "Fast short-circuit protection for SiC MOSFETs in extreme short-circuit conditions by integrated functions in CMOS-ASIC technology." Thesis, Toulouse, INPT, 2020. http://www.theses.fr/2020INPT0091.
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Les transistors de puissance grands gaps tels que les MOSFETs SiC et HEMT GaN repoussent les compromis classiques en électronique de puissance. Brièvement, des gains significatifs ont été démontrés par les transistors SiC et GaN: meilleurs rendements, couplés à une augmentation des densités de puissance offertes par la montée en fréquence de découpage. Les MOSFET SiC à haute tension présentent des spécificités telles qu'une faible tenue en court-circuit (SC) par rapport aux IGBT Si et un oxyde de grille aminci, et une tension de commande rapprochée grillesource élevée. La polarisation négative sur la grille à l'état bloqué crée un stress supplémentaire qui réduit la fiabilité du MOSFET SiC. La forte polarisation positive de la grille provoque un courant de saturation de drain important en cas de SC. Ainsi, cette technologie fait émerger des besoins spécifiques de surveillance et de protection ultra-rapides. Pour cela, le travail de cette thèse se focalise sur deux études pour surmonter ces contraintes toute en gardant un bon compromis de performances entre « niveau d’intégration technologique ‘CMS/ASIC-CMOS’–rapidité–robustesse ». La première, regroupe un ensemble de solutions nouvelles permettant une détection du courtcircuit sur le cycle de commutation, sur la base d'une architecture conventionnelle de commande rapprochée dite à 2 niveaux de tension. La deuxième étude est plus exploratoire et basée sur une nouvelle architecture de gate–driver, dite multi-niveaux, à faible niveau de stress pour le MOSFET SiC tout en maintenant les performances dynamiques. Les travaux portent tout d’abord sur l’environnement du SiC MOSFET, (caractérisation et propriétés de comportement en SC par simulations orientées "circuit" de type PLECS™ et LTSpice™), puis présentent une étude bibliographique sur les commandes rapprochées dites Gate Driver, une étude approfondie a été réalisée sur les court-circuits type I & II (Hard switch fault) (Fault under Load) ; regroupés dans un premier chapitre du manuscrit. Un banc de test réalisé antérieurement au sein du laboratoire, a permis de compléter et de valider l’étude d'analyse-simulation et de préparer des stimuli test pour l'étape de conception des nouvelles solutions. Inspirée par la méthode de Gate charge apparue pour les IGBTs en silicium et évoquée pour les MOSFETs SiC, cette première approche fait l'objet d'un travail de conception, de dimensionnement et de prototypage. Cette méthode de référence permet une détection de type HSF en moins de 200ns sous 0-600V avec des composants 1,2kV allant de 80 mOhm à 120mOhm. S'agissant des nouvelles méthodes de détection rapides et intégrées, les travaux de cette thèse se focalisent particulièrement sur la conception d’un circuit ASIC CMOS. Pour cela, la conception d’un gate driver adapté est essentiel. Un ASIC est conçu en technologie X-Fab XT-0,18μm SOICMOS sous Cadence™, et puis mis en boitier et assemblé sur PCB conçu pour les besoins de tests et adaptable au banc principal. La conception du gate driver a considéré de nombreuses fonctions (détection du SC, SSD Soft shut down, buffer segmenté, AMC Active Miller Clamp", …). Du point de vue de la détection du SC, les fonctions nouvelles de surveillance intégrées concernent la méthode de dérivation temporelle de VGS qui est basée sur une détection par un circuit dérivateur analogique RC sur la séquence de plateau avec deux variantes. Une deuxième méthode nouvelle partiellement intégrée dans l'ASIC a été conçu, non développé dans ce mémoire dans le but d’une valorisation. En marge de cette étude principale, une étude exploratoire a porté sur une nouvelle architecture modulaire de commande rapprochée à plusieurs niveaux de tension de polarisation tirant profit de l'isolation SOI et des transistors CMOS à basse tension pour piloter le MOSFETs SiC et améliorer leur fiabilité grâce à une sélection active et dynamique à plusieurs niveaux sur les séquences de commutation et les états marche/arrêtWide bandgap power transistors such as SiC MOSFETs and HEMTs GaN push furthermore the classical compromises in power electronics. Briefly, significant gains have been demonstrated: better efficiency, coupled with an increase in power densities offered by the increase in switching frequency. HV SiC MOSFETs have specific features such as a low short-circuit SC withstand time capability compared to Si IGBTs and thinner gate oxide, and a high gate-to-source switching control voltage. The negative bias on the gate at the off-state creates additional stress which reduces the reliability of the SiC MOSFET. The high positive bias on the gate causes a large drain saturation current in the event of a SC. Thus, this technology gives rise to specific needs for ultrafast monitoring and protection. For this reason, the work of this thesis focuses on two studies to overcome these constraints, with the objective of reaching a good performance compromise between “CMS/ASIC-CMOS technological integration level-speed–robustness”. The first one, gathers a set of new solutions allowing a detection of the SC on the switching cycle, based on a conventional switch control architecture with two voltage levels. The second study is more exploratory and is based on a new gate-driver architecture, called multi-level, with low stress level for the SiC MOSFET while maintaining dynamic performances. The manuscript covers firstly the SiC MOSFET environment, (characterization and properties of SC behavior by simulation using PLECS and LTSpice software) and covers secondly a bibliographical study on the Gate drivers. And last, an in-depth study was carried out on SC type I & II (hard switch fault) (Fault under Load) and their respective detection circuits. A test bench, previously carried out in the laboratory, was used to complete and validate the analysis-simulation study and to prepare test stimuli for the design stage of new solutions. Inspired by the Gate charge method that appeared for Si IGBTs and evoked for SiC MOSFETs, this method has therefore been the subject of design, dimensioning and prototyping work, as a reference. This reference allows an HSF type detection in less than 200ns under 400V with 1.2kV components ranging from 80 to 120mOhm. Regarding new rapid and integrated detection methods, the work of this thesis focuses particularly on the design of a CMOS ASIC circuit. For this, the design of an adapted gate driver is essential. An ASIC is designed in X-Fab XT-0.18 SOICMOS technology under Cadence, and then packaged and assembled on a PCB. The PCB is designed for test needs and adaptable to the main bench. The design of the gate driver considered many functions (SC detection, SSD, segmented buffer, an "AMC", ...). From the SC detection point of view, the new integrated monitoring functions concern the VGS time derivative method which is based on a detection by an RC analog shunt circuit on the plateau sequence with two approaches: the first approach is based on a dip detection, i.e. the presence or not of the Miller plateau. The second approach is based on slope detection, i.e. the variability of the input capacitance of the power transistor under SC-HSF compared to normal operation. These methods are compared in the third chapter of the thesis, and demonstrate fault detection times between 40ns and 80ns, and preliminary robustness studies and critical cases are presented. A second new method is partially integrated in the ASIC, was designed. This method is not developed in the manuscript for valorization purposes. In addition to the main study, an exploratory study has focused on a modular architecture for close control at several bias voltage levels taking advantage of SOI isolation and low voltage CMOS transistors to drive SiC MOSFETs and improve their reliability through active and dynamic multi-level selection of switching sequences and on/off states
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Johansson, Mattias, and Jonas Ehrs. "Low-Power Low-Noise IQ Modulator Designs in 90nm CMOS for GSM/EDGE/WCDMA/LTE." Thesis, Linköping University, Department of Electrical Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-54552.
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The current consumption of the IQ modulator is a significant part of the totalcurrent consumption of a mobile transmitter platform and reducing it is of greatinterest. Also, as the WCDMA/LTE standards specifies full duplex transmissionsand Tx and Rx are most often using the same antenna, it is crucial to have asolution with low noise generation. Two new proposals have been studied with theaim to reduce the current consumption and noise contribution of the IQ modulator.
A current mode envelope tracking IQM is the first of the studied designs. Thisimplementation lowers the bias currents in the circuit in relation to the amplitudeof the baseband input signals, meaning that a low input amplitude results in alowering of the current consumption. It proves to be very efficient for basebandsignals with a high peak-to-average ratio. Simulations and calculations have shownthat an average current reduction of 56 % can be achieved for an arbitrary LTEbaseband signal.
The second is an entirely new passive mixer design where the baseband voltagesare sequentially copied to the RF node, removing the need for V-to-I conversion inthe mixer which reduces current consumption and noise. Results from simulationshas proven that this design is fully capable of improving both current consumptionas well as the noise levels. With an output power of 4.0 dBm, the power consumptionwas 43.3 mW, including clock generating circuits. This, combined with thefact that the design is small and simple, means that there is definitely a possibilityto replace the present IQM design with a passive mixer.
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Gamet, Arnaud. "Etude et mise en oeuvre de transitions passives aux interfaces circuit/boîtier pour les bases de temps intégrées résonantes." Thesis, Aix-Marseille, 2017. http://www.theses.fr/2017AIXM0002.
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L’intégration des oscillateurs dans les microcontrôleurs est aujourd’hui un enjeu industriel majeur suscitant une forte concurrence entre les principaux acteurs du marché. En effet, les oscillateurs sinusoïdaux sont des circuits indispensables, et sont majoritairement basés sur l’utilisation d’un résonateur à quartz ou MEMS externe. De plus en plus d’investigations sont menées afin d’intégrer des dispositifs résonants dans les boîtiers et éviter ainsi toutes les contraintes extérieures limitant les performances de l’oscillateur. En ce sens, nous avons étudié dans ce travail le comportement électrique, et notamment inductif, des liaisons filaires permettant de connecter une puce à son boîtier de protection. L’avantage d’utiliser ce composant passif est principalement son faible coût. Ce composant a été caractérisé en utilisant plusieurs méthodologies de modélisations et de mesures sur une large plage fréquentielle. Cette étude propose un modèle permettant aux concepteurs d’utiliser une caractéristique électrique équivalente dans une technologie CMOS standard. L’intégration du composant dans une cellule résonante est démontrée au sein d’un prototypeNowadays, the integration of oscillators into microcontrollers is a major industrial challenge which involves a large competition between the main actors of this market. Indeed, sine wave oscillators are essential circuits, and are fore the most part based on external crystal or MEMs resonators. More and more investigations are carried out in order to integrate the resonant structure into the package, and avoid all external constraints able to restrict the performances of the oscillator. With this in mind, we studied in this work the electrical behavior, in particular the inductive behavior of bond wires which are electrical connections between a die and its package. The main advantage to use this type of component is its low cost of manufacturing. This passive component has been characterized using several measurement tools on a wide range of frequencies. A RLC model has been presented, allowing analogue designers to use an electrical equivalent circuit in standard CMOS technology. The integration of the passive component in a resonant cell has been demonstrated in a prototype
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Chan, Yan Fong Joseph Yves. "Etude et réalisation de structures CMOS analogiques pour application haute fréquence." Grenoble INPG, 1989. http://www.theses.fr/1989INPG0056.
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Ce travail a pour but d'etudier les problemes associes a la realisation de circuits cmos analogiques destines a des applications haute frequence (freq. Echant. Sup. Un mhz). La premiere partie traite de la modelisation dynamique du transistor mos. La caracterisation du tmos en hf a l'aide des parametres s a permis de valider un modele petit signal valable pour des frequences atteignant les quelques ghz. La deuxieme partie examine les principaux problemes associes aux structures echantillonnees, telles les capacites commutees (cc). Le probleme de l'injection de charges a pu etre quantifie pour differents interrupteurs par des mesures experimentales. La derniere partie traite de l'amplification et du filtrage a cc a haute frequence. Un filtre elliptique d'ordre cinq a cc, utilisant le principe du double echantillonnage et des nouvelles structures d'interface a ete concu dans une technologie cmos 2
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Aleksandar, Pajkanović. "Пројектовање и карактеризација индуктора и нискошумног појачавача у технологији монолитних интегрисаних кола за широкопојасне примене." Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2018. https://www.cris.uns.ac.rs/record.jsf?recordId=107143&source=NDLTD&language=en.
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Пасивна индуктивна компонента и нискошумни појачавач у технологијимонолитних интегрисаних кола за широкопојасне примјене пројектованису, фабриковани и карактерисани. Приликом пројектовања индуктораизабрана је топологија меандар, а осим софтверских алата запројектовање интегрисаних кола, кориштен је и симулаторелектромагнетског поља. Осим карактеризације основних параметара,пажња је посвећена и анализи процесних и температурских варијација.Спроведена је механичка карактеризација материјала од којег се састојизаштитни слој фабрикованог интегрисаног кола. Нискошумни појачавачпројектован је као први степен пријемника широкопојасне технологије, акарактеризацијом је потврђена успјешност поступка.Pasivna induktivna komponenta i niskošumni pojačavač u tehnologijimonolitnih integrisanih kola za širokopojasne primjene projektovanisu, fabrikovani i karakterisani. Prilikom projektovanja induktoraizabrana je topologija meandar, a osim softverskih alata zaprojektovanje integrisanih kola, korišten je i simulatorelektromagnetskog polja. Osim karakterizacije osnovnih parametara,pažnja je posvećena i analizi procesnih i temperaturskih varijacija.Sprovedena je mehanička karakterizacija materijala od kojeg se sastojizaštitni sloj fabrikovanog integrisanog kola. Niskošumni pojačavačprojektovan je kao prvi stepen prijemnika širokopojasne tehnologije, akarakterizacijom je potvrđena uspješnost postupka.
A passive inductive component and a low-noise amplifier are designed,fabricated in standard monolithic CMOS technology and characterized, bothintended for wideband operation. For the design of the inductor, meandertopology is chosen. Along with the integrated circuit design tools,electromagnetic field simulator is used. Besides the standard parametercharacterization, special attention is dedicated to the analysis of process andtemperature variations. Furthermore, mechanical characterization of thematerial that comprises the protection layer has been undertaken. Low-noiseamplifier is designed as the first stage of an ultra wideband receiver and theresults show that the circuit is successfully designed.
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Germanovix, Walter. "Analogue techniques for micro-power cochlear implants." Thesis, Imperial College London, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313753.
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Gordon, Christal. "Bio-inspired, bio-compatible, reconfigurable analog CMOS circuits." Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/37222.
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This work details CMOS, bio-inspired, bio-compatible circuits which were used as synapses between an artificial neuron and a living neuron and between two living neurons. An intracellular signal from a living neuron was amplified, an integrate-and-fire neuron was used as a simple processing element to detect the spikes, and an artificial synapse was used to send outputs to another living neuron.
The key structure is an electronic synapse which is based around a floating-gate pFET. The charge on the floating-gate is analogous to the synaptic weight and can be modified. This modification can be viewed as similar to long-term potentiation and long-term depression. The modification can either be programmed (supervised learning) or can adapt to the inputs (unsupervised learning). Since the technology to change the floating-gate weight has greatly improved, these weights can be set quickly and accurately. Intrinsic floating-gate learning rules were explored and the ability to change the synaptic weight was shown.
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Mantooth, Homer Alan. "Higher level modeling of analog integrated circuits." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/14951.
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Zhao, Wei. "Development of CMOS sensor with digital pixels for ILD vertex detector." Thesis, Strasbourg, 2015. http://www.theses.fr/2015STRAE004/document.
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La thèse présente le développement de CPS (CMOS Pixel Sensors) intégré avec CAN au niveau du pixel pour les couches externes du détecteur de vertex de l’ILD (International Large Detector). Motivé par la physique dans l’ILC (International Linear Collider), une précision élevée est nécessaire pour les détecteurs. La priorité des capteurs qui montre sur les couches externes est une faible consommation d’énergie en raison du rapport élevé de couverture de la surface sensible (~90%) dans le détecteur de vertex. Le CPS intégré avec CAN est un choix approprié pour cette application. L’architecture de CAN de niveau colonne ne fournit pas une performance optimisée en termes de bruit et la consommation d’énergie. La conception de CAN au niveau du pixel a été proposée. Bénéficiant des sorties de pixels tout-numérique, CAN au niveau des pixels présentent les mérites évidents sur le bruit, la vitesse, la zone sensible et la consommation d’énergie. Un prototype de capteur, appelé MIMADC, a été implémenté par un processus de 0.18 μm CIS (CMOS Image Sensor). L’objectif de ce capteur est de vérifier la faisabilité du CPS intégré avec les CAN au niveau des pixels. Trois matrices sont incluses dans ce prototype, mais avec deux types différents de CAN au niveau de pixel: une avec des CAN à registre à approximations successives (SAR), et les deux autres avec des CAN à une seule pente (Single-Slope, SS) CAN. Toutes les trois possédant les pixels de la même taille de 35×35 μm2 et une résolution de 3-bit. Dans ce texte, des analyses théoriques et le prototype sont présentés, ainsi que la conception détaille des circuitsThis thesis presents the development of CMOS pixel sensors (CPS) integrated with pixel-level ADCs for the outer layers of the ILD (International Large Detector) vertex detector. Driven by physics in the ILC (International Linear Collider), an unprecedented precision is required for the detectors. The priority of the sensors mounted on the outer layers is low power consumption due to the large coverage ratio of the sensitive area (~90%) in the vertex detector. The CPS integrated with ADCs is a promising candidate for this application. The architecture of column-level ADCs, exists but do not provide an optimized performance in terms of noise and power consumption. The concept of pixel-level ADCs has been proposed. Benefiting from the all-digital pixel outputs, pixel-level ADCs exhibit the obvious merits on noise, speed, insensitive area, and power consumption. In this thesis, a prototype sensor, called MIMADC, has been implemented by a 0.18 μm CIS (CMOS Image Sensor) process. The target of this sensor is to verify the feasibility of the CPS integrated with pixel-level ADCs. Three matrices are included in this prototype but with two different types of pixel-level ADCs: one with successive approximation register (SAR) ADCs, and the other two with single-slope (SS) ADCs. All of them feature a same pixel size of 35×35 μm2 and a resolution of 3-bit. In this thesis, the prototype is presented for both theoretical analyses and circuit designs. The test results of the prototype are also presented
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Paramesh, Jeyanandh K. "CMOS multi-antenna receivers : architectures and circuits /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/5980.
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Zarabadi, Seyed Ramezan. "Design of analog VLSI circuits in BICMOS/CMOS technology /." The Ohio State University, 1992. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487777170407338.
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Tenten, Wilfried. "Improved analog to digital converter circuits using CMOS technology." Thesis, University of Bath, 1990. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.329619.
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