Journal articles: 'Analog CMOS integrated circuits'

1

WANG, WEIZHI, and DONGMING JIN. "CMOS DESIGN OF ANALOG FUZZY SYSTEM." Journal of Circuits, Systems and Computers 14, no. 06 (December 2005): 1101–12. http://dx.doi.org/10.1142/s0218126605002830.

Full text

Abstract:

This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high precision.

APA, Harvard, Vancouver, ISO, and other styles

2

Xu, Haoran, Jianghua Ding, and Jian Dang. "Design and Characteristics of CMOS Inverter based on Multisim and Cadence." Journal of Physics: Conference Series 2108, no. 1 (November 1, 2021): 012034. http://dx.doi.org/10.1088/1742-6596/2108/1/012034.

Full text

Abstract:

Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for various types of communications. Based on multisim 14.0 and cadence, the characteristics and performance of CMOS inverter are studied by simulation.

APA, Harvard, Vancouver, ISO, and other styles

3

Rakús, Matej, Viera Stopjaková, and Daniel Arbet. "Design techniques for low-voltage analog integrated circuits." Journal of Electrical Engineering 68, no. 4 (August 28, 2017): 245–55. http://dx.doi.org/10.1515/jee-2017-0036.

Full text

Abstract:

AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

APA, Harvard, Vancouver, ISO, and other styles

4

Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.

Full text

Abstract:

Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to 1.2V, temperature coefficient is 3.09ppm/°C. Adopt a series of measures, like ESD protection circuit, in layout design. The ultimately design through the DRC and LVS verification, and the final layout size is 700μm * 560μm.

APA, Harvard, Vancouver, ISO, and other styles

5

Vera Casañas, César William, Thainann Henrique Pereira de Castro, Gabriel Antonio Fanelli de Souza, Robson Luiz Moreno, and Dalton Martini Colombo. "Review of CMOS Currente References." Journal of Integrated Circuits and Systems 17, no. 1 (April 30, 2022): 1–9. http://dx.doi.org/10.29292/jics.v17i1.592.

Full text

Abstract:

A current reference is able to provide a precise and accurate current for other circuits inside a chip. This type of electronic circuit is employed as a building block in numerous analog and mixed-signal circuits. Moreover, it is a fundamental component of current-mode circuits. This work discusses the basic and essential concepts of designing CMOS integrated current references. A review of conventional topologies is presented, including current mirrors and current references. Temperature dependence is discussed, along with PTAT and CTAT topologies, and some low-power/low-voltage implementations are also presented.

APA, Harvard, Vancouver, ISO, and other styles

6

Yu, Feixia, and Ming-C. Cheng. "Electrothermal simulation of SOI CMOS analog integrated circuits." Solid-State Electronics 51, no. 5 (May 2007): 691–702. http://dx.doi.org/10.1016/j.sse.2007.02.029.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

ALARCÓN, EDUARD, GERARD VILLAR, and ALBERTO POVEDA. "CMOS INTEGRATED CIRCUIT CONTROLLERS FOR SWITCHING POWER CONVERTERS." Journal of Circuits, Systems and Computers 13, no. 04 (August 2004): 789–811. http://dx.doi.org/10.1142/s0218126604001714.

Full text

Abstract:

Two case examples of high-speed CMOS microelectronic implementations of high-performance controllers for switching power converters are presented. The design and implementation of a current-programmed controller and a general-purpose feedforward one-cycle controller are described. The integrated circuit controllers attain high-performance by means of using current-mode analog signal processing, hence allowing high switching frequencies that extend the operation margin compared to previous designs. Global layout-extracted transistor-level simulation results for 0.8 μm and 0.35 μm standard CMOS technologies confirm both the correct operation of the circuits in terms of bandwidth as well as their functionality for the control of switching power converters. The circuits may be used either as standalone IC controllers or as controller circuits that are technology-compatible with on-chip switching power converters and on-chip loads for future powered systems-on-chip.

APA, Harvard, Vancouver, ISO, and other styles

8

Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (October 1, 2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

Full text

Abstract:

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

APA, Harvard, Vancouver, ISO, and other styles

9

Schmidt, Alexander, Holger Kappert, Wolfgang Heiermann, and Rainer Kokozinski. "A Cyclic RSD Analog-Digital-Converter for Application Specific High Temperature Integrated Circuits up to 250°C." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000214–19. http://dx.doi.org/10.4071/hitec-2012-wp13.

Full text

Abstract:

Silicon-on-Insulator (SOI) CMOS is the most commonly used technology for integrated circuits suitable for high temperatures and harsh environmental conditions. Data acquisition circuitry operating at these conditions has to consider the impact of wide temperature range operation. Therefore, the accurate operation of elementary building blocks is essential for proper system performance. To overcome the accuracy limitations set by channel leakage and performance degradation of NMOS and PMOS transistors, advanced circuit design methods are necessary. By introducing advanced leakage compensation, the overall performance of analog circuits at elevated temperatures is significantly improved. In this paper we present a cyclic analog-to-digital converter with a resolution of 12 bit, fabricated in a 1.0 μm SOI CMOS process. It utilizes the redundant signed digit (RSD) principle in a switched capacitor circuit and is thus insensitive to amplifier or comparator offset. In order to reduce the conversion error, leakage current compensated switches have been used. The ADC features two high gain operational amplifiers. Thereby a gain of more than 110 dB over the whole temperature range has been realized. The ADC's performance has been verified up to 250°C with an input voltage range from 0 V to 5 V. Preliminary results report an accuracy of more than 10 bits with a conversion rate of 1.25 kS/s. The supply voltage is 5 V with a maximum power consumption of 3.4 mW for the analog part of the circuit. The ADC is intended as an IP module to be used in customer specific mixed signal integrated circuits.

APA, Harvard, Vancouver, ISO, and other styles

10

ANTREICH, KURT J., HELMUT E. GRAEB, and CLAUDIA U. WIESER. "PRACTICAL METHODS FOR WORST-CASE AND YIELD ANALYSIS OF ANALOG INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 04, no. 03 (September 1993): 261–82. http://dx.doi.org/10.1142/s0129156493000121.

Full text

Abstract:

Worst-case analysis is commonly used in integrated circuit design to verify a satisfactory circuit performance with regard to changes in the manufacturing conditions. However, worst-case analysis is often carried out using approximate worst-case parameter sets. This paper presents a new approach to the worst-case design of integrated circuits that takes account of fluctuations in the operating conditions. It provides exact and unique worst-case manufacturing conditions and worst-case operating conditions for given circuit specifications. These specifications may be either performance limits or minimum yield requirements. The method is illustrated with the parametric design of integrated CMOS bias stages.

APA, Harvard, Vancouver, ISO, and other styles

11

Van der Plas, G., G. Debyser, F. Leyn, K. Lampaert, J. Vandenbussche, G. G. E. Gielen, W. Sansen, P. Veselinovic, and D. Leenarts. "AMGIE-A synthesis environment for CMOS analog integrated circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, no. 9 (2001): 1037–58. http://dx.doi.org/10.1109/43.945301.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Shoucair, F. "Design Consideration in High Temperature Analog CMOS Integrated Circuits." IEEE Transactions on Components, Hybrids, and Manufacturing Technology 9, no. 3 (September 1986): 242–51. http://dx.doi.org/10.1109/tchmt.1986.1136646.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

de Lima Moreto, Rodrigo Alves, Carlos Eduardo Thomaz, and Salvador Pinillos Gimenez. "Gaussian Fitness Functions for Optimizing Analog CMOS Integrated Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 10 (October 2017): 1620–32. http://dx.doi.org/10.1109/tcad.2017.2661804.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Francis, A. Matthew, Jim Holmes, Nick Chiolino, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (January 1, 2016): 000242–48. http://dx.doi.org/10.4071/2016-hitec-242.

Full text

Abstract:

Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time. Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

APA, Harvard, Vancouver, ISO, and other styles

15

Prajapati, Pankaj P., and Mihir V. Shah. "Automatic Circuit Design of CMOS Miller OTA Using Cuckoo Search Algorithm." International Journal of Applied Metaheuristic Computing 11, no. 1 (January 2020): 36–44. http://dx.doi.org/10.4018/ijamc.2020010103.

Full text

Abstract:

The circuit design of the CMOS based analog part of a mixed-signal integrated circuit (IC) needs a large fraction of the overall design cycle time. The automatic design of an analog circuit is inevitable, seeing recently development of System-on-Chip (SOC) design. This brings about the need to develop computer aided design (CAD) tools for automatic design of CMOS based analog circuits. In this article, a Cuckoo Search (CS) algorithm is presented for automatic design of a CMOS Miller Operational Transconductance Amplifier (OTA). The source code of the CS algorithm is developed using the C language. The Ngspice circuit simulator has been used as a fitness function creator and evaluator. A script file is written to provide an interface between the CS algorithm and the Ngspice simulator. BSIM3v3 MOSFET models with 0.18 µm and 0.35 µm CMOS technology have been used to simulate this circuit. The simulation results of this work are presented and compared with previous works reported in the literature. The experimental simulation results obtained by the CS algorithm satisfy all desired specifications for this circuit.

APA, Harvard, Vancouver, ISO, and other styles

16

Chen, Ethan, and Vanessa Chen. "Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications." Mathematics 8, no. 5 (May 20, 2020): 829. http://dx.doi.org/10.3390/math8050829.

Full text

Abstract:

While integrated circuit technologies keep scaling aggressively, analog, mixed-signal, and radio-frequency (RF) circuits encounter challenges by creating robust designs in advanced complementary metal–oxide–semiconductor (CMOS) processes with the diminishing voltage headroom. The increasing random mismatch of smaller feature sizes in leading-edge technology nodes severely limit the benefits of scaling for (RF)/analog circuits. This paper describes the details of the combinatorial randomness by statistically selecting device elements that relies on the significant growth in subsets number of combinations. The randomness can be utilized to provide post-manufacturing reconfiguration of the selectable circuit elements to achieve required specifications for ultra-low-power systems. The calibration methodology is demonstrated with an ultra-low-voltage chaos-based true random number generator (TRNG) for energy-constrained Internet of things (IoT) devices in the secure communications.

APA, Harvard, Vancouver, ISO, and other styles

17

KAMEDA, SEIJI, AKIRA HONDA, and TETSUYA YAGI. "REAL TIME IMAGE PROCESSING WITH AN ANALOG VISION CHIP SYSTEM." International Journal of Neural Systems 09, no. 05 (October 1999): 423–28. http://dx.doi.org/10.1142/s0129065799000423.

Full text

Abstract:

A linear analog network model is proposed to characterize the function of the outer retinal circuit in terms of the standard regularization theory. Inspired by the function and the architecture of the model, a vision chip has been designed using analog CMOS Very Large Scale Integrated circuit technology. In the chip, sample/hold amplifier circuits are incorporated to compensate for statistic transistor mismatches. Accordingly, extremely low noise outputs were obtained from the chip. Using the chip and a zero-crossing detector, edges of given images were effectively extracted in indoor illumination.

APA, Harvard, Vancouver, ISO, and other styles

18

Elmezayen, Mohamed R., Wei Hu, Amr M. Maghraby, Islam T. Abougindia, and Suat U. Ay. "Accurate Analysis and Design of Integrated Single Input Schmitt Trigger Circuits." Journal of Low Power Electronics and Applications 10, no. 3 (June 29, 2020): 21. http://dx.doi.org/10.3390/jlpea10030021.

Full text

Abstract:

Schmitt trigger (ST) circuits are widely used integrated circuit (IC) blocks with hysteretic input/output (I/O) characteristics. Like the I/O characteristics of a living neuron, STs reject noise and provide stability to systems that they are deployed in. Indeed, single-input/single-output (SISO) STs are likely candidates to be the core unit element in artificial neural networks (ANNs) due not only to their similar I/O characteristics but also to their low power consumption and small silicon footprints. This paper presents an accurate and detailed analysis and design of six widely used complementary metal-oxide-semiconductor (CMOS) SISO ST circuits. The hysteresis characteristics of these ST circuits were derived for hand calculations and compared to original design equations and simulation results. Simulations were carried out in a well-established, 0.35 μm/3.3 V, analog/mixed-signal CMOS process. Additionally, simulations were performed using a wide range of supplies and process variations, but only 3.3 V supply results are presented. Most of the new design equations provide better accuracy and insights, as broad assumptions of original derivations were avoided.

APA, Harvard, Vancouver, ISO, and other styles

19

Kanazawa, Yusuke, Tetsuya Asai, and Yoshihito Amemiya. "Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses." Journal of Robotics and Mechatronics 15, no. 2 (April 20, 2003): 208–18. http://dx.doi.org/10.20965/jrm.2003.p0208.

Full text

Abstract:

We discuss the integration architecture of spiking neurons, predicted to be next-generation basic circuits of neural processor and dynamic synapse circuits. A key to development of a brain-like processor is to learn from the brain. Learning from the brain, we try to develop circuits implementing neuron and synapse functions while enabling large-scale integration, so large-scale integrated circuits (LSIs) realize functional behavior of neural networks. With such VLSI, we try to construct a large-scale neural network on a single semiconductor chip. With circuit integration now reaching micron levels, however, problems have arisen in dispersion of device performance in analog IC and in the influence of electromagnetic noise. A genuine brain computer should solve such problems on the network level rather than the element level. To achieve such a target, we must develop an architecture that learns brain functions sufficiently and works correctly even in a noisy environment. As the first step, we propose an analog circuit architecture of spiking neurons and dynamic synapses representing the model of artificial neurons and synapses in a form closer to that of the brain. With the proposed circuit, the model of neurons and synapses can be integrated on a silicon chip with metal-oxide-semiconductor (MOS) devices. In the sections that follow, we discuss the dynamic performance of the proposed circuit by using a circuit simulator, HSPICE. As examples of networks using these circuits, we introduce a competitive neural network and an active pattern recognition network by extracting firing frequency information from input information. We also show simulation results of the operation of networks constructed with the proposed circuits.

APA, Harvard, Vancouver, ISO, and other styles

20

Yen, Chen, Wei, and Chung. "A CMOS Transmitter Analog Baseband for 5G Mobile Communication." Electronics 8, no. 11 (November 8, 2019): 1319. http://dx.doi.org/10.3390/electronics8111319.

Full text

Abstract:

CMOS analog baseband circuits including a low-pass filter (LPF) and a programmable gain amplifier (PGA) are designed and implemented for the fifth-generation (5G) mobile communication. The super source follower topology is adopted to achieve a wideband LPF with good linearity, while the constant current density gain control technique is used to implement gain cells of the PGA. The circuits are integrated as an analog baseband for a 5G transmitter (TX) and fabricated using TSMC 90-nm CMOS technology. The analog baseband exhibits the bandwidth from 1.03 to 1.05 GHz when the voltage gain is varied from −18.9 dB to 3.8 dB in 1-dB steps. The gain step errors are within −0.7 dB to 0.9 dB. In the highest gain mode, the analog baseband achieves the IP1dB of −10 dBv and the IIP3 of −0.2 dBv. Over the band of interest, the NF of the analog baseband is 24.4–40.0 dB.

APA, Harvard, Vancouver, ISO, and other styles

21

FRITZ, KARL E., BARBARA A. RANDALL, GREGG J. FOKKEN, MICHAEL J. DEGERSTROM, MICHAEL J. LORSUNG, JASON F. PRAIRIE, ERIC L. H. AMUNDSEN, et al. "HIGH-SPEED, LOW-POWER DIGITAL AND ANALOG CIRCUITS IMPLEMENTED IN IBM SiGe BiCMOS TECHNOLOGY." International Journal of High Speed Electronics and Systems 13, no. 01 (March 2003): 221–37. http://dx.doi.org/10.1142/s0129156403001582.

Full text

Abstract:

Under the auspices of Defense Advanced Research Project Agency's Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology, simulations and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS 5HP (50 GHz fT HBTs with 0.5 μm CMOS) and 7HP (120 GHz fT HBTs with 0.18 μm CMOS) technologies will be presented.

APA, Harvard, Vancouver, ISO, and other styles

22

FITRIO, DAVID, SUHARDI TJOA, ANAND MOHAN, RONNY VELJANOVSKI, ANDREW BERRY, and GORAN PANJKOVIC. "A CMOS ANALOG INTEGRATED CIRCUIT FOR PIXEL X-RAY DETECTOR." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 71–87. http://dx.doi.org/10.1142/s0218126611007086.

Full text

Abstract:

A front-end read-out application specific integrated circuit (ASIC) for a multichannel pixel X-Ray detector system has been fabricated and tested. The chip provides signal amplification for pixelated compound semiconductors such as Cadmium Telluride ( CdTe ) and Cadmium Zinc Telluride ( CZT ) with either 1 mm or 200 μm pitch. Both the detector (compound semiconductor) and ASIC are combined to target future research applicable to spectroscopic imaging in high intensity X-Ray biomedical detector systems. The ASIC was fabricated in a 0.35 μm process by Austria Microsystems and consists of 32 channels, where each channel contains a charge-sensitive amplifier, a pulse shaper and two further stages of amplification providing an overall gain of 1 mV per kilo electron volt (keV) for photons within the energy range of 30–120 keV. The preamplifier and shaper circuits are designed for both positive and negative charge collection (electrons and holes) produced by the CdTe or CZT detectors. The ASIC's shaper has been designed with a time constant of 100 ns to allow operation at photon rate events above 1 Million photons per pixel per second. The design and characterization of the readout chip will be discussed in this paper presenting results from both the simulated and the fabricated chip.

APA, Harvard, Vancouver, ISO, and other styles

23

Galembeck, Egon Henrique Salerno, Salvador Pinillos Gimenez, and Rodrigo Alves de Lima Moreto. "Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs." Electronics 11, no. 23 (November 27, 2022): 3923. http://dx.doi.org/10.3390/electronics11233923.

Full text

Abstract:

The design and optimization of the analog complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are intrinsically complicated and depend heavily on the designer’s experience, and are associated with very long design and optimization-cycle times. In addition, in order to the analog and radiofrequency (RF) CMOS IC work suitably in practice, it is necessary to perform robustness analyses (RAs) through Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, which result in still-higher design and optimization cycle times and therefore represent the biggest bottleneck to the launching of new electronic products. In this context, this manuscript aims to present, for the first time, the use of a custom imperialist competitive algorithm (ICA) in order to reduce the design and optimization-cycle times of analog CMOS ICs. In this study, we implement some Miller CMOS operational transconductance amplifiers (OTAs) using the computational tool named iMTGSPICE, considering two different bulk CMOS IC manufacturing processes from Taiwan Semiconductor Company (TSMC) (180 nm and 65 nm nodes) and two evolutionary optimization methodologies of artificial intelligence, i.e., ICA and a genetic algorithm (GA). The main result obtained by this work shows that, by using an ICA-customized evolutionary algorithm to perform the design and optimization processes of Miller CMOS OTAs, it is possible to reduce the design and optimization-cycle times by up to 83% in relation to those implemented with the GA-customized evolutionary algorithm, achieving practically the same electrical performance.

APA, Harvard, Vancouver, ISO, and other styles

24

ODAME, KOFI M., and BRADLEY A. MINCH. "THE TRANSLINEAR PRINCIPLE: A GENERAL FRAMEWORK FOR IMPLEMENTING CHAOTIC OSCILLATORS." International Journal of Bifurcation and Chaos 15, no. 08 (August 2005): 2559–68. http://dx.doi.org/10.1142/s0218127405013496.

Full text

Abstract:

In this Letter, we propose a class of nonlinear dynamic translinear circuits as a viable tool for the rapid and systematic implementation of chaotic oscillators in analog integrated circuits. In this regard, our primary focus is on multiple-input translinear element (MITE) networks and their particular merits. We also describe, as an illustrative example, our monolithic implementation of the Lorenz equations, and report on results from a test chip fabricated in a 0.5 μm CMOS process through MOSIS. We also show that Chua's circuit can be implemented easily in our framework.

APA, Harvard, Vancouver, ISO, and other styles

25

Kiela, Karolis, and Romualdas Navickas. "AUTOMATED INTEGRATED ANALOG FILTER DESIGN ISSUES / AUTOMATIZUOTOJO INTEGRINIŲ ANALOGINIŲ FILTRŲ PROJEKTAVIMO YPATUMAI." Mokslas – Lietuvos ateitis 7, no. 3 (July 13, 2015): 323–29. http://dx.doi.org/10.3846/mla.2015.793.

Full text

Abstract:

An analysis of modern automated integrated analog circuits design methods and their use in integrated filter design is done. Current modern analog circuits automated tools are based on optimization algorithms and/or new circuit generation methods. Most automated integrated filter design methods are only suited to gmC and switched current filter topologies. Here, an algorithm for an active RC integrated filter design is proposed, that can be used in automated filter designs. The algorithm is tested by designing an integrated active RC filter in a 65 nm CMOS technology. Atlikta naujausių integrinių analoginių grandynų automatizuotojo projektavimo metodų ir jų taikymo projektuojant integrinius filtrus analizė. Modernios analoginių grandynų automatizavimo priemonės yra grindžiamos esamos topologijos optimizacijos algoritmais ir/arba naujų elektroninių principinių schemų generavimo būdais. Didžioji dauguma literatūroje aprašytų automatizuotojo integrinių filtrų projektavimo metodų yra skirti tik gm-C arba perjungiamos srovės/talpos topologijos filtrams. Darbe siūlomas naujas integrinių aktyviųjų RC filtrų projektavimo algoritmas, įvertinantis integrinių technologijų elementų nuokrypius. Jis patikrintas suprojektavus integrinį aktyvųjį RC filtrą taikant 65 nm KMOP technologiją ir Cadence programinį paketą.

APA, Harvard, Vancouver, ISO, and other styles

26

Kumar, M. Kiran, Santhosh Deep Ettiyala, and Amrita Sajja. "A CMOS Power Efficient Analog Integrated Circuits for Neural Signal Acquisition." International Journal of Engineering Trends and Technology 23, no. 5 (May 25, 2015): 248–56. http://dx.doi.org/10.14445/22315381/ijett-v23p247.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Kumar, Umesh. "Simulation and Realization of Some CMOS-Transconductor Vhf Filters." Active and Passive Electronic Components 26, no. 3 (2003): 133–36. http://dx.doi.org/10.1080/08827510310001603401.

Full text

Abstract:

CMOS circuits for integrated analog filters at very high frequencies have been designed through PSPICE based on the Transconductance-C integrator. They have been implemented on the bread board and many filters i.e. LP, BP, Elliptic LP etc. are simulated and realized.

APA, Harvard, Vancouver, ISO, and other styles

28

Ibarra, F. Sandoval, and S. Ortega Cisneros. "Nyquist Model based Thermal Noise AnalysisFrom Passive Components to CMOS Circuits." International Journal of Emerging Technology and Advanced Engineering 11, no. 1 (January 26, 2021): 1–8. http://dx.doi.org/10.46338/ijetae0121_01.

Full text

Abstract:

The analysis of thermal noise in network components that have resistive properties is presented. Noise analysis, based on the Nyquist model, is calculated as the rms (voltage or current equivalent) noise generated by a transimpedance, which is the concept used by general-purpose circuit simulators like Spice. It shows how this concept is used and understood in RC circuits, and how to evaluate its effect in analog circuits, particularly in the design of CMOS integrated circuits. It is shown that the magnitude of the noise generated by a transistor is not of interest, but the net effect of all sources of thermal noise in circuits and systems, fundamentally, when the miniaturization of the transistor implies reducing the value of the supply voltages. The ultimate purpose of this contribution is to highlight the importance of noise analysis using fundamentals of circuit theory and identify the variables under the designer's control to minimize their effect on the performance of the circuits under development.

APA, Harvard, Vancouver, ISO, and other styles

29

Rasheed, Israa Mohammed, and Hassan Jasim Motlak. "Performance parameters optimization of CMOS analog signal processing circuits based on smart algorithms." Bulletin of Electrical Engineering and Informatics 12, no. 1 (February 1, 2023): 149–57. http://dx.doi.org/10.11591/eei.v12i1.4128.

Full text

Abstract:

Designing ideal analogue circuits has become difficult due to extremely large-scale integration. The complementary metal oxide semiconductor (CMOS) analog integrated circuits (IC) could use an evolutionary method to figure out the size of each device. The CMOS operational transconductance amplifier (CMOS OTA) and the CMOS current conveyor second generation (CMOS CCII) are designed using advanced nanometer transistor technology (180 nm). Both CMOS OTA and CMOS CCII have high performance, such as a wide frequency, voltage gain, slew rate, and phase margin, to include very wide applications in signal processing, such as active filters and oscillators. The optimization approach is an iterative procedure that uses an optimization algorithm to change design variables until the optimal solution is identified. In this study, different sorts of algorithms the genetic algorithm (GA), particle swarm optimization (PSO), and cuckoo search (CS) are employed to boost and enhance the performance parameters. While decreasing the time required to develop a conventional operation amplifier's settling time. Some studies decrease the value of the power utilized at various frequencies. Others operate at extremely high frequencies, but their power consumption is greater than that of those operating at lower frequencies.

APA, Harvard, Vancouver, ISO, and other styles

30

López-Portilla, Bárbaro M., Wladimir Valenzuela, Payman Zarkesh-Ha, and Miguel Figueroa. "A CMOS Image Readout Circuit with On-Chip Defective Pixel Detection and Correction." Sensors 23, no. 2 (January 13, 2023): 934. http://dx.doi.org/10.3390/s23020934.

Full text

Abstract:

Images produced by CMOS sensors may contain defective pixels due to noise, manufacturing errors, or device malfunction, which must be detected and corrected at early processing stages in order to produce images that are useful to human users and image-processing or machine-vision algorithms. This paper proposes a defective pixel detection and correction algorithm and its implementation using CMOS analog circuits, which are integrated with the image sensor at the pixel and column levels. During photocurrent integration, the circuit detects defective values in parallel at each pixel using simple arithmetic operations within a neighborhood. At the image-column level, the circuit replaces the defective pixels with the median value of their neighborhood. To validate our approach, we designed a 128×128-pixel imager in a 0.35μm CMOS process, which integrates our defective-pixel detection/correction circuits and processes images at 694 frames per second, according to post-layout simulations. Operating at that frame rate, our proposed algorithm and its CMOS implementation produce better results than current state-of-the-art algorithms: it achieves a Peak Signal to Noise Ratio (PSNR) and Image Enhancement Factor (IEF) of 45 dB and 198.4, respectively, in images with 0.5% random defective pixels, and a PSNR of 44.4 dB and IEF of 194.2, respectively, in images with 1.0% random defective pixels.

APA, Harvard, Vancouver, ISO, and other styles

31

Qi, Min, An-qiang Guo, and Dong-hai Qiao. "A High-Temperature, Low-Noise Readout ASIC for MEMS-Based Accelerometers." Sensors 20, no. 1 (December 31, 2019): 241. http://dx.doi.org/10.3390/s20010241.

Full text

Abstract:

This paper presents the development and measurement results of a complementary metal oxide semiconductor (CMOS) readout application-specific integrated circuit (ASIC) for bulk-silicon microelectromechanical system (MEMS) accelerometers. The proposed ASIC converts the capacitance difference of the MEMS sensor into an analog voltage signal and outputs the analog signal with a buffer. The ASIC includes a switched-capacitor analog front-end (AFE) circuit, a low-noise voltage reference generator, and a multi-phase clock generator. The correlated double sampling technique was used in the AFE circuits to minimize the low-frequency noise of the ASIC. A programmable capacitor array was implemented to compensate for the capacitance offset of the MEMS sensor. The ASIC was developed with a 0.18 μm CMOS process. The test results show that the output noise floor of the low-noise amplifier was −150 dBV/√Hz at 100 Hz and 175 °C, and the sensitivity of the AFE was 750 mV/pF at 175 °C. The output noise floor of the voltage reference at 175 °C was −133 dBV/√Hz at 10 Hz and −152 dBV/√Hz at 100 Hz.

APA, Harvard, Vancouver, ISO, and other styles

32

Alahdal, Abdulrahman, Anis Ammous, and Kaiçar Ammous. "Design and realization of an analog integrated circuit for maximum power point tracking of photovoltaic panels." EPJ Photovoltaics 13 (2022): 6. http://dx.doi.org/10.1051/epjpv/2022002.

Full text

Abstract:

The tracking of the maximum power point (MPP) of a photovoltaic (PV) solar panel is an important part of a PV generation chain. In order to track maximum power from the solar arrays, it is necessary to control the output impedance of the PV panel, so that the circuit can be operated at its Maximum Power Point (MPP), despite the unavoidable changes in the climate conditions such as temperature and Irradiance. A new MPPT analog technique to track the Maximum Power Point (MPP) of PV arrays is proposed. This new technique uses simple and classical functions of electronic circuits. An Off-Grid PV system was considered to apply and validate the proposed new technique. The entire circuit was implemented in circuit-oriented simulator Proteus-ISIS. We present the results associated with the design, the realization, and the experimentation of a PV system equipped with a new analog MPPT command. The obtained results have shown good efficiency of analog technique (more than 98.5%). The second part of the paper consists of the description of the design and the realization of the novel analog MPPT integrated chip. The integrated circuit (IC) was designed and realized using HV CMOS technology 0.35-µm.

APA, Harvard, Vancouver, ISO, and other styles

33

Tarim, T. B., M. Ismail, and H. H. Kuntman. "Robust design and yield enhancement of low-voltage CMOS analog integrated circuits." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 48, no. 4 (April 2001): 475–86. http://dx.doi.org/10.1109/81.917984.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Mouna Karmani, Chiraz Khedhiri, Belgacem Hamdi, and Brahim Bensalem. "A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits." International Journal of VLSI Design & Communication Systems 2, no. 3 (September 30, 2011): 1–19. http://dx.doi.org/10.5121/vlsic.2011.2301.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Honda, Wataru, Takayuki Arie, Seiji Akita, and Kuniharu Takei. "Bendable CMOS Digital and Analog Circuits Monolithically Integrated with a Temperature Sensor." Advanced Materials Technologies 1, no. 5 (May 25, 2016): 1600058. http://dx.doi.org/10.1002/admt.201600058.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Kladovščikov, Leonid, Marijan Jurgo, and Romualdas Navickas. "Design of an Oscillation-Based BIST System for Active Analog Integrated Filters in 0.18 µm CMOS." Electronics 8, no. 7 (July 20, 2019): 813. http://dx.doi.org/10.3390/electronics8070813.

Full text

Abstract:

In this paper, an oscillation-based built-in self-test system for active an analog integrated circuit is presented. This built-in self-test system was used to detect catastrophic and parametric faults, introduced during chip manufacturing. As circuits under test (CUT), second-order Sallen-Key, Akerberg-Mossberg and Tow-Thomas biquad filters were designed. The proposed test hardware detects parametric and catastrophic faults on changeable limits. The influence of both oscillation and test hardware on fault detection limits were investigated and analyzed. The proposed oscillation based self-test system was designed and simulated in 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. Due to the easiness of implementation and configuration for testing of different active analog filters, such self-test systems can be effectively used in modern integrated circuits, made of a large number of devices and circuits, such as the multi-standard transceivers used in the core hardware of software-defined radios. Using the proposed test strategy, the fault tolerance limits for catastrophic faults varied from 96% to 100% for all injected faults in different structures of low pass filters (LPF). The detection range of parametric faults of passive components’ nominal value, depending on the used structure of the filter, did not exceed –0.74% – 0.72% in case of Sallen-Key, –3.31% – 1.00% in case of Akerberg-Mossberg and –2.39% – 1.44% in case of Tow-Thomas LPF.

APA, Harvard, Vancouver, ISO, and other styles

37

Jendernalik, W., G. Blakiewicz, A. Handkiewicz, and M. Melosik. "Analogue CMOS ASICs in Image Processing Systems." Metrology and Measurement Systems 20, no. 4 (December 1, 2013): 613–22. http://dx.doi.org/10.2478/mms-2013-0052.

Full text

Abstract:

Abstract In this paper a survey of analog application specific integrated circuits (ASICs) for low-level image processing, called vision chips, is presented. Due to the specific requirements, the vision chips are designed using different architectures best suited to their functions. The main types of the vision chip architectures and their properties are presented and characterized on selected examples of prototype integrated circuits (ICs) fabricated in complementary metal oxide semiconductor (CMOS) technologies. While discussing the vision chip realizations the importance of low-cost, low-power solutions is highlighted, which are increasingly being used in intelligent consumer equipment. Thanks to the great development of the automated design environments and fabrication methods, new, so far unknown applications of the vision chips become possible, as for example disposable endoscopy capsules for photographing the human gastrointestinal tract for the purposes of medical diagnosis.

APA, Harvard, Vancouver, ISO, and other styles

38

Kappert, Holger, Stefan Dreiner, Dirk Dittrich, Katharina Grella, Andreas Kelberer, Miriam Klusmann, Norbert Kordas, et al. "High Temperature 0.35 Micron Silicon-on-Insulator CMOS Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000154–58. http://dx.doi.org/10.4071/hitec-wa14.

Full text

Abstract:

Silicon-on-Insulator (SOI) is the most commonly used technology for integrated circuits capable of operating at high temperature. Due to the efficient reduction of leakage current paths much higher operation temperatures are achievable with SOI than with bulk technologies. Published work on high temperature CMOS circuits typically refers to technologies with a minimum feature size of 0.8 to 1.0 micron [1][2][3] even though for complex digital circuits this results in large die size. Technologies with smaller feature size are available but typically not suitable for reliable high temperature operation due to high leakage currents, decreasing threshold voltages over temperature or reliability issues with the standard aluminum metallization. Fraunhofer IMS has developed a high temperature 0.35 micron thin film SOI technology. The mixed signal technology provides numerous devices, e.g. specific transistors for analog and digital circuit design, diodes, resistors and voltage independent capacitors. Also non-volatile memory cells (EEPROM) are available. In addition the technology is equipped with a tungsten metallization for highly reliable operation even at high temperatures. An overview on the new technology including characterization results of devices and test circuits is given in this paper.

APA, Harvard, Vancouver, ISO, and other styles

39

Sanabria-Borbón, Adriana, Sergio Soto-Aguilar, Johan Estrada-López, Douglas Allaire, and Edgar Sánchez-Sinencio. "Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design." Electronics 9, no. 4 (April 23, 2020): 685. http://dx.doi.org/10.3390/electronics9040685.

Full text

Abstract:

Optimization algorithms have been successfully applied to the automatic design of analog integrated circuits. However, many of the existing solutions rely on expensive circuit simulations or use fully customized surrogate models for each particular circuit and technology. Therefore, the development of an easily adaptable low-cost and efficient tool that guarantees resiliency to variations of the resulting design, remains an open research area. In this work, we propose a computationally low-cost surrogate model for multi-objective optimization-based automated analog integrated circuit (IC) design. The surrogate has three main components: a set of Gaussian process regression models of the technology’s parameters, a physics-based model of the MOSFET device, and a set of equations of the performance metrics of the circuit under design. The surrogate model is inserted into two different state-of-the-art optimization algorithms to prove its flexibility. The efficacy of our surrogate is demonstrated through simulation validation across process corners in three different CMOS technologies, using three representative circuit building-blocks that are commonly encountered in mainstream analog/RF ICs. The proposed surrogate is 69 X to 470 X faster at evaluation compared with circuit simulations.

APA, Harvard, Vancouver, ISO, and other styles

40

Xu, Bin, Yong Gang Yuan, Ding Ma, Neng Bin Cai, and Xiang Yang Li. "Readout Integrated Circuits with Pixel-Level ADC for Ultraviolet FPA Applications." Applied Mechanics and Materials 229-231 (November 2012): 1499–502. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1499.

Full text

Abstract:

An array of 128×128 digital pixel sensors (DPS) that performs both in pixel light current integration and analog-to-digital conversion is presented. The pixel fabricated on a DP4M CMOS process provides a digital output of ultraviolet light intensity via an integrated multiple-channel bit-serial (MCBS) ADC. Due to low light current (~pA) of ultraviolet focal-plane-array, the architecture of capacitive trans-impedance amplifier (CTIA) is used. The proposed readout integrated circuits have a 12-bit resolution, 70dB dynamic range and 99% of linearity.

APA, Harvard, Vancouver, ISO, and other styles

41

Alimisis, Vassilis, Vassilis Mouzakis, Georgios Gennis, Errikos Tsouvalas, Christos Dimas, and Paul P. Sotiriadis. "A Hand Gesture Recognition Circuit Utilizing an Analog Voting Classifier." Electronics 11, no. 23 (November 26, 2022): 3915. http://dx.doi.org/10.3390/electronics11233915.

Full text

Abstract:

Electromyography is a diagnostic medical procedure used to assess the state of a muscle and its related nerves. Electromyography signals are monitored to detect neuromuscular abnormalities and diseases but can also prove useful in decoding movement-related signals. This information is vital to controlling prosthetics in a more natural way. To this end, a novel analog integrated voting classifier is proposed as a hand gesture recognition system. The voting classifiers utilize 3 separate centroid-based classifiers, each one attached to a different electromyographic electrode and a voting circuit. The main building blocks of the architecture are bump and winner-take-all circuits. To confirm the proper operation of the proposed classifier, its post-layout classification results (91.2% accuracy) are compared to a software-based implementation (93.8% accuracy) of the same voting classifier. A TSMC 90 nm CMOS process in the Cadence IC Suite was used to design and simulate the following circuits and architectures.

APA, Harvard, Vancouver, ISO, and other styles

42

Riddle, Alfy. "Fundamentals of High Frequency Analog CMOS Analog Integrated Circuits (Leblebici, D. and Leblebici, Y.) [Book Review]." IEEE Microwave Magazine 10, no. 7 (2009): 92. http://dx.doi.org/10.1109/mmw.2009.934505.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Zamora, Iván, Eyglis Ledesma, Arantxa Uranga, and Núria Barniol. "Miniaturized 0.13-μm CMOS Front-End Analog for AlN PMUT Arrays." Sensors 20, no. 4 (February 22, 2020): 1205. http://dx.doi.org/10.3390/s20041205.

Full text

Abstract:

This paper presents an analog front-end transceiver for an ultrasound imaging system based on a high-voltage (HV) transmitter, a low-noise front-end amplifier (RX), and a complementary-metal-oxide-semiconductor, aluminum nitride, piezoelectric micromachined ultrasonic transducer (CMOS-AlN-PMUT). The system was designed using the 0.13-μm Silterra CMOS process and the MEMS-on-CMOS platform, which allowed for the implementation of an AlN PMUT on top of the CMOS-integrated circuit. The HV transmitter drives a column of six 80-μm-square PMUTs excited with 32 V in order to generate enough acoustic pressure at a 2.1-mm axial distance. On the reception side, another six 80-μm-square PMUT columns convert the received echo into an electric charge that is amplified by the receiver front-end amplifier. A comparative analysis between a voltage front-end amplifier (VA) based on capacitive integration and a charge-sensitive front-end amplifier (CSA) is presented. Electrical and acoustic experiments successfully demonstrated the functionality of the designed low-power analog front-end circuitry, which outperformed a state-of-the art front-end application-specific integrated circuit (ASIC) in terms of power consumption, noise performance, and area.

APA, Harvard, Vancouver, ISO, and other styles

44

Kim, Min-Su, Youngoo Yang, Hyungmo Koo, and Hansik Oh. "The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology." Applied Sciences 11, no. 1 (January 4, 2021): 429. http://dx.doi.org/10.3390/app11010429.

Full text

Abstract:

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

APA, Harvard, Vancouver, ISO, and other styles

45

Medina-Santiago, Alejandro, Carlos Arturo Hernández-Gracidas, Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Monica Amador García, and Jorge Antonio Orozco Torres. "CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions." Sensors 21, no. 21 (October 25, 2021): 7071. http://dx.doi.org/10.3390/s21217071.

Full text

Abstract:

The design of neural network architectures is carried out using methods that optimize a particular objective function, in which a point that minimizes the function is sought. In reported works, they only focused on software simulations or commercial complementary metal-oxide-semiconductor (CMOS), neither of which guarantees the quality of the solution. In this work, we designed a hardware architecture using individual neurons as building blocks based on the optimization of n-dimensional objective functions, such as obtaining the bias and synaptic weight parameters of an artificial neural network (ANN) model using the gradient descent method. The ANN-based architecture has a 5-3-1 configuration and is implemented on a 1.2 μm technology integrated circuit, with a total power consumption of 46.08 mW, using nine neurons and 36 CMOS operational amplifiers (op-amps). We show the results obtained from the application of integrated circuits for ANNs simulated in PSpice applied to the classification of digital data, demonstrating that the optimization method successfully obtains the synaptic weights and bias values generated by the learning algorithm (Steepest-Descent), for the design of the neural architecture.

APA, Harvard, Vancouver, ISO, and other styles

46

Alimisis, Vassilis, Christos Dimas, Georgios Pappas, and Paul P. Sotiriadis. "Analog Realization of Fractional-Order Skin-Electrode Model for Tetrapolar Bio-Impedance Measurements." Technologies 8, no. 4 (November 2, 2020): 61. http://dx.doi.org/10.3390/technologies8040061.

Full text

Abstract:

This work compares two design methodologies, emulating both AgCl electrode and skin tissue Cole models for testing and verification of electrical bio-impedance circuits and systems. The models are based on fractional-order elements, are implemented with active components, and capture bio-impedance behaviors up to 10 kHz. Contrary to passive-elements realizations, both architectures using analog filters coupled with adjustable transconductors offer tunability of the fractional capacitors’ parameters. The main objective is to build a tunable active integrated circuitry block that is able to approximate the models’ behavior and can be utilized as a Subject Under Test (SUT) and electrode equivalent in bio-impedance measurement applications. A tetrapolar impedance setup, typical in bio-impedance measurements, is used to demonstrate the performance and accuracy of the presented architectures via Spectre Monte-Carlo simulation. Circuit and post-layout simulations are carried out in 90-nm CMOS process, using the Cadence IC suite.

APA, Harvard, Vancouver, ISO, and other styles

47

Rohith Krishnan, R., and S. Krishnakumar. "An Approach Towards Design of Analog Integrated Circuits Based on Fixator–Norator Pair." Journal of Circuits, Systems and Computers 26, no. 06 (March 5, 2017): 1750100. http://dx.doi.org/10.1142/s0218126617501006.

Full text

Abstract:

This paper presents a novel method for the design of analog integrated circuit, making use of fixator–norator pairs for the performance design and biasing design. Fixators are the distinctive tools for setting a critical design parameter at a desired value whereas the pairing norator renders these critical parameters into adequate supporting components, mainly resistors. For analog ICs, active loads and current mirrors serve as supporting components. Hence, the use of fixator–norator pairs may abbreviate as defining the dynamic and static resistance of active loads and current mirrors that should be affirmative with a given design. The proposed methodology is illustrated by the use of a common emitter amplifier, a BJT differential amplifier, a MOS operational amplifier and a three-stage CMOS operational amplifier.

APA, Harvard, Vancouver, ISO, and other styles

48

Sabiri, Issa, Hamid Bouyghf, Abdelhadi Raihani, and Brahim Ouacha. "Optimal design of CMOS current mode instrumentation amplifier using bio-inspired method for biomedical applications." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 1 (January 1, 2022): 120. http://dx.doi.org/10.11591/ijeecs.v25.i1.pp120-129.

Full text

Abstract:

Analog integrated circuits for biomedical applications require good performance. This paper presents an instrumentation amplifier (IA) design based on three complementary metal oxide semiconductor (CMOS) conveyors with an active resistor. This circuit offers the possibility to control the gain by voltage and current. We have designed the IA to minimize the parasitic resistance (Rx) with large bandwidth and high common mode rejection ratio (CMRR) using the artificial bee colony algorithm (ABC). The topology is simulated using 0.35µm CMOS technology parameters. The optimization problem is represented by an objective function that will be implemented using MATLAB script. The results were approved by the simulation using the advanced design system (ADS) tool. The simulation results were compared to the characteristics of some other instrumentation amplifiers exsisting in the literature. The circuit has a higher CMRR than other topologies.

APA, Harvard, Vancouver, ISO, and other styles

49

Aparecido da Silva Braga, Rodrigo, Paulo Marcio Moreira e Silva, and Dean Bicudo Karolak. "Are CMOS Operational Transconductance Amplifiers Old Fashioned? A Systematic Review." Journal of Integrated Circuits and Systems 17, no. 1 (April 30, 2022): 1–7. http://dx.doi.org/10.29292/jics.v17i1.574.

Full text

Abstract:

Operational Transconductance Amplifiers (OTAs) are essential building blocks in analog circuits. Since the early years of integrated circuit science, OTAs have been used in industry and researched in academia. Over the years, a number of techniques and approaches to OTA design have been observed in the literature. With this systematic review, we aim to provide a overview of top journal papers published from 2017 to 2021 containing OTA design. In our investigation we initially found 128 manuscripts and 24 primary studies of OTA design. A set of 10 different techniques have been found. Furthermore, we also evaluate used technology, inversion level and characterization process. With this study we contribute to highlight recent OTA design innovations.

APA, Harvard, Vancouver, ISO, and other styles

50

Asghar, Malik Summair, Saad Arslan, and Hyungwon Kim. "A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits." Sensors 21, no. 13 (June 29, 2021): 4462. http://dx.doi.org/10.3390/s21134462.

Full text

Abstract:

To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation.

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Analog CMOS integrated circuits'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles