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Dissertations / Theses on the topic 'Analog Devices'
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Neugebauer, Charles F. Yariv Amnon Yariv Amnon. "Parallel analog computation with charge coupled devices /." Diss., Pasadena, Calif. : California Institute of Technology, 1993. http://resolver.caltech.edu/CaltechETD:etd-08312007-094832.
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Liesk, André. "Porting eCos to the Analog Devices BLACKfin DSP." Master's thesis, Universitätsbibliothek Chemnitz, 2006. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200602009.
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This thesis covers the work to combine the two worlds of the hardware platform of the
BLACKfin by Analog Devices and the software based on the eCos operating system to
provide a foundation for embedded real-time applications to build on to benefit from the
best aspects of both. This document will therefore outline the main objectives of this thesis
followed by an overview of the functionality provided by eCos and the BLACKfin.
It will further outline the steps required to combine both by porting the hardware
abstraction layer and device drivers for the BLACKfin architecture to eCos.
Prior to detailing selected implementations of particular code segments of special interest
this thesis will outline the design and concept considerations involved and the conclusion
drawn in order to provide a working HAL. After describing the current state of the hardware
abstraction layer port conducted as part of this thesis this document will provide an
evaluation of the implementation itself the benefits as well as possible limitations.
To provide a conclusion to the work outlined in this document further possible questions of
interest for future work based on the results of this thesis will be provided.
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Pansare, Manoj M. "Modeling and simulation of analog devices using PRECISE." Thesis, Virginia Tech, 1988. http://hdl.handle.net/10919/43263.
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The design and development of computer models to simulate analog devices and their effects on circuit applications has been investigated at length. The focus of this research is the development of theoretical and computer models for discrete devices using the popular simulator PRECISE, PRogram for Evaluating Circuits in an Interactive Simulation Environment [3], using a new method for model construction.
This new method develops a model approximating the mathematics of the simulation via perturbations and iterations [19]. The models developed by the new method in each case yield a minimum simulation accuracy of 90 percent in circuit applications. In comparison, models developed by the conventional method, which uses measured data to complete physical constructs of SPICE 2G.6 [5], offer a lower accuracy for the same circuits. Hence, the new method is more effective than the old method and also much faster, since the model generation process is now automated and does not require time-consuming manual measurements and calculations spread out over a long period of time.
With further development, a computer model can also be developed for the theoretical model presented in this thesis for the Gallium Arsenide Metal Semiconductor Field Effect Transistor (GaAs MESFET) device using the same methodology that has been used to develop the computer model for the Bipolar Junction Transistor (BUT) device. Hence this research, in addition to developing a library of a hundred and fifty odd successful models in the PRECISE and SPICE formats for the diode and BUT, can also be used to develop a new model for the GaAs MESFET, which would make both PRECISE and SPICE easier and more user friendly as circuit simulators.Master of Science
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Mohdzaini, Jefri 1976. "The characterization of the Analog Devices Inc. (ADI) magnetometer." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86535.
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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.Includes bibliographical references (leaves 45-46).
by Jefri Mohdzaini.
M.Eng.
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Lee, Frank 1975. "Physical manifestation of NP-completeness in analog computer devices." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80096.
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Song, Jinxin. "Ultra low power Analog-to-Digital Converter for Biomedical Devices." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-44790.
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The biomedical devices often operate only with a battery, e.g., blood glucose monitor, pacemaker. Therefore, it is desirable to fully utilize the energy without sacrificing the performance of the system. The Analog-to-Digital Converter (ADC), as a key component of most of the biomedical devices, needs to be designed for minimum power consumption by exploring various techniques from system level to circuit level. In addition, the nature of bio-signal provides more alternatives to reduce the power. In this thesis work, an 8 bit 11 kS/s modified algorithmic analog-to-digital converter for biomedical applications is proposed. All analog components are designed at circuit level using a 90 nm CMOS technology and digital components are implemented using Verilog-A language in Cadence. The ADC is operating in current mode at sub-threshold region with only 0.5 V supply voltage with an input current from 0 nA to 512 nA. The ADC is designed based on a top-down design with bottom-up verification approach. The system level model is described using top level language and then the circuit level is created and verified using Cadence tools according to the system level model. The INL and DNL obtained from simulation is -1/+0.8 LSB and -0.9/+1 LSB respectively. The SNDR is 47 dB (7.5 ENOB) for a -0.2 dBFS at 1 kHz sinusoidal signal. The power consumption is 2.83 μW without biasing and 4μW with biasing.
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Yoon, Kwang Sub. "A precision analog small-signal model for submicron MOSFET devices." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/14935.
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Killens, Jacob. "Utilizing standard CMOS process floating gate devices for analog design." Master's thesis, Mississippi State : Mississippi State University, 2001. http://library.msstate.edu/etd/show.asp?etd=etd-04092001-110957.
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Daggett, Josephine Anne. "Theoretical investigation of carbon nanotube devices for millimeter/submillimeter wave analog circuits." Thesis, Montana State University, 2009. http://etd.lib.montana.edu/etd/2009/daggett/DaggettJ1209.pdf.
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Carbon nanotubes have become a very exciting area of research in the field of nanoelectronics in the past few years. Diodes and transistors fabricated using carbon nanotubes are theoretically very promising. Although, experimentally these devices are challenging to successfully realize it is hoped that further research and improvements in fabrication procedures will yield devices which could match or surpass current CMOS technologies. However, there are still many areas that need to be improved before anyone sees these devices mass produced commercially. This thesis gives a detailed overview of the fundamentals of these devices which can be easily understood by someone with a typical electrical engineering background. The purpose of this thesis is to investigate both the theory behind these devices and to conduct a series of simulations in order to determine how they compare to ultimately scaled CMOS for high frequency applications by ignoring the challenges associated with fabricating these devices reliably. In other words, at best how could these devices perform if they could be mass produced with high yield compared to current technologies? First an introduction to carbon nanotubes and a review of relevant concepts from solid-state electronics will be given, followed by a brief overview of quantum theory for 1-D systems as it pertains to nanotube based electronics. This will then be used to develop models for a Schottky diode and Schottky barrier transistor. Simulations using these models were conducted that show the potential for these devices for high frequency electronics. These results are subsequently used to compare to current state-of-the-art technologies. Upon completion of the simulations in this thesis, it was determined that carbon nanotube based Schottky diodes and Schottky barrier transistors do not perform as well as current technologies in relation to applications for submillimeter/millimeter wave detection and analog circuits, even when assuming no limitations imposed due to poor fabrication.
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Gurary, Jonathan Gurary. "Improving the Security of Mobile Devices Through Multi-Dimensional and Analog Authentication." Cleveland State University / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=csu1521564381685222.
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Gutiérrez, Campo Ana María. "Development of integrated silicon photonics modulation devices for digital and analog applications." Doctoral thesis, Universitat Politècnica de València, 2013. http://hdl.handle.net/10251/33330.
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Silicon photonics is one of the most exciting and fastest growing photonic technologies
in recent years. The salient feature of this technology is its compatibility with the
mature silicon IC manufacturing based on complementary metal-oxide semiconductor
(CMOS) processes widely used in microelectronic industry. Another motivation is the
availability of high-quality silicon-on-insulator (SOI) planar waveguide circuits that
offer strong optical confinement due to the high index contrast between silicon (n=3.45)
and SiO2 (n=1.45). This opens up miniaturization and very large scale integration of
photonic devices allowing photonic integrated circuits for a wide range of applications
and markets, from optical telecommunications to bio-photonic devices or precise fibre
sensors. Optical modulators are key building-blocks for high speed signal transmission
and information processing in any photonic interconnection solution. The work
developed in this thesis, as part of the objectives of the European project HELIOS in
which it is framed, is essentially focused on realizing compact and efficient modulators
integrated on silicon chips.
The thesis consists of three main chapters as well as the concluding section on the
work accomplished. Chapter one is aimed at giving a general description of the benefits
of using silicon photonics, showing its challenges and opportunities as well as at giving
a deeply overview of all issues related to the electro-optic modulation. Chapter two is
devoted to develop silicon modulators with high features for digital applications.
Specifically, new optical structures different to the conventional ones are presented with
the aim of enhancing the modulation performance or at least several critical parameters
in the modulation. Chapter three is dedicated to the analog applications. The concept of
microwave photonics is described as well as different researches carried out in the
analog scope for application in the field of integrated microwave photonics, all of them
using CMOS-compatible electro-optic silicon modulators which validate the potential of
silicon photonics as a promising approach for enabling the development of integrated
microwave photonics applications. Finally, conclusions on the work realized are
provided in Chapter 4.La fotónica de silicio es una de las tecnologías fotónicas que está experimentando un crecimiento más excitante y rápido en los últimos años. La característica más destacada de esta tecnología es su compatibilidad con las maduras técnicas de fabricación de circuitos integrados de silicio basadas en los procesos ¿complementary metal-oxide semiconductor¿ (CMOS) ampliamente utilizados en la industria microelectrónica. Otra motivación es la disponibilidad de circuitos de guía de ondas planas de silicio sobre aislante (SOI) de alta calidad que ofrecen un fuerte confinamiento óptico debido al alto contraste índices entre el silicio (n=3,45) y el SiO2 (n = 1,45). Esto abre las puertas a la miniaturización y a la integración a gran escala de dispositivos fotónicos lo que resulta en circuitos fotónicos integrados para una amplia gama de aplicaciones y mercados, desde telecomunicaciones ópticas a dispositivos bio-fotónicos o sensores de fibra precisos. Los moduladores ópticos son elementos básicos fundamentales para la transmisión de señales a alta velocidad y el procesado de información en cualquier solución de interconexión fotónica. El trabajo desarrollado en esta tesis, como parte del los objetivos del proyecto Europeo HELIOS en el que está enmarcada, se centra fundamentalmente en realizar moduladores compactos y eficientes, integrados en chips de silicio. La tesis consiste en 3 capítulos principales así como una sección de conclusiones del trabajo conseguido. El capítulo uno está destinado a dar una descripción general de los beneficios del uso de la fotónica de silicio, mostrando sus retos y oportunidades, así como a dar una visión profunda de todos los aspectos relacionados con la modulación electro-óptica. El capítulo dos está dedicado a desarrollar moduladores de silicio de altas prestaciones para aplicaciones digitales. Específicamente, se presentan nuevas estructuras ópticas diferentes a las convencionales con el objetivo de mejorar el rendimiento de la modulación o al menos algunos parámetros críticos en la modulación. El tercer capítulo se dedica a las aplicaciones analógicas. Se describe el concepto de la fotónica de microondas, así como diferentes investigaciones llevadas a cabo en el ámbito analógico para su aplicación en el campo de la fotónica integrada de microondas, todas ellas usando moduladores electro-ópticos de silicio compatibles con los procesos de fabricación CMOS, lo que valida el potencial de la fotónica de silicio como un prometedor enfoque para permitir el desarrollo de aplicaciones de la fotónica integrada de microondas. Por último, las conclusiones sobre el trabajo realizado se proporcionan en el Capítulo 4.
Gutiérrez Campo, AM. (2013). Development of integrated silicon photonics modulation devices for digital and analog applications [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/33330
TESIS
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Kathuria, Amit D. "Optical pulse generation at high pulse rates for electro-optical analog to digital converters /." free to MU campus, to others for purchase, 2004. http://wwwlib.umi.com/cr/mo/fullcit?p1426072.
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Schlottmann, Craig Richard. "Analog signal processing on a reconfigurable platform." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29623.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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ROTA, LUCIANO. "Implementation and Validation Methods for Electronic Integrated Circuits and Devices." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2023. https://hdl.handle.net/10281/404776.
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Negli ultimi tre decenni l'elettronica delle telecomunicazioni mobili ha subito un grande miglioramento, questo ramo dell'elettronica si è rivelato una delle principali forze trainanti nello sviluppo delle nuove tecnologie CMOS. in tutto il mondo richiedono dispositivi portatili estremamente performanti, più veloci, più affidabili, a basso consumo energetico.
Questa situazione è diventata estremamente favorevole per lo sviluppo di dispositivi digitali ad alte prestazioni in grado di raggiungere velocità e capacità di memoria prima incredibili. Anche i blocchi di costruzione analogici devono essere integrati in nodi profondamente ridimensionati, al fine di adattarsi ai circuiti integrati digitali . Il primo compito di questo lavoro di tesi è stata l'implementazione e la misurazione di diversi circuiti integrati in due nodi tecnologici profondamente scalati come CMOS bulk a 28 nm e FinFET (Fin Field Effect Transistor) a 16 nm. In particolare, il secondo di questi introduce novità sulla struttura del transistor utilizzato per implementare i circuiti. Ciascun circuito realizzato incontra diverse difficoltà dovute al particolare comportamento di tali tecnologie avanzate, in particolare in termini di basso intrinsic gain e basso output voltage swing come conseguenza della bassa tensione di alimentazione.
Ho lavorato nel progetto FinFET16 con il compito principale di realizzare e validare il layout di un filtro analogico Super-Source-Follower fully-differential del 4° ordine. Dopo le misurazioni, il filtro raggiunge 15,1 dBm IIP3 in banda a 10 MHz e toni di ingresso 11 MHz, con un consumo energetico di 968 µW da una singola tensione di alimentazione da 1 V. Il rumore integrato in banda è 85,78 µVrms per una figura di merito complessiva di 162,8 dB (j-1) che supera lo stato dell'arte dei filtri analogici.
Ho anche collaborato come layoutista in altri due progetti realizzati con tecnologia CMOS a 28 nm. Il primo è stato il progetto PRIN Brain28nm che riguarda l'implementazione di una catena di acquisizione del segnale neurale. L'obiettivo di questo lavoro era la realizzazione di un biosensore che utilizza la struttura EOMOSFET con il nodo tecnologico CMOS a 28 nm. L'utilizzo di questa tecnologia rende questo circuito più competitivo rispetto ai biosensori presenti in letteratura. L'ultimo progetto è stato il progetto Pignoletto realizzato in collaborazione con RedCat Devices. Esso riguarda l'implementazione e l'analisi teorica di due diverse tipologie di circuiti integrati misurati sotto irraggiamento: due celle digitali e un convertitore da analogico a digitale.
Nella seconda parte del mio terzo anno ho iniziato un'attività lavorativa presso la sede di Pavia della AMS come validation engineer. Questa azienda è leader mondiale nel campo dell'Automotive Interior Lightning. ll progetto che sto portando avanti prevede la realizzazione di un setup di validazione per un IC, al fine di verificare il corretto svolgimento delle molteplici funzioni per le quali questo chip è progettato.
Una prima analisi, utile allo studio preliminare per la realizzazione del setup, è stata effettuata attraverso l'utilizzo di un FPGA su cui è stato caricato il codice che realizza la parte logica dell'IC utilizzando il software Quartus. Una volta validato il corretto funzionamento dell'FPGA, attraverso l'utilizzo di un microcontrollore STM32, sono state testate e correttamente validate diverse configurazioni e funzioni. Lo scopo finale di questa attività, che proseguirà nei prossimi mesi, è la validazione di alcune modalità di comunicazione tra diversi dispositivi, fondamentali per l'interfaccia dell'IC con gli standard automotive, e la creazione di una versione aggiornata del codice FPGA e della sua successiva verifica. Questa attività sembra essere una novità nel campo del design di circuiti integrati perché potrebbe permettere di evidenziare eventuali problemi.In the last three decades Mobile Telecommunication (TLC) electronics has undergone a great improvement, this limited branch of electronics proved to be one of the major driving motor in the development of the new Complementary Metal-Oxide-Semiconductor (CMOS) technologies. People all around the world ask for extremely performing portable devices, faster, more reliable, low power consuming and with impressive memory capability. This situation has become extremely favorable for the development of high performance digital devices which are able to reach speed and memory capability previously unbelievable. Also analog building blocks must be integrated in deeply down-scaled node, in order to adapt with digital integrated circuits (ICs). First task of this thesis work was the implementation and measurement of different integrated circuits in two deep sub-micron technology nodes as 28nm bulk-CMOS and 16nm FinFET (Fin Field Effect Transistor). In particular the second one of these introduces novelty about the structure of transistor used to implement the circuits. Each circuit created faces various difficulties due to the particular behaviour of such advanced technologies, in particular in terms of low intrinsic gain and limited signal swing as consequence of low supply voltage. I worked in FinFET16 project with the main task to realize and validate the layout of a 4^th Order Fully-Differential Super-Source-Follower Analog Filter. After measurements the filter achieves 15.1 dBm in-band IIP3 at 10 MHz & 11 MHz input tones, with 968 µW power consumption from a single 1V supply voltage. In-band integrated noise is 85.78 µVrms for an overall Figure-of-Merit of 162.8 dB (j-1) which outperforms analog filters State-of-the-Art. I also collaborated as layoutist in other two projects realized with 28nm CMOS technology. The first one was the PRIN Brain28nm project that concerns the implementation of a neural signal acquisition chain. The goal of this work was the realization of a biosensor that uses the EOMOSFET structure with the 28nm CMOS technological node. The use of this technology makes this circuit more competitive when compared to the biosensors present in literature. The last one was Pignoletto project realized in collaboration with RedCat Devices. It concerns the implementation and theorical analysis of two different typologies of ICs measured under radiation: two digital cells and one Analog to Digital Converter. Under radiation measurements will be realize in January 2023. In the second part of my third year I started a work activity in Pavia site of AMS-Osram S.r.l as validation engineer. This company is a world leader in the field of optical sensors and the application of the latter in the automotive sector. The project I am carrying out involves the creation of a validation setup for an IC, in order to verify the correct performance of the multiple functions for which this chip is designed. A first analysis, useful for the preliminary study for the realization of the setup, was carried out through the use of an FPGA (Cyclone1000) on which the code that realizes the logic part of the IC was loaded using the Quartus software. Once the correct operation of the FPGA was validated, through the use of an STM32 micro-controller, various configurations and functions have been tested and correctly validated. The final purpose of this activity, which will continue in the coming months, is the validation of some communication methods between different devices, fundamental for the interface of the IC with automotive standards, and the creation of an updated version of the FPGA code and its subsequent verification. This activity appears to be a novelty in the field of integrated circuit design as it would allow to highlight problems and malfunctions of the circuit.
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Hayashi, Takayuki. "A 1 V floating-point analog-to-digital converter for portable communication devices." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0005/MQ45436.pdf.
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Peng, Sheng-Yu. "Charge-based analog circuits for reconfigurable smart sensory systems." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29655.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Degertekin, F.; Committee Member: Ghovanloo, Maysam; Committee Member: Minch, Bradley. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Young, Forrest C. "Phoenix autonomous underwater vehicle (AUV) : networked control of multiple analog and digital devices using LonTalk /." Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1997. http://handle.dtic.mil/100.2/ADA342308.
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Thesis (M.S. in Electrical Engineering)) Naval Postgraduate School, December 1997."December 1997." Thesis advisor(s): Xiaoping Yun, Don Brutzman. DTIC Descriptors: Underwater Vehicles, Autonomous Navigation, Digital Communications, Signal Processing, Robotics, Real Time, Robots, Computer Architecture, Theses, Analog to Digital Converters, Digital To Analog Converters. Author(s) subject terms: Autonomous Underwater Vehicle, AUV, Networked Control, Lon Works Technology, LonTalk, LonBuilder. Includes bibliographical references (p. 93-94). Also available online.
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Twetman, Theodor. "Multi View Image Stitching of Planar Surfaces on Mobile Devices : Large Surface Analog Notes Scanning." Thesis, KTH, Robotik, perception och lärande, RPL, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-196554.
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Digital notes have numerous advantages compared to analog notes, yet the will to use pen and paper remains. Thus, a need to digitize handwritten notes arises. To make it as simple as possible a minimum amount of user interaction should be required. The aim of this project is to present a process of automated image capturing, followed by a process of automatic image stitching, given photos taken by a camera which is moved parallel to a whiteboard or similar planar scenery. The need stems from being able to obtain higher image quality than possible using only one overall picture. The processes is to be executed on mobile devices, with comparatively low computational capacity, within a reasonable time interval. A review and theoretical analysis is conducted of existing methods for all parts of the processes: automated image capturing, registration, reprojection and blending. The methods considered appropriate for further use are evaluated in the form of a series of tests developed for the purpose with focus on the balance between robustness, which ultimately means visual accuracy in the final image, and computation intensity. The techniques evaluated are based on feature points which are used to calculate a transformation homography. Also, two new techniques are presented and evaluated. One for finding features in the form of corners by approximating shapes into polygons. The other method is used to speed up the image matching process from a camera feed towards a given image by reducing the search space by using the former transient image from the camera feed. The results show that it is feasible to assemble correct image compositions despite that the intended sceneries often contain few features; a bigger problem is that they often are poorly distributed. The difference in quality between the corresponding evaluated techniques is small in comparison to the speed differences. With a combination of fast algorithms, including the proposed speed up, it is possible to achieve a holistic process working viable on standard mobile devices. To optimize the stitching process an alternative method is proposed utilising dynamic criteria for when a new image should be stored during the automated capturing.Digitala anteckningar har flera fördelar gentemot analoga, men viljan att använda penna och papper kvarstår. Därmed uppkommer ett behov av att digitalisera handskrivna anteckningar. För att det ska vara så enkelt som möjligt är målet minsta möjliga antal interaktioner med användaren. Syftet med projektet är att presentera en process för automatiserad bildtagning för bilder tagna av en kamera som flyttas parallellt med en whiteboardtavla, eller liknande scenbild, följt av en process för automatisk sammanfogning av dessa bilder. Problemet ligger i behovet av att få högre kvalitet i den slutgiltiga bilden än vad som är möjligt med enbart en övergripande bild. Processerna ska exekveras på mobila enheter, med jämförelsevis låg beräkningskapacitet, inom ett rimligt tidsintervall. En genomgång och teoretisk analys utförs av befintliga metoder för alla delar av processen: automatiserad bildtagning, registrering, omprojecering samt färgutjämning. De metoder som bedöms ändamålsenliga utvärderas vidare i form av en serie tester utvecklade för ändamålet där fokus ligger på avvägningen mellan robusthet, vilket i förlängningen innebär visuell korrekthet i den slutgiltiga bilden, samt beräkningsintensitet. Teknikerna som utvärderas baseras på intressepunkter vilka används för att beräkna en omvandlingshomografi. Även två nya tekniker presenteras och utvärderas. Den ena för att hitta intressepunkter i form av hörn genom att approximera former till polygoner. Den andra metoden används för att snabba upp matchningsprocessen från ett kameraflöde mot en given bild genom att minska sökrymden med hjälp av föregående bild från kameraflödet. Resultaten visar att det är möjligt att foga samman korrekta bildkompositioner trots att de avsedda scenbilderna ofta innehåller få intressepunkter; ett större problem är att de ofta har dålig spridning. Skillnaden i bildkvalitet mellan de utvärderade teknikerna är små i jämförelse med hastighetsskillnaderna. Med en kombination av snabba algoritmer, inklusive den föreslagna uppsnabbningen, är det möjligt att åstadkomma en helhetsprocess som fungerar dugligt på vanliga mobila enheter. För att optimera bildsammanfogningen föreslås en alternativ metod med dynamiska kriterier för när en ny bild ska sparas under den automatiserade bildtagningen.
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Hansen, Mirko [Verfasser]. "On the development of memristive devices for electroforming-free and analog memristive crossbar arrays / Mirko Hansen." Kiel : Universitätsbibliothek Kiel, 2018. http://d-nb.info/1167770986/34.
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Damkjer, Kristian Linn. "Architecting RUBE worlds a methodology for creating virtual analog devices as metaphorical representations of formal systems /." [Gainesville, Fla.] : University of Florida, 2003. http://purl.fcla.edu/fcla/etd/UFE0000670.
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Ramasamy, Lakshminarayanan. "First Order Mobility Independent ASIC for a Point-of-Care In-Vitro Diagnostic Device." University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1326296847.
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Greenlee, Jordan Douglas. "Study of cation-dominated ionic-electronic materials and devices." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53401.
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The memristor is a two-terminal semiconductor device that is able to mimic the conductance response of synapses and can be utilized in next-generation computing platforms that will compute similarly to the mammalian brain. The initial memristor implementation is operated by the digital formation and dissolution of a highly conductive filament. However, an analog memristor is necessary to mimic analog synapses in the mammalian brain. To understand the mechanisms of operation and impact of different device designs, analog memristors were fabricated, modeled, and characterized. To realize analog memristors, lithiated transition metal oxides were grown by molecular beam epitaxy, RF sputtering, and liquid phase electro-epitaxy. Analog memristors were modeled using a finite element model simulation and characterized with X-ray absorption spectroscopy, impedance spectroscopy, and other electrical methods. It was shown that lithium movement facilitates analog memristance and nanoscopic ionic-electronic memristors with ion-soluble electrodes can be key enabling devices for brain-inspired computing.
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Imam, Neena. "Analysis, design, and testing of semiconductor intersubband devices." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15664.
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Chang, Jae Joon. "CMOS differential analog optical receivers with hybrid integrated I-MSM detector." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/14998.
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Zhang, Dai. "Design of Ultra-Low-Power Analog-to-Digital Converters." Licentiate thesis, Linköpings universitet, Elektroniska komponenter, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79276.
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Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, typically requirelow-speed, medium-resolution ADCs. The successive approximation register (SAR) ADC exhibits significantly high energy efficiency compared to other prevalent ADC architectures due to its good tradeoffs among power consumption, conversion accuracy, and design complexity. To design an energy-efficient SAR ADC, an understanding of its error sources as well as its power consumption bounds is essential. This thesis analyzes the power consumption bounds of SAR ADC: 1) at low resolution, the power consumption is bounded by digital switching power; 2) at medium-to-high resolution, the power consumption is bounded by thermal noise if digital assisted techniques are used to alleviate mismatch issues; otherwise it is bounded by capacitor mismatch. Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. It is not straightforward to effectively reduce the unnecessary speed for lower power consumption using inherently fast components in advanced CMOS technologies. Moreover, the leakage current degrades the sampling accuracy during the long conversion time, and the leakage power consumption contributes to a significant portion of the total power consumption. Two SAR ADCs have been implemented in this thesis. The first ADC, implemented in a 0.13-µm CMOS process, achieves 9.1 ENOB with 53-nW power consumption at 1 kS/s. The second ADC, implemented in a 65-nm CMOS process, achieves the same resolution at 1 kS/s with a substantial (94%) improvement in power consumption, resulting in 3-nW total power consumption. Our work demonstrates that the ultra-low-power operation necessitates maximum simplicity in the ADC architecture.
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Leung, Matthew Chung-Hin. "CMOS RF SOC Transmitter Front-End, Power Management and Digital Analog Interface." Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24664.
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With the growing trend of wireless electronics, frequency spectrum is crowded with different applications. High data transfer rate solutions that operate in license-exempt frequency spectrum range are sought. The most promising candidate is the 60 GHz multi-giga bit transfer rate millimeter wave circuit. In order to provide a cost-effective solution, circuits designed in CMOS are implemented in a single SOC.
In this work, a modeling technique created in Cadence shows an error of less than 3dB in magnitude and 5 degree in phase for a single transistor. Additionally, less than 3dB error of power performance for the PA is also verified. At the same time, layout strategies required for millimeter wave front-end circuits are investigated. All of these combined techniques help the design converge to one simulation platform for system level simulation.
Another aspect enabling the design as a single SOC lies in integration. In order to integrate digital and analog circuits together, necessary peripheral circuits must be designed. An on-chip voltage regulator, which steps down the analog power supply voltage and is compatible with digital circuits, has been designed and has demonstrated an efficiency of 65 percent with the specific area constraint. The overall output voltage ripple generated is about 2 percent.
With the necessary power supply voltage, gate voltage bias circuit designs have been illustrated. They provide feasible solutions in terms of area and power consumption. Temperature and power supply sensitivities are minimized in first two designs. Process variation is further compensated in the third design. The third design demonstrates a powerful solution that each aspect of variations is well within 10%.
As the DC conditions are achieved on-chip for both the digital and analog circuits, digital and analog circuits must be connected together with a DAC. A high speed DAC is designed with special layout techniques. It is verified that the DAC can operate at a speed higher than 3 Gbps from the pulse-shaping FIR filter measurement result.
With all of these integrated elements and modeling techniques, a high data transfer rate CMOS RF SOC operating at 60 GHz is possible.
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Зубков, О. В., І. В. Свид, О. С. Мальцев, and Л. Ф. Сайківська. "In-circuit Signal Analysis in the Development of Digital Devices in Vivado 2018." Thesis, Theoretical and Applied Aspects of Device Development on Microcontrollers and FPGAs, MC&FPGA-2019, 2019. https://doi.org/10.35598/mcfpga.2019.003.
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Considered the implementation of in-circuit analysis of logical signals in digital devices synthesized in Xilinx Field-Programmable Gate Array. Designed a digital control device streaming analog-to-digital converter. An analysis of the results of the analog-digital conversion was carried out and measures were taken to smooth out the false results of the conversion.
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Зубков, О. В., І. В. Свид, О. С. Мальцев, and Л. Ф. Сайківська. "In-circuit Signal Analysis in the Development of Digital Devices in Vivado 2018." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-003.
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Considered the implementation of in-circuit analysis of logical signals in digital devices synthesized in Xilinx Field-Programmable Gate Array. Designed a digital control device streaming analog-to-digital converter. An analysis of the results of the analog-digital conversion was carried out and measures were taken to smooth out the false results of the conversion.
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Yoo, Heejong. "Low-Power Audio Input Enhancement for Portable Devices." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6821.
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With the development of VLSI and wireless communication
technology, portable devices such as personal digital assistants
(PDAs), pocket PCs, and mobile phones have gained a lot of
popularity. Many such devices incorporate a speech recognition
engine, enabling users to interact with the devices using
voice-driven commands and text-to-speech synthesis.
The power consumption of DSP microprocessors has been
consistently decreasing by half about every 18 months, following
Gene's law. The capacity of signal processing, however, is still
significantly constrained by the limited power budget of these
portable devices. In addition, analog-to-digital (A/D) converters
can also limit the signal processing of portable devices. Many
systems require very high-resolution and high-performance A/D
converters, which often consume a large fraction of the limited
power budget of portable devices.
The proposed research develops a low-power audio signal
enhancement system that combines programmable analog signal
processing and traditional digital signal processing. By
utilizing analog signal processing based on floating-gate
transistor technology, the power consumption of the overall
system as well as the complexity of the A/D converters can be
reduced significantly. The system can be used as a front end of
portable devices in which enhancement of audio signal quality
plays a critical role in automatic speech recognition systems on
portable devices. The proposed system performs background audio
noise suppression in a continuous-time domain using analog
computing elements and acoustic echo cancellation in a
discrete-time domain using an FPGA.
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Lu, Dongtian. "High speed CMOS ADC for UWB receiver /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LUD.
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Gray, Jordan D. "Application of Floating-Gate Transistors in Field Programmable Analog Arrays." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7540.
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Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design that FPGAs have had on digital design. In my research, I investigate the areas floating-gate transistors can be used to impact FPAA design and implementation.
An FPAA can be broken up into two basic components, elements of connection and elements of computation. With respect to connection, I show that a floating-gate switch can be used in a cross-bar matrix in place of a transmission gate resulting in less parasitic capacitance and a more linear resistance for the same size transistor. I illuminate the programming issues relating to injecting a floating-gate for use as a switch, including the drain selection circuitry and rogue injection due to gate induced drain leakage. With respect to computation, I explain how a Multiple-Input Translinear Element, or MITE, can be augmented to fit in an FPAA framework. I also discuss two different MITE implementations compatible with CMOS technology, a subthreshold MOS design and a BJT MITE that uses a lateral BJT.
Beyond FPAA components, I present two alternative FPAA systems. The first is a general purpose reconfigurable analog system that uses standard analog design components that have been augmented with floating-gates. The second FPAA is built upon MITE circuits, and is focused on supporting direct system synthesis. I conclude with a discussion of a future large-scale MITE FPAA.
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Pant, Sanjiv Nath. "An Ion Detection Scheme Employing Solid State Devices for Use in Portable Mass Spectrometers." BYU ScholarsArchive, 2016. https://scholarsarchive.byu.edu/etd/6597.
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This thesis presents a solid state approach to the ion detection system used in the back-end of modern mass spectrometers. Although various techniques already exist to detect ions – even with the sensitivity of a single particle, the existing techniques require high voltage or lower operation temperature to counteract the noise inherent in the system. The suggested design presents an alternative to the more popular detection system whereby the requirement of high operation voltage or low operation temperature can be precluded. This is made possible through the gate capacitance of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). This thesis presents the design that utilizes the MOSFET as an ion signal amplifier; including the simulation and silicon testbench results.
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Matinpour, Babak. "Design and development of compact and monolithic direct conversion receivers." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14991.
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Levski, Deyan. "Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors." Thesis, University of Oxford, 2018. http://ora.ox.ac.uk/objects/uuid:31b9426f-8a7c-4c86-9471-32431f33ebe7.
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This thesis presents a study on solutions to high-speed analog-to-digital conversion in CMOS image sensors using time-interpolation methods. Data conversion is one of the few remaining speed bottlenecks in conventional 2D imagers. At the same time, as pixel dark current continues to improve, the resolution requirements on imaging data converters impose very high system-level design challenges. The focus of the presented investigations here is to shed light on methods in Time-to-Digital Converter interpolation of single-slope ADCs. By using high-factor time-interpolation, the resolution of single-slope converters can be increased without sacrificing conversion time or power. This work emphasizes on solutions for improvement of multiphase clock interpolation schemes, following an all-digital design paradigm. Presented is a digital calibration scheme which allows a complete elimination of analog clock generation blocks, such as PLL or DLL in Flash TDC-interpolated single-slope converters. To match the multiphase clocks in time-interpolated single-slope ADCs, the latter are generated by a conventional open-loop delay line. In order to correct the process voltage and temperature drift of the delay line, a digital backend calibration has been developed. It is also executed online, in-column, and at the end of each sample conversion. The introduced concept has been tested in silicon, and has showed promising results for its introduction in practical mass-production scenarios. Methods for reference voltage generation in single-slope ADCs have also been looked at. The origins of error and noise phenomenona, which occur during both the discrete and continuous-time conversion phases in a single-slope ADC have been mathematically formalized. A method for practical measurement of noise on the ramp reference voltage has also been presented. Multiphase clock interpolation schemes are difficult for implementation when high interpolation factors are used, due to their quadratic clock phase growth with resolution. To allow high interpolation factors a time-domain binary search concept with error calibration has been introduced. Although the study being conceptual, it shows promising results for highly efficient implementations, if a solution to stable column-level unit delays can be found. The latter is listed as a matter of future investigations.
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Roth, Matthias, Jörg Heber, and Klaus Janschek. "Concept for the fast modulation of light in amplitude and phase using analog tilt-mirror arrays." SPIE, 2017. https://tud.qucosa.de/id/qucosa%3A35124.
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The full complex, spatial modulation of light at high frame rates is essential for a variety of applications. In particular, emerging techniques applied to scattering media, such as Digital Optical Phase Conjugation and Wavefront Shaping, request challenging performance parameters. They refer to imaging tasks inside biological media, whose characteristics concerning the transmission and reflection of scattered light may change over time within milliseconds. Thus, these methods call for frame rates in the kilohertz range. Existing solutions typically offer frame rate capabilities below 100 Hz, since they rely on liquid crystal spatial light modulators (SLMs). We propose a diffractive MEMS optical system for this application range. It relies on an analog, tilt-type micro mirror array (MMA) based on an established SLM technology, where the standard application is grayscale amplitude control. The new MMA system design allows the phase manipulation at high-speed as well.
The article studies properties of the appropriate optical setup by simulating the propagation of the light. Relevant test patterns and sensitivity parameters of the system will be analyzed. Our results illustrate the main opportunities of the concept with particular focus on the tilt mirror technology. They indicate a promising path to realize the complex light modulation at frame rates above 1 kHz and resolutions well beyond 10,000 complex pixels.
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Chiu, Leung Kin. "Efficient audio signal processing for embedded systems." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44775.
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We investigated two design strategies that would allow us to efficiently process audio signals on embedded systems such as mobile phones and portable electronics. In the first strategy, we exploit properties of the human auditory system to process audio signals. We designed a sound enhancement algorithm to make piezoelectric loudspeakers sound "richer" and "fuller," using a combination of bass extension and dynamic range compression. We also developed an audio energy reduction algorithm for loudspeaker power management by suppressing signal energy below the masking threshold. In the second strategy, we use low-power analog circuits to process the signal before digitizing it. We designed an analog front-end for sound detection and implemented it on a field programmable analog array (FPAA). The sound classifier front-end can be used in a wide range of applications because programmable floating-gate transistors are employed to store classifier weights. Moreover, we incorporated a feature selection algorithm to simplify the analog front-end. A machine learning algorithm AdaBoost is used to select the most relevant features for a particular sound detection application. We also designed the circuits to implement the AdaBoost-based analog classifier.
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Odame, Kofi. "Exploiting device nonlinearity in analog circuit design." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29751.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Butera, Robert; Committee Member: Minch, Bradley; Committee Member: Taylor, David. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Vigraham, Saranyan A. "An Analog Evolvable Hardware Device for Active Control." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1195506953.
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Bee, Sarah Caroline. "Radiation effects in analogue to digital converters." Thesis, University College London (University of London), 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.298887.
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Walton, Emma Jayne. "The physics of analogue smectic devices." Thesis, University of Exeter, 2000. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.531673.
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Bhatta, Sambasiva R. "Model-based analogy in innovative device design." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/8136.
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Byun, Albert Joon-Soo. "Analog signal conditioning design for a wireless data acquisition device." Connect to this title online, 2005. http://hdl.handle.net/1811/368.
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Thesis (Honors)--Ohio State University, 2005.Title from first page of PDF file. Document formattted into pages: contains v, 28 p.; also includes graphics. Includes bibliographical references (p. 21-22). Available online via Ohio State University's Knowledge Bank.
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Gedra, David R. "Design of a VLSI charge-coupled device analog delay line." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1995. http://handle.dtic.mil/100.2/ADA296475.
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Clegg, Kester Dean. "Evolving gene expression to reconfigure analogue devices." Thesis, University of York, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.479503.
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Penrod, Logan B. "An Exploratory Study of Pulse Width and Delta Sigma Modulators." DigitalCommons@CalPoly, 2020. https://digitalcommons.calpoly.edu/theses/2278.
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This paper explores the noise shaping and noise producing qualities of Delta-Sigma Modulators (DSM) and Pulse-Width Modulators (PWM). DSM has long been dominant in the Delta Sigma Analog-to-Digital Converter (DSADC) as a noise-shaped quantizer and time discretizer, while PWM, with a similar self oscillating structure, has seen use in Class D Power Amplifiers, performing a similar function. It has been shown that the PWM in Class D Amplifiers outperforms the DSM [1], but could this advantage be used in DSADC use-cases? LTSpice simulation and printed circuit board implementation and test are used to present data on four variations of these modulators: The DSM, PWM, the out-of-loop discretized PWM (OOLDP), and the cascaded modulator. A generic form of an Nth order loop filter is presented, where three orders of this generic topology are analyzed in simulation for each modulator, and two orders are used in physical testing.
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Joly, Yohan. "Etude des fluctuations locales des transistors MOS destinés aux applications analogiques." Thesis, Aix-Marseille 1, 2011. http://www.theses.fr/2011AIX10138/document.
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Les fluctuations électriques des composants sont une limitation à la miniaturisation des circuits. Malgré des procédés de fabrications en continuelle évolution, les variations des caractéristiques électriques dues au désappariement entre deux dispositifs limitent les performances des circuits. Concernant les applications à faible consommation, ces fluctuations locales peuvent devenir très critiques. Dans le contexte du développement d’une technologie CMOS 90nm avec mémoire Flash embarquée pour des applications basse consommation, l’appariement de transistors MOS est étudié. Une analyse de l’impact du dopage de grille des transistors NMOS est menée. L’étude se focalise sur l’appariement en tension des paires différentielles polarisées dans la zone de fonctionnement sous le seuil. Il est démontré que cet appariement peut être dégradé à cause de l’effet « hump », c'est-à-dire la présence de transistors parasites en bord d’active. Un macro-modèle permettant aux concepteurs de modéliser cet effet est présenté. Il est étudié au niveau composant, au niveau circuit et en température. Enfin, une étude de la dégradation de l’appariement des transistors MOS sous stress porteurs chauds est réalisée, validant un modèle de dégradation. Des transistors octogonaux sont proposés pour supprimer l’effet « hump » et donnent d’excellents résultats en termes d’appariement ainsi qu’en fiabilitéElectrical fluctuations of devices limit chip miniaturization. Despite manufacturing processes in continuous evolution, circuit performances are limited by electrical characteristics variations due to mismatch between two devices. Concerning low power applications, local fluctuations can become very critical. In the context of development of a 90nm CMOS technology with Embedded Flash memory for low power applications, MOS transistors matching is studied. A study of NMOS transistors gate doping impact is conducted. Study focuses on voltage matching of differential pairs biased under threshold. It is demonstrated that this matching can be degraded due to « hump » effect, meaning presence of parasitic devices on active edge. A macro-model allowing designers to model this effect is presented. It is studied at device level, circuit level and for different temperatures. Finally, a degradation study of MOS transistors mismatch under Hot Carriers Injection stress is performed, validating a degradation model. Octagonal devices are proposed to suppress « hump » effect and give good results in terms of matching as well as reliability
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Abel, Christopher J. "An investigation of nonideal process and device effects in fundamental CMOS analog subcircuits /." The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487865929454587.
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Svensson, Jesper. "Barn i den digitala världen." Thesis, Blekinge Tekniska Högskola, Institutionen för teknik och estetik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-14627.
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Detta kandidatarbete handlar om hur skolan arbetar med digitaliseringen och hur de använder de digitala verktyg som finns. Det kommer handla om de övergångar digitaliseringen innebär för skolan och vad som kan vara hinder för skolan att digitaliseras. Kandidatarbetet kommer också ta upp vikten av vuxnas närvaro för de barnen som använder internet och blivit upprörda/besvärade av något som det sätt på internet. Den gestaltande delen av kandidatarbetet kommer att handla om barn som ännu inte börjat skolan. Barnen kommer att hjälpa till för att skapa sig en egen design på en applikation som de sedan skulle vilja använda. Barns vetskap om hur tekniken används är begränsad på ett positivt sätt som gör att de kan öppna upp för nya sätt att se tekniken. Barnen är villiga att använda tekniken och det spelar ingen roll om det skulle vara på ett papper eller digitalt. De gillar allra bäst närheten till vuxna när de får interagera med det som är framför dem.This Bachelor Thesis is about how the school works with digitalization and how they use the digital tools that are available. It is about the transitions that digitalization faces that could prevent the school from becoming more digitized. The work will also address the importance of adult’s presence for the children's use of the internet and support them if they had a bad experienced on the internet. The output of the Bachelor Thesis will be about children who have not yet started school. The children will help to create their own design on an application that they would like to play with. Children's knowledge of how technology is used is limited in a positive way, that enables them to open up new ways to see the technology. Children are willing to use the technology and it doesn't matter if it is paper or digital. They enjoy the company of grownups when they interact with what's in front of them.
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Feng, Hong. "Impact of atomistic device variability on analogue circuit design." Thesis, University of Glasgow, 2011. http://theses.gla.ac.uk/3074/.
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Scaling of complementary metal-oxide-semiconductor (CMOS) technology has benefited the semiconductor industry for almost half a century. For CMOS devices with a physical gate-length in the sub-100 nm range, extreme device variability is introduced and has become a major stumbling block for next generation analogue circuit design. Both opportunities and challenges have therefore confronted analogue circuit designers. Small geometry device can enable high-speed analogue circuit designs, such as data conversion interfaces that can work in the radio frequency range. These designs can be co-integrated with digital systems to achieve low cost, high-performance, single-chip solutions that could only be achieved using multi-chip solutions in the past. However, analogue circuit designs are extremely vulnerable to device mismatch, since a large number of symmetric transistor pairs and circuit cells are required. The increase in device variability from sub-100 nm processes has therefore significantly reduced the production yield of the conventional designs. Mismatch models have been developed to analytically evaluate the magnitude of random variations. Based on measurements from custom designed test structures, the statistics of process variation can be estimated using design related parameters. However, existing models can no longer accurately estimate the magnitude of mismatch for sub-100 nm “atomistic” devices, since short-channel effects have become important. In this thesis, a new mismatch model for small geometry devices will be proposed to address this problem. Based on knowledge of the matching performance obtained from the mismatch model, design solutions are desired at different design levels for a variety of circuit topologies. In this thesis, transistor level compensation solutions have been investigated and closed-loop compensation circuits have been proposed. At circuit level, a latch-based comparator has been used to develop a compensation solution because this type of comparator is extremely sensitive to the device mismatch. These comparators are also used as the fundamental building block for the analogue-to-digital converters (ADC). The proposed comparator compensation scheme is used to improve the performance of a high-speed flash ADC.
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Rogers, Craig N. "Object-oriented design of an automated calibration system for an analog I/O process control device." [Denver, Colo.] : Regis University, 2006. http://165.236.235.140/lib/CRogers2007.pdf.
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