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Journal articles on the topic 'Analog-digital converter (ADC)'

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Published: 4 June 2021
Last updated: 15 February 2022

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1

Chauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 31, 2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.

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After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.
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Bialek, J., A. Wickmann, F. Ohnhaeuser, G. Fischer, R. Weigel, and T. Ussmueller. "Implementation of a digital trim scheme for SAR ADCs." Advances in Radio Science 11 (July 4, 2013): 227–30. http://dx.doi.org/10.5194/ars-11-227-2013.

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Abstract. Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.
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3

Anvekar, Dinesh K., and B. S. Sonde. "Programmable Nonlinear Adc: An Illustrative Example." International Journal of Electrical Engineering & Education 33, no. 3 (July 1996): 216–24. http://dx.doi.org/10.1177/002072099603300303.

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Programmable nonlinear ADC: an illustrative example Programmable nonlinear analog-to-digital conversion is a new topic in EE curricula. With a view to introducing the EE student to the concept of transfer characteristic programmability of an analog-to-digital converter (ADC), a memory-prefetch programmable nonlinear ADC is presented. The design, analytical evaluation, and experimental implementation for the ADC are described.
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NING, NING, LING DU, HUA CHEN, SHUANGYI WU, QI YU, and YANG LIU. "A DITHERING TECHNIQUE FOR SHA_LESS PIPELINED ADC." Journal of Circuits, Systems and Computers 23, no. 01 (January 2014): 1450006. http://dx.doi.org/10.1142/s0218126614500066.

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A dithering technique for pipelined analog-to-digital converter (ADC) without sample-and-hold amplifier (SHA) is proposed in this paper. The dither signals are injected to the output of the first stage multiplying digital-to-analog converter (MDAC) and the input of the first stage Sub_ADC simultaneously. The equivalent input voltage of the first stage Sub_ADC is consistent with that of the first stage MDAC with dither. To subtract the dither signal precisely, all of the dither signals are quantified by the ADC itself before normal conversion, and the digital codes representing dither signals are stored. During normal conversion, a dither signal selected randomly is added to the analog input and the corresponding digital code is subtracted from the digital output. The proposed dithering technique is verified by behavior simulation. The simulation results show that the spurious free dynamic range (SFDR) is improved effectively and the degradation of signal-to-noise ratio (SNR) can be minimized.
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5

Faure, Nicolaas, and Saurabh Sinha. "High-speed Cherry Hooper flash analog-to-digital converter." Microelectronics International 34, no. 1 (January 3, 2017): 22–29. http://dx.doi.org/10.1108/mi-08-2015-0075.

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Purpose The 60 GHz unlicensed band is being utilized for high-speed wireless networks with data rates in the gigabit range. To successfully make use of these high-speed signals in a digital system, a high-speed analog-to-digital converter (ADC) is necessary. This paper aims to present the use of a common collector (CC) input tree and Cherry Hooper (C-H) differential amplifier to enable analog-to-digital conversion at high frequencies. Design/methodology/approach The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain bandwidth speeds higher than the comparator stages while using less current than the comparator stages. The C-H differential amplifier is modified to accommodate the low breakdown voltages of the technology node and implemented as a comparator. The comparator stages are biased to obtain a high output voltage swing and have a small signal bandwidth up to 29 GHz. Simulations were performed using foundry development kits to verify circuit operation. A two-bit ADC was prototyped in IBM’s 130 nm SiGe BiCMOS 8HP technology node. Measurements were carried out on test printed circuit boards and compared with simulation results. Findings The use of the added CC input tree showed a simulated bandwidth improvement of approximately 3.23 times when compared to a basic flash architecture, for a two-bit ADC. Measured results showed an effective number of bits (ENOB) of 1.18, from DC up to 2 GHz, whereas the simulated result was 1.5. The maximum measured integral non-linearity and differential non-linearity was 0.33 LSB. The prototype ADC had a figure of merit of 42 pJ/sample. Originality/value The prototype ADC results showed that the group delay for the C-H comparator plays a critical role in ADC performance for high frequency input signals. For minimal component variation, the group delay between channels deviate from each other, causing incorrect output codes. The prototype ADC had a low gain which reduced the comparator performance. The two-bit CC C-H ADC is capable of achieving an ENOB close to 1.18, for frequencies up to 2 GHz, with 180 mW total power consumption.
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6

Sudimanto. "Perancangan Thermometer Digital tanpa Menggunakan Mikrokontroler." Media Informatika 18, no. 1 (March 1, 2019): 37–41. http://dx.doi.org/10.37595/mediainfo.v18i1.23.

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Suhu adalah suatu pengukuran yang menunjukan kondisi panas dari sebuah benda atau kondisi panas tubuh dari manusia maupun hewan. Suhu mempunyai data analog sehingga data yang baca agak sulit. Data analog bersifat continues yang artinya data tersebut memiliki sifat berkesinambungan. Berbeda dengan data digital yang merupakan data diskrit. Oleh karena itu dibutuhkan sebuah pegubah sinyal atau data yang dapat merubah data analog menjadi data digital atau yang biasa disebut juga dengan Analog Digital Converter (ADC). Perancangan ini hanya menggunakan ADC sebagai pembaca data analog dan mengubah menjadi digital yang mana di tampilkan melalui LED.
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7

Mr. Nikhil Surkar, Ms. Shriya Timande. "Analysis of Analog to Digital Converter for Biomedical Applications." International Journal of New Practices in Management and Engineering 1, no. 03 (September 30, 2012): 01–07. http://dx.doi.org/10.17762/ijnpme.v1i03.6.

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This paper presents an ADC which can be used for biomedical application like pacemaker. For the low-power operation, monotonic switching scheme and operating voltage reduction have been implemented in the design. The 10bit 1.8V rail-to-rail (SAR) ADC is realized using UMC 0.18µm CMOS process. Simulations are performed by spectre simulation. From static performance, offset error and full scale error are noticed. This performance issue can be corrected by reducing discharge in capacitor by implementing sampling switch as bootstrapped switch and proper selection of common-mode voltage where 20fF is used as unit capacitance.
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8

Miyata, Takeo, Satoshi Nidaira, Kazushi Shimizu, and Kousuke Tsukamoto. "An Analog-to-Digital Converter with Frequency Dependent Effective Resolution." IEEJ Transactions on Electronics, Information and Systems 112, no. 4 (1992): 216–20. http://dx.doi.org/10.1541/ieejeiss1987.112.4_216.

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9

Jovanović, Jelena, and Dragan Denić. "A Cost-effective Method for Resolution Increase of the Twostage Piecewise Linear ADC Used for Sensor Linearization." Measurement Science Review 16, no. 1 (February 1, 2016): 28–34. http://dx.doi.org/10.1515/msr-2016-0005.

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Abstract A cost-effective method for resolution increase of a two-stage piecewise linear analog-to-digital converter used for sensor linearization is proposed in this paper. In both conversion stages flash analog-to-digital converters are employed. Resolution increase by one bit per conversion stage is performed by introducing one additional comparator in front of each of two flash analog-to-digital converters, while the converters’ resolutions remain the same. As a result, the number of employed comparators, as well as the circuit complexity and the power consumption originating from employed comparators are for almost 50 % lower in comparison to the same parameters referring to the linearization circuit of the conventional design and of the same resolution. Since the number of employed comparators is significantly reduced according to the proposed method, special modifications of the linearization circuit are needed in order to properly adjust reference voltages of employed comparators.
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10

Gaude, Disha, Bathini Poornima, Sudharshan K. M., and Prashant V. Joshi. "Design and Simulation of 4-Bit Flash Analog to Digital Converter (ADC) for High Speed Applications." Indian Journal of Science and Technology 12, no. 36 (September 20, 2019): 1–7. http://dx.doi.org/10.17485/ijst/2019/v12i36/148021.

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11

Quenzer-Hohmuth, Samuel, Thoralf Rosahl, Steffen Ritzmann, and Bernhard Wicht. "Challenges and implementation aspects of switched-mode power supplies with digital control for automotive applications." Advances in Radio Science 14 (September 28, 2016): 85–90. http://dx.doi.org/10.5194/ars-14-85-2016.

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Abstract. Switched-mode power supplies (SMPS) convert an input DC-voltage into a higher or lower output voltage. In automotive, analog control is mostly used in order to keep the required output voltages constant and resistant to disturbances. The design of robust analog control for SMPS faces parameter variations of integrated and external passive components. Using digital control, parameter variations can be eliminated and the required area for the integrated circuit can be reduced at the same time. Digital control design bears challenges like the prevention of limit cycle oscillations and controller-wind-up. This paper reviews how to prevent these effects. Digital control loops introduce new sources for dead times in the control loop, for example the latency of the analog-to-digital-converter (ADC). Dead times have negative influence on the stability of the control loop, because they lead to phase delays. Consequently, low latency is one of the key requirements for analog-to-digital-converters in digitally controlled SMPS. Exploiting the example of a 500 kHz-buck converter with a crossover frequency of 70 kHz, this paper shows that the 5 µs-latency of a ΔΣ-analog-to-digital-converter leads to a reduction in phase margin of 126°. The latency is less critical for boost converters because of their inherent lower crossover frequencies. Finally, the paper shows a comparison between analog and digital control of SMPS with regard to chip area and test costs.
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12

Chen, Guo Ping, Xian Zhong Jian, and Er Liang Xiao. "Design and Simulation of a Pipeline Analog-to-Digital Converter." Applied Mechanics and Materials 182-183 (June 2012): 1154–58. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.1154.

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The pipeline Analog-to-Digital Converter is highlight for its high resolution, accuracy, speed and low power consumption. In this paper, we have completed the design and simulation of a pipeline ADC with the SIMULINK toolbox of MATLAB. The model of 1.5 bit per stage was set up, and nine stages were connected to establish the system model. The system model can work correctly at 100MHz sampling frequency and reach 10 bit resolution. The simulation results can verify the correction of the pipeline ADC theory.
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13

Belega, Daniel, and Dan Stoiciu. "Polynomial approximation of the transfer function of an analog-to-digital converter." Facta universitatis - series: Electronics and Energetics 17, no. 3 (2004): 443–53. http://dx.doi.org/10.2298/fuee0403443b.

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In this paper the polynomial approximation of the transfer function of an analog-to-digital converter (ADC) affected by harmonic distortions is investigated. The theoretical expression of the polynomial approximation of the transfer function of an ADC with harmonic components up to 5th order in the case of a sine wave test signal is derived. Also, a practical method to determine the polynomial approximation of an ADC is proposed. The simulation effected confirmed that the results obtained by this method are very accurate. Moreover, an ADC test system, developed to determine the polynomial approximation of the transfer function of an ADC by the proposed method is presented. Some experimental results obtained with this test system are given.
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14

Jung, Inseok, Kyung Ki Kim, and Yong-Bin Kim. "A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC." Journal of Integrated Circuits and Systems 10, no. 3 (December 28, 2015): 187–200. http://dx.doi.org/10.29292/jics.v10i3.422.

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This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.
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15

Wang, Jia Rong, Xiao Dong Xia, Zong Da Zhang, and Han Yang. "Using Dual-Channel D/A Converters Design Successive Approximation A/D Converter." Applied Mechanics and Materials 719-720 (January 2015): 611–14. http://dx.doi.org/10.4028/www.scientific.net/amm.719-720.611.

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The successive approximation analog-to-digital converter (ADC) has been widely used in electronic devices due to the corresponding characteristics which are low cost, low power consumption, high accuracy and so on. This paper expounds a design of successive approximation A / D converter to show how to use TCL5615 which is a dual-channel serial 10-bit D/A converter (DAC) to make the conversion accuracy to reach 14-bit.
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Fahmy, Ghazal A., and Mohamed Zorkany. "Design of a Memristor-Based Digital to Analog Converter (DAC)." Electronics 10, no. 5 (March 7, 2021): 622. http://dx.doi.org/10.3390/electronics10050622.

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A memristor element has been highlighted in recent years and has been applied to several applications. In this work, a memristor-based digital to analog converter (DAC) was proposed due to the fact that a memristor has low area, low power, and a low threshold voltage. The proposed memristor DAC depends on the basic DAC cell, consisting of two memristors connected in opposite directions. This basic DAC cell was used to build and simulate both a 4 bit and an 8 bit DAC. Moreover, a sneak path issue was illustrated and its solution was provided. The proposed design reduced the area by 40%. The 8 bit memristor DAC has been designed and used in a successive approximation register analog to digital converter (SAR-ADC) instead of in a capacitor DAC (which would require a large area and consume more switching power). The SAR-ADC with a memristor-based DAC achieves a signal to noise and distortion ratio (SNDR) of 49.3 dB and a spurious free dynamic range (SFDR) of 61 dB with a power supply of 1.2 V and a consumption of 21 µW. The figure of merit (FoM) of the proposed SAR-ADC is 87.9 fj/Conv.-step. The proposed designs were simulated with optimized parameters using a voltage threshold adaptive memristor (VTEAM) model.
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Zhao, Xing Sheng, Xiao Jun Wang, Dan Niu, and Chao Li. "Voltage Measurement with Improved Multi-Slope Integral Analog-to-Digital Converter." Applied Mechanics and Materials 742 (March 2015): 90–94. http://dx.doi.org/10.4028/www.scientific.net/amm.742.90.

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This paper presents a 20 Hz to 200K Hz alternating current (AC) and direct current (DC) analog-to-digital converter (ADC). The strange to minimize the zero crossing noise adopts hysteresis comparison technique. Multi-slope integral technique is also employed to enhance measurement accuracy. Furthermore, an algorism is designed to eliminate measure error. The prototype ADC achieves millivolt precision.
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18

Bchir, Mounira, Thouraya Ettaghzouti, and Néjib Hassen. "A Novel High Frequency Low Voltage Low Power Current Mode Analog to Digital Converter Pipeline." Journal of Low Power Electronics 15, no. 4 (December 1, 2019): 368–78. http://dx.doi.org/10.1166/jolpe.2019.1621.

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This paper introduces a novel structure for the realization of a low voltage, low power current-mode analog to the digital converter (ADC) pipeline (12 bits). The proposed structure of the ADC is based on a novel design of a current comparator and Digital to Analog Converter (DAC) structure. This modification allows us to reach a higher speed, lower voltage, and lower power dissipation. ELDO simulators using 0.18 μm, CMOS and TSMC parameters are performed to confirm the workability of this architecture. The proposed ADC is powered with a 1 V supply voltage. It is characterized by wide conversion frequency (350 MHz) and low power consumption that is 2.76 mW.
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Kelly, Brandon M., Alexander T. DiLello, and David W. Graham. "Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion." Journal of Low Power Electronics and Applications 9, no. 3 (August 12, 2019): 25. http://dx.doi.org/10.3390/jlpea9030025.

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Wearable medical devices, wireless sensor networks, and other energy-constrained sensing devices are often concerned with finding specific data within more-complex signals while maintaining low power consumption. Traditional analog-to-digital converters (ADCs) can capture the sensor information at a high resolution to enable a subsequent digital system to process for the desired data. However, traditional ADCs can be inefficient for applications that only require specific points of data. This work offers an alternative path to lower the energy expenditure in the quantization stage—asynchronous content-dependent sampling. This asynchronous sampling scheme is achieved by pairing a flexible analog front-end with an asynchronous successive-approximation ADC and a time-to-digital converter. The versatility and reprogrammability of this system allows a multitude of event-driven, asynchronous, or even purely data-driven quantization methods to be implemented for a variety of different applications. The system, fabricated in standard 0.5 μ m and 0.35 μ m processes, is demonstrated along with example applications with voice, EMG, and ECG signals.
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20

Marcinkevičius, Albinas J., and V. Jasonis. "The Calculation of Dynamic Errors in Signal Transformation Circuits of Analog-to-Digital Converters for Mechatronic Systems." Solid State Phenomena 113 (June 2006): 131–36. http://dx.doi.org/10.4028/www.scientific.net/ssp.113.131.

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Precision and wide-band analog-to-digital converters (ADC) are used for information processing in mechatronic systems. The analog signal transformation circuits, such as sample, and hold circuit (SHC) and an analog signal interpolation circuit (ASIC), are applied with the aim of increasing the precision of converters. These circuits allow for reducing the quantity of comparators in the converter and increase their dynamic stability. The models of SHC and ASIC as well as the results of the calculation precision and dynamic parameters of such circuits are presented in this paper. Equations for the calculation of the aperture error in the Gaussian and a sinusoidal input signal were derived. The structural model, proposed for SHC, evaluates the nonlinearity of a transfer characteristic, and the influence of noise in the signal and strobe channels. The results of the theoretical research and analytical equations for the evaluation of the number of signal interpolation block differential amplifiers, which depends on the analog signal’s maximal frequency and the number of segments of the converter, are presented. The results of this work allow one to estimate the main precision and dynamic parameters of ADC transformation circuits.
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Magerramov, R. V. "APPLICATION OF THE PLL CONTROL AT THE REALIZATION OF A 16-THROUGH ADC." Issues of radio electronics, no. 8 (August 20, 2018): 6–12. http://dx.doi.org/10.21778/2218-5453-2018-8-6-12.

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This article describes the method of converting an analog signal into a digital code using a phase locked loop (PLL) circuit. The functional structure of the voltage-to-digital conversion circuit is considered. The application of the principle of phase-locked loop for controlling the duty cycle of the output signal of a phase detector when the voltage at the positive input of the operational amplifier included in the low-pass filter is investigated. In the modern world, analog-to-digital converters (ADCs) are available in almost every electronic device. The application of different ADC architectures is determined by their parameters and features by circuit and technological implementation. The phase-locked loop with a digital part (16-bit counter, storage register and data transfer interface) allows to obtain a precision analog-to-digital converter, based on a relatively simple circuit design, which has high accuracy and low noise level. Negative feedback of the PLL loop makes it possible to level the error of the passive elements of the low-pass filter (LPF) and the voltage controlled oscillator (VCO). The result of this work is an analysis of the ADC characteristics in the technological basis of 250 nm.
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Yadav, Nandakishor, Youngbae Kim, Mahmoud Alashi, and Kyuwon Ken Choi. "Sensitive, Linear, Robust Current-To-Time Converter Circuit for Vehicle Automation Application." Electronics 9, no. 3 (March 16, 2020): 490. http://dx.doi.org/10.3390/electronics9030490.

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Voltage-to-time and current-to-time converters have been used in many recent works as a voltage-to-digital converter for artificial intelligence applications. In general, most of the previous designs use the current-starved technique or a capacitor-based delay unit, which is non-linear, expensive, and requires a large area. In this paper, we propose a highly linear current-to-digital converter. An optimization method is also proposed to generate the optimal converter design containing the smallest number of PMOS and sensitive circuits such as a differential amplifier. This enabled our design to be more stable and robust toward negative bias temperature instability (NBTI) and process variation. The proposed converter circuit implements the point-wise conversion from current-to-time, and it can be used directly for a variety of applications, such as analog-to-digital converters (ADC), used in built-in computational random access (C-RAM) memory. The conversion gain of the proposed circuit is 3.86 ms/A, which is 52 times greater than the conversion gains of state-of-the-art designs. Further, various time-to-digital converter (TDC) circuits are reviewed for the proposed current-to-time converter, and we recommend one circuit for a complete ADC design.
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23

Peralías, E. J., M. A. Jalón, and A. Rueda. "Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach." VLSI Design 2008 (July 22, 2008): 1–8. http://dx.doi.org/10.1155/2008/657207.

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This work presents a new method to estimate the nonlinearity characteristics of analog-to-digital converters (ADCs). The method is based on a nonnecessarily polynomial continuous and differentiable mathematical model of the converter transfer function, and on the spectral processing of the converter output under a sinusoidal input excitation. The simulation and experiments performed on different ADC examples prove the feasibility of the proposed method, even when the ADC nonlinearity pattern has very strong discontinuities. When compared with the traditional code histogram method, it also shows its low cost and efficiency since a significant lower number of output samples can be used still giving very realistic INL signature values.
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Kobayashi, Yutaro, and Haruo Kobayashi. "Redundant SAR ADC Algorithm Based on Fibonacci Sequence." Key Engineering Materials 698 (July 2016): 118–26. http://dx.doi.org/10.4028/www.scientific.net/kem.698.118.

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This paper describes a redundant Successive Approximation Register Analog-to-Digital Converter (SAR ADC) design method which enables high-reliability and high-speed AD conversion by using digital error correction. Especially we introduce to apply Fibonacci sequence and its property called Golden ratio to SAR ADC design to improve conventional redundant search algorithms. We also present some derived equations and many beautiful properties for well-balanced redundancy design for SAR ADC
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25

Zhenatov, B. D. "Expansion of dynamic range of sampling and storage device by weight integration of narrow-band oscillation." Omsk Scientific Bulletin, no. 178 (2021): 80–82. http://dx.doi.org/10.25206/1813-8225-2021-178-80-82.

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The most bottleneck of high-frequency digital radio receivers in terms of dynamic characteristics is the process of analog-to-digital conversion. Most often, to meet the requirements for the speed and dynamic range of the analog-to-digital conversion, a sampling and storage device (UHF) is included in front of the analog-to-digital converter (ADC), which is significantly simpler in structure than the ADC structure, but reduces the requirements for its speed and dynamic range [1, 2]. A method for expanding the dynamic range of the integrating sampling and storage device for digital radio receivers using the weight integration of the input narrow-band oscillation is proposed
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26

Zurita, M., R. C. S. Freire, S. Tedjini, and S. A. Moshkalev. "A Review of Implementing ADC in RFID Sensor." Journal of Sensors 2016 (2016): 1–14. http://dx.doi.org/10.1155/2016/8952947.

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The general considerations to design a sensor interface for passive RFID tags are discussed. This way, power and timing constraints imposed by ISO/IEC 15693 and ISO/IEC 14443 standards to HF RFID tags are explored. A generic multisensor interface is proposed and a survey analysis on the most suitable analog-to-digital converters for passive RFID sensing applications is reported. The most appropriate converter type and architecture are suggested. At the end, a specific sensor interface for carbon nanotube gas sensors is proposed and a brief discussion about its implemented circuits and preliminary results is made.
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Muthers, D., and R. Tielert. "Ein 10 bit 10MS/s Low-Power AD-Converter in 0.11mm2." Advances in Radio Science 2 (May 27, 2005): 205–9. http://dx.doi.org/10.5194/ars-2-205-2004.

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Abstract. Ein 10 bit 10MS/s Analog-Digital- Wandler mit niedriger Leistungaufnahme von 8,4mW wurde implementiert. Der geringe Flächenbedarf von 0,11mm2 macht diesen Wandler besonders geeignet f¨ur Multikanalanwendungen. Um die Anforderungen von 10 bit, 10 MS/s möglichst effizient zu erfüllen wurde eine zyklische Wandlerarchitektur gewählt, die in einem 0,18μm-CMOSProzess mit MIM-Kondensatoren implementiert wurde. Der entworfene ADC wurde in 21 parallelen Kanälen auf einem mixed-signal-Chip zusammen mit digitalen Filtern, vier RISC-CPUs und I/O-Schaltungen implementiert. A 10 bit 10MS/s Analog to Digital Converter, consuming a power of 8,4mW, has been implemented. Due to the small area of 0,11mm2 this ADC is highly suited for multichannel implementations. A cyclic converter architecture is best suited for this application, being implemented in a 0,18μm CMOS process with MIM-capacitors. The designed ADC was implemented in an array of 21 channels on a mixed signal chip together with digital filters, four RISC-CPUs and I/O circuitry.
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Sokolov, Kamenskij, Novikov, and Ivetić. "How to Increase the Analog-to-Digital Converter Speed in Optoelectronic Systems of the Seed Quality Rapid Analyzer." Inventions 4, no. 4 (October 6, 2019): 61. http://dx.doi.org/10.3390/inventions4040061.

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This invention is relevant when working as part of optoelectronic systems, including non-destructive quality control of forest seeds. The possibility of synthesis of the ultrafast optical analog-to-digital converter (ADC) providing conversion of analog information to digital in the sub-GHz range is considered. The functional scheme of the optical ADC, containing technologically well-developed optical elements is given; the principle of operation is described in detail. The possibility of increasing the speed of the ADC to make it potentially possible for optical data processing schemes is shown.
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Elgreatly, Ahmed, Ahmed Dessouki, Hassan Mostafa, Rania Abdalla, and El-sayed El-Rabaie. "A Novel Highly Linear Voltage-To-Time Converter (VTC) Circuit for Time-Based Analog-To-Digital Converters (ADC) Using Body Biasing." Electronics 9, no. 12 (December 1, 2020): 2033. http://dx.doi.org/10.3390/electronics9122033.

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Time-based analog-to-digital converter is considered a crucial part in the design of software-defined radio receivers for its higher performance than other analog-to-digital converters in terms of operation speed, input dynamic range and power consumption. In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These novel converters exhibit better linearity, which is analytically proven in this paper. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800 mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology. These novel designs consist of only a single inverter stage, which results in reducing the layout area and the power consumption. The overall power consumption is 18 μW for the first proposed circuit and 15 μW for the second proposed circuit. The novel converter circuits have a resolution of 5 bits and operate at a maximum clock frequency of 500 MHz.
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30

Al-Naamani, Yahya Mohammed Ali, K. Lokesh Krishna, and A. M. Guna Sekhar. "A Successive Approximation Register Analog to Digital Converter for Low Power Applications." Journal of Computational and Theoretical Nanoscience 17, no. 1 (January 1, 2020): 451–55. http://dx.doi.org/10.1166/jctn.2020.8689.

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In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less die area poses a stringent requirement in designing and fabricating an ultra-low power ADCs. Among the diverse converter architectures existing, Successive Approximation Register (SAR) type converter architecture has shown better capabilities in terms of ultra-low power operation, medium resolution, less form factor and less silicon area. In this described paper a novel power effective, better resolution SAR type ADC to be used for biomedical related applications. The proposed work consists of capacitive type Digital to Analog Converter (DAC) based on charge distribution, a CMOS comparator, and SAR logic implemented using D-flip-flops. The different blocks of SAR architecture are simulated using EDA tools in CMOS 180 nm N-well process operated at VDD = 1.5 V voltage (VDD). The circuit is measured under various input frequencies with a sampling speed of 50 MHz and it consumes 22.6 μW. The proposed ADC technology shows SNDR of 48.6 dB and occupies a circuit area of 0.11 mm2 and the measured INL and DNL is calculated to be fewer than 0.54 LSB and 0.45 LSB respectively.
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31

KOCAK, TASKIN, GEORGE R. HARRIS, and RONALD F. DEMARA. "SELF-TIMED ARCHITECTURE FOR MASKED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION." Journal of Circuits, Systems and Computers 16, no. 01 (February 2007): 1–14. http://dx.doi.org/10.1142/s0218126607003551.

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In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.
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32

Chakir, Mostafa, Hicham Akhamal, and Hassan Qjidaa. "A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor." Scientific World Journal 2017 (2017): 1–15. http://dx.doi.org/10.1155/2017/8418042.

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The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.
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33

Osipov, Dmitry, Aleksandr Gusev, Vitaly Shumikhin, and Steffen Paul. "Noise shaping in SAR ADC." Facta universitatis - series: Electronics and Energetics 33, no. 1 (2020): 15–26. http://dx.doi.org/10.2298/fuee2001015o.

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The successive approximation register (SAR) analog-to-digital converter (ADC) is currently the most popular type of ADC architecture, owing to its power efficiency. They are also used in multichannel systems, where power efficiency is of high importance because of the large number of simultaneously working channels. However, the SAR ADC architecture is not the most area efficient. In SAR ADCs, the binary weighted capacitive digital-to-analog converter (DAC) is used, which means that one additional bit of resolution costs double the increase of area. Oversampling and noise shaping are methods that allow an increase in resolution without an increase of area. In this paper we present the new SAR ADC architectures with a noise shaping. A first-order noise transfer function (NTF) with zero located nearly at one can be achieved. We propose two modifications of the architecture: with zero-only NTF and with the NTF with additional pole. The additional pole theoretically increases the efficiency of noise shaping to further 3 dB. The architectures were applied to the design of SAR ADCs in a 65 nm complementary metal-oxide semiconductor (CMOS) with OSR equal to 10. A 6-bit capacitive DAC was used. The proposed architectures provide nearly 4 additional bits in ENOB. The equalent input bandwitdth is equal to 200 kHz with the sampling rate equal to 4 MS/s.
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34

Magerramov, R. V. "Method of frequency-phase detection used in ADC based on PLL circuit." Issues of radio electronics, no. 8 (August 7, 2019): 26–30. http://dx.doi.org/10.21778/2218-5453-2019-8-26-30.

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The phase‑locked loop (PLL) is an integral part of many electronic products in modern electronics and radio engineering, which is used to form and process analog and digital signals. One of the non‑standard applications of the PLL circuit is to implement an analog voltage‑to‑pulse converter. This application of the PLL circuit allows you to create an analog‑to‑digital converter (ADC) with high resolution, and the implementation features of the PLL circuit can provide a number of advantages, such as high noise immunity, compensation for the errors of passive elements, operation in a wide temperature range, etc. The accuracy of the conversion in such a device depends on both the separately designed blocks of the PLL circuit and the parameters of the system as a whole. The paper discusses the implementation of a digital frequency‑phase detector (FFD) operating in the range from 0 to 2p. The basis of his work is the method of frequency‑phase detection, which reduces the time of transients in the PLL circuit, and also eliminates the detection of coherent and multiple frequencies of the reference signal.
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35

An, Sheng-Biao, Li-Xin Zhao, Shi-Cong Yang, Tao An, and Rui-Xia Yang. "Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique." Journal of Nanoelectronics and Optoelectronics 15, no. 4 (April 1, 2020): 478–86. http://dx.doi.org/10.1166/jno.2020.2782.

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This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%. The test chip fabricated in 180 nm Complementary Metal Oxide Semiconductor (CMOS) occupied an active area of 0.12 mm 2 . At 10 MS/s, a signal-to-noise and distortion ratio (SNDR) of 57.70 dB and a spurious-free dynamic range (SFDR) of 55.63 dB are measured with 1.68 Vpp differential-mode input signal. The total power consumption is 690 μW corresponding to 67 fJ/conversion step figure of merit.
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36

Quintero, Andres, Fernando Cardes, Carlos Perez, Cesare Buffa, Andreas Wiesbauer, and Luis Hernandez. "A VCO-Based CMOS Readout Circuit for Capacitive MEMS Microphones." Sensors 19, no. 19 (September 24, 2019): 4126. http://dx.doi.org/10.3390/s19194126.

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Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered “always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta ( Σ Δ ) analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by 1 / f and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 μ A at 1.8 V and the effective area is 0.12 mm 2 . This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.
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37

Yurish, Sergey Y. "Advanced Analog-to-Digital Conversion Using Voltage-to-Frequency Converters for Remote Sensors." Key Engineering Materials 381-382 (June 2008): 623–26. http://dx.doi.org/10.4028/www.scientific.net/kem.381-382.623.

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This paper presents an advanced analog-to-digital conversion technique based on a voltage-to-frequency-to-digital conversion that is suitable for remote sensors, telemetry applications and multichannel data acquisition systems. A voltage-to-frequency conversion part can be based, for example, on high performance, charge-balance voltage-to-frequency converter (VFC), where monostable is replaced by a bistable, driven by an external clock, or other existing high performance VFCs. The frequency-to-digital converter “bottleneck” problem in such promised ADC scheme was solved due to proposed advanced method of the dependent count for frequency-to-digital conversion. This ADC technique lets receive many advantages such as high accuracy, relatively low power consumption, low cost solution, wide dynamic range, great stability and faster conversion time in comparison with existing VFC-based techniques. The conversion rate (6.25 µs to 6.25 ms) in such ADC scheme is programmable, non-redundant, shorter than for pulse counting technique and comparable with successive-approximation and Σ- ADC.
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38

Watson, Jeff, and Maithil Pachchigar. "A Low Power, Precision SAR Analog to Digital Converter for High Temperature Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000053–57. http://dx.doi.org/10.4071/hitec-ta26.

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A growing number of industries are calling for low power electronics that operate reliably at temperatures of 175°C and higher. Many of these applications require a precision data acquisition signal chain in order to digitize analog data so that it can be collected and processed. Designing circuits that meet these needs can be very challenging, requiring a data converter that can deliver high performance and reliability in these harsh environments. There are currently a very limited number of integrated circuits commercially available that are specified for operation at these temperatures, and no low power precision data converters with sample rates greater than 100kSPS. This paper presents a new 210°C rated precision analog to digital converter capable of sample rates up to 600 kSPS with 16 bit resolution while maintaining low power consumption and packaged in a small form factor. We will explore the converter architecture of this ADC, present initial test results, and show how high reliability is achieved through qualification and advanced packaging techniques.
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39

Gao, Bo, Xin Li, Jie Sun, and Jianhui Wu. "Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM." Electronics 9, no. 1 (January 10, 2020): 137. http://dx.doi.org/10.3390/electronics9010137.

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The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.
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40

Ro, Duckhoon, Minseong Um, and Hyung-Min Lee. "A Soft-Error-Tolerant SAR ADC with Dual-Capacitor Sample-and-Hold Control for Sensor Systems." Sensors 21, no. 14 (July 13, 2021): 4768. http://dx.doi.org/10.3390/s21144768.

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For a reliable and stable sensor system, it is essential to precisely measure various sensor signals, such as electromagnetic field, pressure, and temperature. The measured analog signal is converted into digital bits through the sensor readout system. However, in extreme radiation environments, such as in space, during flights, and in nuclear fusion reactors, the performance of the analog-to-digital converter (ADC) constituting the sensor readout system can be degraded due to soft errors caused by radiation effects, leading to system malfunction. This paper proposes a soft-error-tolerant successive-approximation-register (SAR) ADC using dual-capacitor sample-and-hold (S/H) control, which has robust characteristics against total ionizing dose (TID) and single event effects (SEE). The proposed ADC was fabricated using 65-nm CMOS process, and its soft-error-tolerant performance was measured in radiation environments. Additionally, the proposed circuit techniques were verified by utilizing a radiation simulator CAD tool.
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41

Misto, Misto, Tri Mulyono, and Alex Alex. "Measurement System of Sugar Content in Liquid Media using Computerized Photodiode Sensor." Jurnal ILMU DASAR 17, no. 1 (January 24, 2017): 13. http://dx.doi.org/10.19184/jid.v17i1.2664.

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It has been made an electronic system for measurement of sugar cane in solution media. This system uses a pin photodiode as a sensor, laser source, optical fiber, an operational amplifier (Op-Amp), analog to digital converter (ADC) of the Arduino, and computers. The main operation of the measurement system is done by the sensor and controlled by computer. The the photodiode sensor sends a signal to a signal processing unit (op-amp) and converted to a digital signal by the ADC. The digital signal is then forwarded for processing and display (computer). We Concluded that the system working well because of the sugar content information can be simultaneously displayed on the monitor .Keywords: sugar content, pin photodiode, computer
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42

Vadipour, Morteza. "Analog digital converter (ADC) having improved stability and signal to noise ratio (SNR)." Journal of the Acoustical Society of America 125, no. 5 (2009): 3479. http://dx.doi.org/10.1121/1.3139547.

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43

Bhargava, Bhanupriya, Pradeep Kumar Sharma, and Shyam Akashe. "High Performance Analysis of CDS Delta-Sigma ADC in 45-Nanometer Regime." International Journal of Nanoscience 13, no. 01 (February 2014): 1450003. http://dx.doi.org/10.1142/s0219581x14500033.

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In this paper, a correlated double sampling (CDS) technique is proposed in the design of a delta sigma analog-to-digital converter (ADC). These CDS techniques are very effective for the compensation of the nonidealities in switched-capacitor (SC) circuits, such as charge injection, clock feed-through, operational amplifier (op-amp) input-referred offset and finite op-amp gain. An improved compensation scheme is proposed to attain continuous compensation of clock feed-through and offset in SC integrators. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. Also this CDS delta sigma ADC is the most promising circuit for analog to digital converter because this circuit reduces noise due to drift and low frequency noise such as flicker noise and offset voltage and also boosts the gain performance of the amplifier. Further, the simulation results of this circuit are verified on using a "cadence virtuoso tool" using spectre at 45 nm technology with supply voltage 0.7 V.
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44

Idzura Yusuf, Siti, Suhaidi Shafie, Hasmayadi Abdul Majid, and Izhal Abdul Halin. "Differential input range driver for SAR ADC measurement setup." Indonesian Journal of Electrical Engineering and Computer Science 17, no. 2 (February 1, 2020): 750. http://dx.doi.org/10.11591/ijeecs.v17.i2.pp750-758.

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<span>Differential successive approximation register (SAR) of analog to digital converter (ADC) requires two balancing input signals that have same amplitude with 180⁰ out of phase. Otherwise, it performs inaccurately and degrades the performance during ADC testing procedure. Therefore, an implementation of AD8139 chip single to differential amplifier was chosen as an ADC driver to generate sufficient differential output for the ADC. The chip was placed on a printed circuit board (PCB) to test the functionality as well as the performance of static and dynamic SAR ADC. The result shows that the single-ended input transform into differential voltage outputs. The amplitudes for the amplifier remain equal and is 180° out of phase for DC and AC voltage input signal. Besides, the fabricated 0.18µm CMOS technology of differential 10-bit SAR ADC is capable of digitising full code digital output and perform 9.5-bit effective number of bit (ENOB) from analog input driving by the ADC driver.</span>
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45

INANLOU, REZA, and MOHAMMAD YAVARI. "A 10-BIT 0.5 V 100 kS/s SAR ADC WITH A NEW RAIL-TO-RAIL COMPARATOR FOR ENERGY LIMITED APPLICATIONS." Journal of Circuits, Systems and Computers 23, no. 02 (February 2014): 1450026. http://dx.doi.org/10.1142/s0218126614500261.

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In this paper, a 10-bit 0.5 V 100 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a new fully dynamic rail-to-rail comparator is presented. The proposed comparator enhances the input signal range to the rail-to-rail mode, and hence, improves the signal-to-noise ratio (SNR) of the ADC in low supply voltages. The effect of the latch offset voltage is reduced by providing a higher voltage gain in the regenerative latch. To reduce the ADC power consumption further, the binary-weighted capacitive array with an attenuation capacitor (BWA) is employed as the digital-to-analog converter (DAC) in this design. The ADC is designed and simulated in a 90 nm CMOS process with a single 0.5 V power supply. Spectre simulation results show that the average power consumption of the proposed ADC is about 400 nW and the peak signal-to-noise plus distortion ratio (SNDR) is 56 dB. By considering 10% increase in total ADC power consumption due to the parasitics and a loss of 0.22 LSB in ENOB due to the DAC capacitors mismatch, the achieved figure of merit (FoM) is 11.4 fJ/conversion-step.
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46

Kroics, Kaspars. "Digital Control of Variable Frequency Interleaved DC-DC Converter." Environment. Technology. Resources. Proceedings of the International Scientific and Practical Conference 2 (August 8, 2015): 124. http://dx.doi.org/10.17770/etr2013vol2.854.

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This paper represents a design and implementation of a digital control of variable frequency interleaved DC-DC converter using a digital signal processor (DSP). The digital PWM generation, current and voltage sensing, user interface and the new period and pulse width value calculation with DSP STM32F407VGT6 are considered. Typically, the multiphase interleaved DC - DC converters require a current control loop in each phase to avoid imbalanced current between phases. This increases system costs and control complexity. In this paper the converter which operates in discontinuous conduction mode is designed in order to reduce costs and remove the current control loop in each phase. High current ripples associated with this mode operation are then alleviated by interleaving. Pulse width modulation (PWM) is one of the most conventional modulation techniques for switching DC - DC converters. It compares the error signal with the sawtooth wave to generate the control pulse. This paper shows how six PWM signals phase-shifted by 60 degrees can be generated from calculated values. To ensure that the measured values do not contain disturbances and in order to improve the system stability the digital signal is filtered. The analog to digital converter's (ADC) sampling time must not coincide with the power transistor's switching time, therefore the sampling time must be calculated correctly as well. Digital control of the DC-DC converter makes it easy and quickly to configure. It is possible for this device to communicate with other devices in a simple way, to realize data input by using buttons and keyboard, and to display information on LED, LCD displays, etc.
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UDDIN, MOHAMMED RAFIQ, GAZI MAEEN -UR- RASHID, and MD SHAHIDUL ISLAM. "MICROCONTROLLER BASED LIGHT CONTROL." International Journal of Software Engineering and Knowledge Engineering 15, no. 02 (April 2005): 319–24. http://dx.doi.org/10.1142/s021819400500235x.

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A microcontroller-based control system is a direct outgrowth of the extensive advances in the Integrated Circuit design and microelectronic device processing technology. This has led to the development of new forms of technologies. This paper presents a technique of microcontroller based control system for controlling the lights of a room. Using the technique, according to the intensity of the sunlight in a room, the states of light of that room will change. Therefore we need to collect data or information from the environment using light sensors to control lights. The microcontroller collects the information from the atmosphere and changes the state of different lights. The analog data collected by the sensors are converted to digital form by an Analog to Digital Converter (ADC) and then fed to the microcontroller. The output data stream of the microcontroller is in digital form by which analog device lights will be controlled.
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YE, MAO, BIN WU, YONGXU ZHU, and YUMEI ZHOU. "AN OPTIMIZED LOW POWER PIPELINE ANALOG-TO-DIGITAL CONVERTER FOR HIGH-SPEED WLAN APPLICATION." Journal of Circuits, Systems and Computers 23, no. 05 (May 8, 2014): 1450059. http://dx.doi.org/10.1142/s0218126614500595.

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This paper presents the design and implementation of a 11-bit 160 MSPS analog-to-digital converter (ADC) for next generation super high-speed wireless local area network (WLAN) application. The ADC core consists of one front sample and hold stage and four cascades of 2.5 bit pipeline stages with opamp sharing between successive stages. To achieve low power dissipation at 1.2 V supply, a single stage symmetrical amplifier with double transimpedance gain-boosting amplifier is proposed. High speed on-chip reference buffer with replica source follower is also included for linearity performance. The ADC was fabricated in a standard 130-nm CMOS process and an occupied silicon area of 0.95 mm × 1.15 mm. Performance of 73 dB spurious-free-dynamic-range is measured at 160 MS/s with 1 Vpp input signal. The power dissipation of the analog core chip is only 50 mW from a 1.2 V supply.
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Prasad, Deepak, and Vijay Nath. "An Ultra Low Power CMOS Sigma Delta ADC Modulator for System-on-chip (SoC) Temperature Sensor for Aerospace Applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (May 30, 2018): 12. http://dx.doi.org/10.11591/ijres.v7.i1.pp12-20.

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In the current paper, an accurate with low power consumed sigma delta (ΣΔ) analog to digital converter has been designed for the aerospace applications. The sigma delta ADC has been designed in such a way that it works fine with consumption of low power and high accuracy in the system on chip (SoC) temperature sensor where the analog output from the temperature sensor unit will be the fed to the analog to digital converter. To check the robustness, different parameters with variation has been analyzed. The high gain operational amplifier plays a vital role in the circuits design. Hence, a 30 MHz operational amplifier has also been proposed whose unity gain bandwidth (UGB) has been observed of about 30 MHz, 51.1dB dc gain and slew rate (SR) of about 27.9 V/ μsec. For the proper operation of the circuit, a power supply of +1.3V to -1.3V is used. The proposed sigma delta ADC modulator is showing better results over previously designed modulator in terms of power consumption, error and performance. The design and simulation have been tested with the help of cadence analog design environment with UMC 90nm CMOS process technology.
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Wan, Peiyuan, Limei Su, Hongda Zhang, and Zhijie Chen. "A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC." Electronics 9, no. 1 (January 20, 2020): 199. http://dx.doi.org/10.3390/electronics9010199.

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An unity-gain 1-bit flip-around digital-to-analog converter (FADAC), without any capacitor matching issue, is proposed as the front-end input stage in a pipelined analog-to-digital converter (ADC), allowing an input signal voltage swing up to be doubled. This large input swing, coupled with the inherent large feedback factor (ideally β = 1) of the proposed FADAC, enables a power-efficient low-voltage high-resolution pipelined ADC design. The 1-bit FADAC is exploited in a SHA-less and opamp-sharing pipelined ADC, exhibiting 12-bit resolution with an input swing of 1.8 Vpp under a 1.1 V power supply. Fabricated in a 0.13-μm CMOS process, the prototype ADC achieves a measured signal-to-noise plus distortion ratio (SNDR) of 66.4 dB and a spurious-free dynamic range (SFDR) of 76.7 dB at 20 MS/s sampling rate. The ADC dissipates 5.2 mW of power and occupies an active area of 0.44 mm2. The measured differential nonlinearity (DNL) is +0.72/−0.52 least significant bit (LSB) and integral nonlinearity (INL) is +0.84/−0.75 LSB at a 3-MHz sinusoidal input.
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