Relevant bibliographies by topics / Analog front end design for compressed sensing

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  1. Journal articles
  2. Dissertations / Theses
  3. Conference papers

Academic literature on the topic 'Analog front end design for compressed sensing'

Author: Grafiati
Published: 4 June 2021
Last updated: 5 February 2022

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Journal articles on the topic "Analog front end design for compressed sensing"

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Gangopadhyay, Daibashish, Emily G. Allstot, Anna M. R. Dixon, Karthik Natarajan, Subhanshu Gupta, and David J. Allstot. "Compressed Sensing Analog Front-End for Bio-Sensor Applications." IEEE Journal of Solid-State Circuits 49, no. 2 (February 2014): 426–38. http://dx.doi.org/10.1109/jssc.2013.2284673.

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Nam, Hyohyun, Junsik Park, Kyu-Ha Song, and Jung-Dong Park. "Design of an Integrated Broadband Front-end for the Compressed Sensing Receiver." Journal of the Institute of Electronics and Information Engineers 55, no. 4 (April 30, 2018): 37–43. http://dx.doi.org/10.5573/ieie.2018.55.4.37.

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Sadhu, Bodhisatwa, Martin Sturm, Brian M. Sadler, and Ramesh Harjani. "Passive Switched Capacitor RF Front Ends for Spectrum Sensing in Cognitive Radios." International Journal of Antennas and Propagation 2014 (2014): 1–20. http://dx.doi.org/10.1155/2014/947373.

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This paper explores passive switched capacitor based RF receiver front ends for spectrum sensing. Wideband spectrum sensors remain the most challenging block in the software defined radio hardware design. The use of passive switched capacitors provides a very low power signal conditioning front end that enables parallel digitization and software control and cognitive capabilities in the digital domain. In this paper, existing architectures are reviewed followed by a discussion of high speed passive switched capacitor designs. A passive analog FFT front end design is presented as an example analog conditioning circuit. Design methodology, modeling, and optimization techniques are outlined. Measurements are presented demonstrating a 5 GHz broadband front end that consumes only 4 mW power.
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Ganguly, Anirban, and Ayan Banerjee. "Precise realization of one-staged 2-D DCT using analog current mode architecture in compressed sensing front-end." Microelectronics Journal 115 (September 2021): 105184. http://dx.doi.org/10.1016/j.mejo.2021.105184.

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Luo, Kan, Zhipeng Cai, Keqin Du, Fumin Zou, Xiangyu Zhang, and Jianqing Li. "A Digital Compressed Sensing-Based Energy-Efficient Single-Spot Bluetooth ECG Node." Journal of Healthcare Engineering 2018 (2018): 1–11. http://dx.doi.org/10.1155/2018/2687389.

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Energy efficiency is still the obstacle for long-term real-time wireless ECG monitoring. In this paper, a digital compressed sensing- (CS-) based single-spot Bluetooth ECG node is proposed to deal with the challenge in wireless ECG application. A periodic sleep/wake-up scheme and a CS-based compression algorithm are implemented in a node, which consists of ultra-low-power analog front-end, microcontroller, Bluetooth 4.0 communication module, and so forth. The efficiency improvement and the node’s specifics are evidenced by the experiments using the ECG signals sampled by the proposed node under daily activities of lay, sit, stand, walk, and run. Under using sparse binary matrix (SBM), block sparse Bayesian learning (BSBL) method, and discrete cosine transform (DCT) basis, all ECG signals were essentially undistorted recovered with root-mean-square differences (PRDs) which are less than 6%. The proposed sleep/wake-up scheme and data compression can reduce the airtime over energy-hungry wireless links, the energy consumption of proposed node is 6.53 mJ, and the energy consumption of radio decreases 77.37%. Moreover, the energy consumption increase caused by CS code execution is negligible, which is 1.3% of the total energy consumption.
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Ohme, Bruce W., Mark R. Larson, Bhal Tulpule, and Alireza Behbahani. "Characterization of Circuit Blocks for Configurable Analog-Front-End." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000146–53. http://dx.doi.org/10.4071/hitec-wa13.

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Analog functions have been implemented in a Silicon-on-Insulator (SOI) process optimized for high-temperature (>225°C) operation. These include a linear regulator/reference block that supports input voltages up to 50V and provides multiple independent voltage outputs. Additional blocks provide configurable sensor excitation levels of up to 10V DC and/or 20V AC-differential, with current limiting and monitoring. A dual-channel Programmable-Gain-Instrumentation Amplifier (PGIA) and a high-level AC input block with programmable gain and offset serve signal conditioning, gain, and scaling needs. A multiplexer and analog buffer provide an output that is scaled and centered for down-stream A-to-D conversion. Limited component availability and high component counts deter development of sensing and control electronics for extreme temperature (>200°) applications. Systems require front-end power conditioning, sensor excitation and monitoring, response amplification, scaling, and multiplexing. Back-end Analog-to-Digital conversion and digital processing/control can be implemented using one or two integrated circuit chips, whereas the front-end functions require component counts in the dozens. The low level of integration in the available portfolio of SOI devices results in high component count when constructing signal conditioning interfaces for aerospace sensors. These include quasi-DC sensors such as thermo-couples, strain-gauges, bridge transducers as well as AC-coupled sensors and position transducers, such as Linear Variable Differential Transducers (LVDT's). Furthermore, a majority of sensor applications are best served by excitation/response voltage ranges that typically exceed the voltage range of digital electronics (either 5V or 3.3V in currently available digital IC's for use above 200°C). These constraints led Embedded Systems LLC to design a generic device which was implemented by Honeywell as an analog ASIC (Application Specific Integrated Circuit). This paper will describe the ASIC block-level capabilities in the context of the typical applications and present characterization data from wafer-level testing at the target temperature range (225C). This material is based upon work performed by Honeywell International under a subcontract from Embedded Systems LLC, funding for which was provided by the U.S. Air Force Small Business Innovative Research program.
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Wang, Yihang, Qiang Fu, Yufeng Zhang, Wenbo Zhang, Dongliang Chen, Liang Yin, and Xiaowei Liu. "A Digital Closed-Loop Sense MEMS Disk Resonator Gyroscope Circuit Design Based on Integrated Analog Front-end." Sensors 20, no. 3 (January 27, 2020): 687. http://dx.doi.org/10.3390/s20030687.

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A digital closed-loop system design of a microelectromechanical systems (MEMS) disk resonator gyroscope (DRG) is proposed in this paper. Vibration models with non-ideal factors are provided based on the structure characteristics and operation mode of the sensing element. The DRG operates in force balance mode with four control loops. A closed self-excited loop realizes stable vibration amplitude on the basis of peak detection technology and phase control loop. Force-to-rebalance technology is employed for the closed sense loop. A high-frequency carrier loaded on an anchor weakens the effect of parasitic capacitances coupling. The signal detected by the charge amplifier is demodulated and converted into a digital output for subsequent processing. Considering compatibility with digital circuits and output precision demands, a low passband sigma-delta (ΣΔ) analog-to-digital converter (ADC) is implemented with a 111.8dB signal-to-noise ratio (SNR). The analog front-end and digital closed self-excited loop is manufactured with a standard 0.35 µm complementary metal-oxide-semiconductor (CMOS) technology. The experimental results show a bias instability of 2.1 °/h and a nonlinearity of 0.035% over the ± 400° full-scale range.
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Voulgari, Evgenia, François Krummenacher, and Maher Kayal. "ANTIGONE: A Programmable Energy-Efficient Current Digitizer for an ISFET Wearable Sweat Sensing System." Sensors 21, no. 6 (March 16, 2021): 2074. http://dx.doi.org/10.3390/s21062074.

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This article describes the design and the characterization of the ANTIGONE (ANalog To dIGital cONvErter) ASIC (Application Specific Integrated Circuit) built in AMS 0.35 m technology for low dc-current sensing. This energy-efficient ASIC was specifically designed to interface with multiple Ion-Sensitive Field-Effect Transistors (ISFETs) and detect biomarkers like pH, Na+, K+ and Ca2+ in human sweat. The ISFET-ASIC system can allow real-time noninvasive and continuous health monitoring. The ANTIGONE ASIC architecture is based on the current-to-frequency converter through the charge balancing principle. The same front-end can digitize multiple currents produced by four sweat ISFET sensors in time multiplexing. The front-end demonstrates good linearity over a dynamic range that spans from 1 pA up to 500 nA. The consumed energy per conversion is less than 1 J. The chip is programmable and works in eight different modes of operation. The system uses a standard Serial Peripheral Interface (SPI) to configure, control and read the digitally converted sensor data. The chip is controlled by a portable device over Bluetooth Low Energy (BLE) through a Microcontroller Unit (MCU). The sweat sensing system is part of a bigger wearable platform that exploits the convergence of multiparameter biosensors and environmental sensors for personalized and preventive healthcare.
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Dissertations / Theses on the topic "Analog front end design for compressed sensing"

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Shah, Julin Mukeshkumar. "Compressive Sensing Analog Front End Design in 180 nm CMOS Technology." Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1440381988.

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Li, Wen-Chih, and 李文志. "Analog Front-end Circuits and Time-Frequency Analysis Design for ECG Sensing System." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/z48cz8.

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碩士
國立中山大學
醫學科技研究所
106
Recently, the demand for wireless electronic medical devices has been greatly increased. The innovation of wearable sensors with a portable data analysis device can not only monitors medical parameters of the patient under the less affection to human’s daily activities. Based on above design target, we design several chips for the implementation of the measuring and analyzing platform which includes the following three parts: (1) A front-end readout circuit is composed of Instrumentation Amplifier (IA), band-pass filter, gain stage, and Analog-to-Digital Converter (ADC); (2) A digital signal processor on Field-Programmable Gate Array (FPGA) is responsible for handling the convolution operation of Hanning window; (3) A back-end analysis circuit is composed of sliding discrete Fourier transform (SDFT); The operational steps for the proposed platform are as follow: (1) we convert electrocardiogram (ECG) signals to digital codes through the front-end circuit; (2) the processor on FPGA will deal with the ECG digital codes by multiplying the cefficients of Hanning window; (3) the time-domain ECG digital codes are converted into the spectrum results through the SDFT circuit, and then the time-frequency analysis is achieved. The proposed design is realized by using TSMC CMOS 0.18-µm technology. The proposed IA has 89dB CMRR and 88dB PSRR. Under a 1-kHz sampling rate, the SNDR and ENOB of the proposed SAR ADC are 58.8dB and 9.4bit. The chip area and total power consumption of analog circuit chip area are 1.599X1.146mm2, and 0.238mW, respectively. Under a 1-kHz operating frequency, the gate count, chip area, and power consumption of the proposed time-frequency processor are 73446, 1.151X1.141mm2, and 1.62μW, respectively. The time-frequency module compared with Krzysztof Duda’s method, the number of multiplication and addition are achieve 80.35% and 54.91% reducing, respectively. Therefore, the proposed platform can achieve low-complexity and area effectively. We believe it can help us to develop a portable and low-power detecting device in the future.
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Wang, Tzu Yun, and 王子昀. "The Design of Low-Power Reconfigurable Analog Sensing Front-End Circuits for Biomedical Applications." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/47mzna.

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Chen, Chun-Cheng, and 陳君政. "The Low-Power Integrated Circuit Design of A Reconfigurable 4-Channel Analog Front End for Biomedical Sensing Applications." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/n244n6.

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碩士
國立臺灣科技大學
電機工程系
105
This thesis presentslow-power integrated circuit design of a reconfigurable multi-channel analog sensing front end for biomedical applications. Each single channel consists of a biopotential sensing amplifier(LNA), a variable gain amplifier (VGA), and a linearized operationaltransconductance amplifier-capacitor(OTA-C) filter. The analog output signals from different channels are converted into digital format viaasuccessive approximationregisteranalog to digital converter(SAR ADC).By employingfloating-gate transistors and the relevant analog programming techniques, the analog sensing front-end circuits achieve features of low power, low noise and reconfigurability. Besides, to save the number of chip pins, serial-peripheral interface circuits are used to transmit the controls signals required for floating-gate programming and circuit calibration. The signal path can also be adjusted according to the demands of users. Moreover, the circuit layout are modulized so that the number of the sensing channels can be extended easily in the future. The integrated circuits presented in this these have been designed and fabricated in a TSMC 0.35mstandard CMOS process. The chip includes four channel analog sensing front-end and the circuits for floating-gate programming. From the measurements, when the bandwidth is programmed at 100Hz, the total current consumption for single channel is 50nA with input referred noise of 2.85 . The calculated noise efficiency factor (NEF) is 2.48 and the dynamic range is 46.24dB. When the bandwidth is increased to 1kHz, the current consumption becomes 634nA with input referred noise of 3.03 and NEF of 2.98 and dynamic range is 46.33dB. The measured number of effective bits from the employed SAR ADC is 5.9. Finally, the functionality of the chip is verified by a signal from an ECG simulator.
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Chen, Han-Chun, and 陳翰群. "Design of Voltage-Controlled-Oscillator-Based Continuous-Time Delta-Sigma Analog Front-End Circuit for Low Frequency Sensing Applications." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/vqu3cu.

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碩士
國立臺灣大學
電子工程學研究所
106
Sensor systems are becoming more and more important with the progress of IOT and AI. Besides, we hope to integrate whole sensors system which includes sensor interface circuit and digital processor in one chip. Therefore, this thesis focuses on the power and area efficient analog front end (AFE) design. Conventional sensor interface circuit consists of a low noise amplifier and an analog to digital converter (ADC). It is inefficient on both power consumption and area, and also complex to design. To solve the above problem, this thesis uses two voltage control oscillator (VCO) based circuits as the integrator and quantizer to implement the 2nd-order continuous time delta-sigma modulator (CTDSM), merging an ADC with the AFE. This thesis implements and measures the CTDSM in TSMC 180 nm CMOS process. This work uses a VCO and a counter as an integrator. Furthermore, we add another VCO with frequency-to-digital converter as a quantizer. Due to the first-order noise shaping characteristic of the second-stage. The whole loop shows second-order noise shaping. The second-stage quantizes the signal as a digital thermometer code with dynamic element matching (DEM), we do not need the dynamic weighted averaging (DWA). The core area of the chip is 0.19 mm2. This chip using sampling frequency at 1 MHz, with supply voltage of 1.2 V. This chip achieves the signal-to-noise-and-distortion-ratio of 62.5 dB. The power consumption of this chip is 52.4 μW, and the FoMs of the work is 143.7 dB. This chip meets bio-AFE requirement and is outstanding on power consumption and chip area.
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Conference papers on the topic "Analog front end design for compressed sensing"

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Charbiwala, Zainul, Paul Martin, and Mani B. Srivastava. "CapMux: A scalable analog front end for low power compressed sensing." In 2012 International Green Computing Conference (IGCC). IEEE, 2012. http://dx.doi.org/10.1109/igcc.2012.6322255.

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Kuo, Liang-Ting, Chun-Chih Hou, Meng-Hsuan Wu, and Yun-Shiang Shu. "A 1V 9pA analog front end with compressed sensing for electrocardiogram monitoring." In 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE, 2015. http://dx.doi.org/10.1109/asscc.2015.7387484.

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Mamaghanian, Hossein, and Pierre Vandergheynst. "Ultra-Low-Power ECG Front-End Design Based on Compressed Sensing." In Design, Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2015. http://dx.doi.org/10.7873/date.2015.1098.

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Shimeno, Yoichi. "Introduction of Analog Front End IC used in sensing system." In 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems". IEEE, 2017. http://dx.doi.org/10.23919/mixdes.2017.8004586.

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Chung, Wen-Yaw, Chung-Huang Yang, Kang-Chu Peng, and M. H. Yeh. "Low-voltage analog front-end processor design for ISFET-based sensor and H+ sensing applications." In AeroSense 2003, edited by Anthony J. Bell, Mladen V. Wickerhauser, and Harold H. Szu. SPIE, 2003. http://dx.doi.org/10.1117/12.508516.

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Park, Jiheon, Young-Ha Hwang, Jonghyun Oh, Yoonho Song, Jun-Eun Park, and Deog-Kyoon Jeong. "A Compact Self-Capacitance Sensing Analog Front-End for a Touch Detection in Low-Power Mode." In 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2019. http://dx.doi.org/10.1109/islped.2019.8824937.

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Liu, Xilin, Hongjie Zhu, Milin Zhang, Andrew G. Richardson, Timothy H. Lucas, and Jan Van der Spiegel. "Design of a low-noise, high power efficiency neural recording front-end with an integrated real-time compressed sensing unit." In 2015 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2015. http://dx.doi.org/10.1109/iscas.2015.7169317.

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Lin, Ying-Jia, Ying-Cheng Su, Paul C. P. Chao, Jia-Yu Zhang, and Eka Fitrah Pribadi. "Application of Code Division Multiple Access Technology in Readout Circuit and System Design for an Ultra-Thin On-Cell Flexible Capacitive Touch Panel." In ASME 2019 28th Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/isps2019-7522.

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Abstract A capacitive sensing circuit including electrodes for a 7-inch ultra-thin flexible on-cell touch panel has been designed. Implementing code-division multiple sensing (CDMS) with Walsh transform to scan Tx electrodes is chosen to improve the signal-to-noise ratio (SNR). The algorithm applies to field programmable logic array (FPGA). The sensing readout algorithm is applied to work on 4 Tx transmitter electrodes and 4 Rx sensing electrodes. The switched-capacitor (SC) circuit is applied to avoid disturbing sample signal from parasitic capacitance and enlarge the voltage difference from capacitance changes of the touch panel. 12-bit ADC to transfer the front-end analog signal to digital code. The digital part adopts a correction algorithm to eliminate the background value of the panel, the moving average algorithm has an adjustable signal-to-noise ratio function, and the Walsh conversion demodulation algorithm improves the touch report rate to achieve high SNR with up-to 34 dB.
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Pandey, Rajeev Kumar, Jerry Lin, and Paul C. P. Chao. "Design of a New Long-Time Continuous Photoplethysmography Signal Acquisition System to Obtain Accurate Measurement of Heart Rate." In ASME 2020 29th Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/isps2020-1916.

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Abstract This study presents a time-interleave and low DC drift long-time continuous photoplethysmography (PPG) signal acquisition system to obtain accurate measurement of heart rate (HR) in real-time. Time-interleave functionality is used herein to minimize the mispositioning issue. Intensity tuning and transimpedance amplifier gain tuning is used herein to acquire a high-quality PPG signal. The front-end analog readout circuit is designed and implemented by using T18 process. The experimental result shows that the design readout system has the DC settling time of 1 second after the motion artifact. The measured current sensing range is 30nA–10uA. The estimated signal to noise ratio is 68dB@1Hz. The backend pre-signal processing incorporates a new convolution-based moving average filter, signal quality index estimator, and a peak-through detector. The non-invasive PPG sensor is applied to the wrist artery of the 40 healthy subjects for sensing the pulsation of the blood vessel. During the measurement, the subject did not drink (alcohol), eat, smoke or workout. The Measurement results shows that the heart rate accuracy and standard error are 95%, and 0.37±1.96bpm, respectively.
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