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Journal articles on the topic 'Analog Integrated Circuit Design'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Hurst, Stanley L. "Analog integrated circuit design." Microelectronics Journal 29, no. 6 (1998): 361–62. http://dx.doi.org/10.1016/s0026-2692(97)00051-7.

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2

Gao, Sirui. "Analog integrated circuit design with machine learning." Theoretical and Natural Science 5, no. 1 (2023): 788–95. http://dx.doi.org/10.54254/2753-8818/5/20230495.

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Due to the widespread application of semiconductor technology in integrated circuits, more and more design studies on analog integrated circuits are gradually being implemented. However, due to the nature of analog integrated circuits, it is time-consuming and inefficient. Therefore, there are lots of experts studying how to reduce the design cycle of analog ICs. The use of machine learning in analog circuits stands out, as machine learning-based design methods have significantly reduced the analog cycle time. This review report will first introduce the algorithms related to machine learning,

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3

WANG, WEIZHI, and DONGMING JIN. "CMOS DESIGN OF ANALOG FUZZY SYSTEM." Journal of Circuits, Systems and Computers 14, no. 06 (2005): 1101–12. http://dx.doi.org/10.1142/s0218126605002830.

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This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high p

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4

Johns, D. A., K. Martin, and J. Wiley. "Analog integrated circuit design [Book Review]." IEEE Circuits and Devices Magazine 16, no. 5 (2000): 39–40. http://dx.doi.org/10.1109/mcd.2000.876905.

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5

Ravender, Goyal, and Dragiša P. Milovanović. "High-frequency analog integrated circuit design." Microelectronics Reliability 37, no. 5 (1997): 873. http://dx.doi.org/10.1016/s0026-2714(96)00280-6.

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Milovanović, Dragiša P. "High-frequency analog integrated circuit design." Microelectronics Journal 28, no. 5 (1997): 598. http://dx.doi.org/10.1016/s0026-2692(97)80953-6.

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7

Mina, Rayan, Chadi Jabbour, and George E. Sakr. "A Review of Machine Learning Techniques in Analog Integrated Circuit Design Automation." Electronics 11, no. 3 (2022): 435. http://dx.doi.org/10.3390/electronics11030435.

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Analog integrated circuit design is widely considered a time-consuming task due to the acute dependence of analog performance on the transistors’ and passives’ dimensions. An important research effort has been conducted in the past decade to reduce the front-end design cycles of analog circuits by means of various automation approaches. On the other hand, the significant progress in high-performance computing hardware has made machine learning an attractive and accessible solution for everyone. The objectives of this paper were: (1) to provide a comprehensive overview of the existing state-of-

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8

Sharroush, Sherif. "Analog CMOS Design in Nanometer Regime." Jordan Journal of Electrical Engineering 10, no. 4 (2024): 1. http://dx.doi.org/10.5455/jjee.204-1703756483.

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There is no doubt that the short-channel effects have affected the analysis and design of modern analog CMOS integrated circuits significantly. Thus, models that take into account these effects must be adopted in order to obtain more accurate results. In this paper, the AC small-signal low-frequency equivalent circuit of the short-channel MOSFET transistor is developed using an appropriate model. The impact of short-channel effects on the operation of basic building blocks of analog integrated circuits such as basic amplifier configurations, cascode stage, differential amplifier and composite

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9

Mavor, J. "Bipolar and MOS Analog Integrated Circuit Design." Electronics and Power 31, no. 2 (1985): 164. http://dx.doi.org/10.1049/ep.1985.0109.

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Pennock, J. L. "Bipolar and MOS Analog Integrated Circuit Design." IEE Proceedings G (Electronic Circuits and Systems) 132, no. 2 (1985): 71. http://dx.doi.org/10.1049/ip-g-1.1985.0016.

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11

Kavya Gaddipati. "Navigating the Architectural Shift: RibbonFET Implementation Strategies for Next-Generation Analog Integrated Circuits." Journal of Computer Science and Technology Studies 7, no. 3 (2025): 616–23. https://doi.org/10.32996/jcsts.2025.7.3.70.

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This article explores the transformative shift from FinFET to RibbonFET (Gate-All-Around) transistor architecture in semiconductor technology, with a specific focus on analog integrated circuit design implications. The article analyzes the fundamental structural advantages of RibbonFET technology, highlighting its enhanced electrostatic control, performance improvements, and scaling benefits compared to traditional FinFET designs. Detailed considerations of layout techniques for analog applications are presented, including device structure adaptations, parasitic management strategies, and matc

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12

Takai, Nobukazu. "Realization of a design-less system for analog integrated circuits." Impact 2020, no. 1 (2020): 9–11. http://dx.doi.org/10.21820/23987073.2020.1.9.

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The 21st century has given rise to a digital world which has significantly impacted on the ways in which humans go about their everyday lives. From being able to speak with whomever you want, whenever you want, wherever you are on your smartphone, to tapping away on your laptop, through to spending hours each day on the internet, the world we live in is firmly digital and it now shapes the way we experience life. When it comes to circuits, analog still has a hugely important role to play. Circuit designer Associate Professor Nobukazu Takai is leading a team of researchers who are applying mach

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13

Hu, Wenxing, Xianke Zhan, and Minglei Tong. "Parsing Netlists of Integrated Circuits from Images via Graph Attention Network." Sensors 24, no. 1 (2023): 227. http://dx.doi.org/10.3390/s24010227.

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A massive number of paper documents that include important information such as circuit schematics can be converted into digital documents by optical sensors like scanners or digital cameras. However, extracting the netlists of analog circuits from digital documents is an exceptionally challenging task. This process aids enterprises in digitizing paper-based circuit diagrams, enabling the reuse of analog circuit designs and the automatic generation of datasets required for intelligent design models in this domain. This paper introduces a bottom-up graph encoding model aimed at automatically par

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14

ANTREICH, KURT J., HELMUT E. GRAEB, and CLAUDIA U. WIESER. "PRACTICAL METHODS FOR WORST-CASE AND YIELD ANALYSIS OF ANALOG INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 04, no. 03 (1993): 261–82. http://dx.doi.org/10.1142/s0129156493000121.

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Worst-case analysis is commonly used in integrated circuit design to verify a satisfactory circuit performance with regard to changes in the manufacturing conditions. However, worst-case analysis is often carried out using approximate worst-case parameter sets. This paper presents a new approach to the worst-case design of integrated circuits that takes account of fluctuations in the operating conditions. It provides exact and unique worst-case manufacturing conditions and worst-case operating conditions for given circuit specifications. These specifications may be either performance limits or

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Kobayashi, Haruo, and Anna Kuwana. "Study of analog-to-digital mixed integrated circuit configuration using number theory." Impact 2022, no. 3 (2022): 9–11. http://dx.doi.org/10.21820/23987073.2022.3.9.

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Electronic circuits form the basis of much of the technology we use today. Professor Haruo Kobayashi and Assistant Professor Anna Kuwana, Division of Electronics and Informatics, Gunma University, Japan, are utilising classical mathematics, including theorems such as number theory and control theory in their design of circuits that contain elements of analogue signalling. Analogue circuit planning is regarded as an art as these circuits are typically designed based on mature designers' intuition and experiences in a process that is less systematic for coming up with new architectures and more

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Richelli, Anna. "Low-Voltage Integrated Circuits Design and Application." Electronics 10, no. 1 (2021): 89. http://dx.doi.org/10.3390/electronics10010089.

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One of the most challenging tasks for analog and digital designers is to maintain the circuit performances by developing novel circuit structures, robust, reliable, and capable of operating with low supply voltage [...]

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17

Martins, Ricardo. "Closing the Gap Between Electrical and Physical Design Steps with an Analog IC Placement Optimizer Enhanced with Machine-Learning-Based Post-Layout Performance Regressors." Electronics 13, no. 22 (2024): 4360. http://dx.doi.org/10.3390/electronics13224360.

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The design of integrated circuits in the analog spectrum is intricate due to the signals’ continuous nature. Additionally, it is strongly affected by the physical implementation of their devices and interconnections on the layout, a design task that has stubbornly defied all automation attempts. In this paper, one limitative factor is identified that must be addressed to finally push automation tools into the analog integrated circuit design flow: accurate assessment of post-layout performance degradation. For this purpose, a performance-driven placement generator highly integrated with off-th

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Song, Jierui. "The Research of Integrated Circuit Design Technology." Advances in Engineering Technology Research 4, no. 1 (2023): 519. http://dx.doi.org/10.56028/aetr.4.1.519.2023.

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This article discusses the fundamentals of analogue integrated circuit design and construction, as well as the operation and some basic models of MOS transistors. It also provides a thorough introduction to the CMOS, PMOS, and NMOS structures, as well as the benefits and drawbacks of each. Additionally, operational and differential amplifiers are introduced, along with some examples of their uses. While attending summer school, I also learned how to simulate the SPEICE model using the computer program CoolSPICE. The SPEICE model is a literal description of a circuit component that theoreticall

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Yang, Yunqi, Jiaming Su, Xiaoran Lai, Dongdong Chen, Di Li, and Yintang Yang. "Recent Developments and Perspectives on Optimization Design Methods for Analog Integrated Circuits." Symmetry 17, no. 4 (2025): 529. https://doi.org/10.3390/sym17040529.

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As the cornerstone of the modern information industry, designing a high-performance circuit is crucial. Due to the influence of external environmental and asymmetric arrangements, non-ideal factors in analog integrated circuits (ICs) cannot be ignored, which makes the design process heavily reliant on human experience, and the design efficiency is low. Recently, scholars have conducted extensive research on optimization design methods for analog ICs by combining artificial intelligence and optimization algorithms. In this article, the developments and perspectives on optimization design method

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20

Sanabria-Borbón, Adriana, Sergio Soto-Aguilar, Johan Estrada-López, Douglas Allaire, and Edgar Sánchez-Sinencio. "Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design." Electronics 9, no. 4 (2020): 685. http://dx.doi.org/10.3390/electronics9040685.

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Optimization algorithms have been successfully applied to the automatic design of analog integrated circuits. However, many of the existing solutions rely on expensive circuit simulations or use fully customized surrogate models for each particular circuit and technology. Therefore, the development of an easily adaptable low-cost and efficient tool that guarantees resiliency to variations of the resulting design, remains an open research area. In this work, we propose a computationally low-cost surrogate model for multi-objective optimization-based automated analog integrated circuit (IC) desi

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21

Rakús, Matej, Viera Stopjaková, and Daniel Arbet. "Design techniques for low-voltage analog integrated circuits." Journal of Electrical Engineering 68, no. 4 (2017): 245–55. http://dx.doi.org/10.1515/jee-2017-0036.

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AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or

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22

L. Bharvad, Sureshbhai, Pankaj P. Prajapati, and Anilkumar J. Kshatriya. "META HEURISTIC OPTIMIZATION APPROACH FOR CMOS BASED ANALOG CIRCUIT DESIGN AND PERFORMANCE EVALUATION OF EVOLUTIONARY ALGORITHMS." ICTACT Journal on Soft Computing 13, no. 2 (2023): 2827–41. https://doi.org/10.21917/ijsc.2023.0402.

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Manual design of Complementary Metal Oxide Semiconductor (CMOS) based analog circuit design becomes more challenging and tedious task due to very complex physical models and variation in the fabrication process as technology scale down. In this continuously changing era, the demand of mixed signal System on Chip (SoC) increasing day by day which digital and analog circuits integrated on same silicon chip. For the digital circuit design, many mature computer based automated tools have been established and limited research efforts made towards automization of the analog circuit design. This gap

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23

Younis, Ahmad T., and Emad Abd Al Halem. "Genetic algorithm application to analog integrated circuit design." International Journal of Reasoning-based Intelligent Systems 4, no. 4 (2012): 209. http://dx.doi.org/10.1504/ijris.2012.051721.

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24

Feng, Chang Jiang, Bing Xue, and Ze Jian Zhang. "A Method for Analog Integrated Circuit Embedded Self-Test." Advanced Materials Research 816-817 (September 2013): 1069–72. http://dx.doi.org/10.4028/www.scientific.net/amr.816-817.1069.

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Aimed at the embedded analog integrated circuit chip, a research for the analog integrated circuit self-test is presented in this paper. As an embedded test system, one of the key factors is to minimize the resources occupation rate besides completing the test task. The principle of this study is to simplify the scale of the test circuit, in order to reduce the hardware cost of the analog integrated circuit performance test as much as possible. The idea is like this: sending the impulse signal as the excitation to the under test circuit and transforming its response signals into digital. Thus,

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25

Alahdal, Abdulrahman, Anis Ammous, and Kaiçar Ammous. "Design and realization of an analog integrated circuit for maximum power point tracking of photovoltaic panels." EPJ Photovoltaics 13 (2022): 6. http://dx.doi.org/10.1051/epjpv/2022002.

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The tracking of the maximum power point (MPP) of a photovoltaic (PV) solar panel is an important part of a PV generation chain. In order to track maximum power from the solar arrays, it is necessary to control the output impedance of the PV panel, so that the circuit can be operated at its Maximum Power Point (MPP), despite the unavoidable changes in the climate conditions such as temperature and Irradiance. A new MPPT analog technique to track the Maximum Power Point (MPP) of PV arrays is proposed. This new technique uses simple and classical functions of electronic circuits. An Off-Grid PV s

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26

Chen, Ethan, and Vanessa Chen. "Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications." Mathematics 8, no. 5 (2020): 829. http://dx.doi.org/10.3390/math8050829.

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While integrated circuit technologies keep scaling aggressively, analog, mixed-signal, and radio-frequency (RF) circuits encounter challenges by creating robust designs in advanced complementary metal–oxide–semiconductor (CMOS) processes with the diminishing voltage headroom. The increasing random mismatch of smaller feature sizes in leading-edge technology nodes severely limit the benefits of scaling for (RF)/analog circuits. This paper describes the details of the combinatorial randomness by statistically selecting device elements that relies on the significant growth in subsets number of co

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27

Hoang, Trang, Bao Quoc Bui, Hoang Trong Nguyen, and Phuc That Bao Ton. "Evolutionary Optimization Techniques in Analog Integrated Circuit Designs." MENDEL 29, no. 2 (2023): 245–54. http://dx.doi.org/10.13164/mendel.2023.2.245.

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The proposed genetic algorithm (GA) and particle swarm optimization (PSO) applied for the optimal design of a one-stage operational amplifier circuit with a current mirror load are studied in this work. The sizes of transistors are optimized using the proposed GA and PSO for improved areas and performance parameters of the circuit. A number of performance parameters are collected from the data set created by GA and PSO to optimize the size of transistors and other design parameters. The Spectre simulator is chosen for the simulation of circuit parameters to obtain necessary for the GA and PSO

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Maralani, A., Michael S. Mazzola, David C. Sheridan, Igor Sankin, and Volodymyr Bondarenko. "Characterization and Modeling of SiC LTJFET for Analog Integrated Circuit Simulation and Design." Materials Science Forum 615-617 (March 2009): 915–18. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.915.

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The design of analog integrated circuits, for instance, the operational amplifiers, have been widely perfected with devices and processes available in silicon. However, analogous circuits have been the subject of research in Silicon Carbide (SiC). Among SiC devices, 4H-SiC Lateral-Trench JFET (LTJFET) transistor offers advantages and new opportunities to make affordable and reliable analog integrated circuits for harsh environment. In this paper: (1) SiC LTJFET is characterized for modeling and simulation, (2) effect of temperature variation on SiC LTJFET threshold voltage and small signal par

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29

Prajapati, Pankaj P., and Mihir V. Shah. "Automatic Circuit Design of CMOS Miller OTA Using Cuckoo Search Algorithm." International Journal of Applied Metaheuristic Computing 11, no. 1 (2020): 36–44. http://dx.doi.org/10.4018/ijamc.2020010103.

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The circuit design of the CMOS based analog part of a mixed-signal integrated circuit (IC) needs a large fraction of the overall design cycle time. The automatic design of an analog circuit is inevitable, seeing recently development of System-on-Chip (SOC) design. This brings about the need to develop computer aided design (CAD) tools for automatic design of CMOS based analog circuits. In this article, a Cuckoo Search (CS) algorithm is presented for automatic design of a CMOS Miller Operational Transconductance Amplifier (OTA). The source code of the CS algorithm is developed using the C langu

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30

Harshada Suresh Thorat. "Review on the Design of Meminductor Emulator Using Analog Building Blocks." Journal of Information Systems Engineering and Management 10, no. 24s (2025): 474–503. https://doi.org/10.52783/jisem.v10i24s.3924.

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The advent of meminductors as a basic passive circuit element has sparked widespread attention because of their potential uses in neuromorphic computing, memory storage, and programmable analog circuits. This study gives a detailed assessment of design techniques for meminductor emulators, emphasizing current-mode components. Current-mode circuits provide benefits such as fast operation, low power consumption, and a greater dynamic range, making them an excellent option for meminductor emulator design. The study categorizes and analyzes current designs based on their fundamental ideas, circuit

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31

Nguyen, Hoang Trong, and Trang Hoang. "A Novel Framework of Genetic Algorithm and Spectre to Optimize Delay and Power Consumption in Designing Dynamic Comparators." Electronics 12, no. 16 (2023): 3392. http://dx.doi.org/10.3390/electronics12163392.

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In integrated circuit (IC) design, analog circuits contribute significantly as the interface between real and digital world signals. Although they make up a relatively small portion of the overall circuit, their design process is often most time-consuming, mostly from the phase of manual iteration of circuit parameters to meet design specifications. Therefore, the design automation of analog circuits with the help of efficient optimization techniques arises as a promising candidate to address the issue. Among optimization algorithms, while the genetic algorithm (GA) has been shown to be effect

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32

Ma, Yujie. "The Application of Secondary Effects in Optimizing Analog Circuits." Applied and Computational Engineering 103, no. 1 (2024): 50–56. http://dx.doi.org/10.54254/2755-2721/103/20241074.

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Abstract. This study delves into the application of secondary effects, specifically body effect, channel length modulation effect, and subthreshold conduction effect, in the optimization of analog integrated circuits. The research highlights the critical role these effects play in modern circuit design, especially as device dimensions continue to shrink. Through a systematic analysis, the study presents key strategies for mitigating these effects to enhance circuit performance, reliability, and power efficiency. Notably, the implementation of a transient BD scheme in partially analog-assisted

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33

BŰRMEN, ÁRPÁD, TADEJ TUMA, and IZTOK FAJFAR. "A COMBINED SIMPLEX–TRUST-REGION METHOD FOR ANALOG CIRCUIT OPTIMIZATION." Journal of Circuits, Systems and Computers 17, no. 01 (2008): 123–40. http://dx.doi.org/10.1142/s0218126608004125.

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The analog-integrated circuits industry is exerting increasing pressure to shorten the analog circuit design time. This pressure is put primarily on the analog circuit designers that in turn demand automated circuit design tools evermore vigorously. Such tools already exist in the form of circuit optimization software packages but they all suffer a common ailment — slow convergence. Even taking into account the increasing computational power of modern computers the convergence times of such optimization tools can range from a few days to even weeks. Different authors have tried diverse approac

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34

Barari, Mansour, Hamid Reza Karimi, and Farhad Razaghian. "Analog Circuit Design Optimization Based on Evolutionary Algorithms." Mathematical Problems in Engineering 2014 (2014): 1–12. http://dx.doi.org/10.1155/2014/593684.

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This paper investigates an evolutionary-based designing system for automated sizing of analog integrated circuits (ICs). Two evolutionary algorithms, genetic algorithm and PSO (Parswal particle swarm optimization) algorithm, are proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through specific electrical simulation, to the optimization system in the MATLAB environment, for the selected topology. The system has been tested by typical and hard-to-design cases, such as c

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35

Smith, M. J. S., C. Portmann, R. Jorgenson, et al. "Analog CMOS integrated circuit design: research and undergraduate teaching." IEEE Transactions on Education 32, no. 3 (1989): 210–17. http://dx.doi.org/10.1109/13.34152.

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36

Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.

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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to

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Kiela, Karolis, and Romualdas Navickas. "AUTOMATED INTEGRATED ANALOG FILTER DESIGN ISSUES / AUTOMATIZUOTOJO INTEGRINIŲ ANALOGINIŲ FILTRŲ PROJEKTAVIMO YPATUMAI." Mokslas – Lietuvos ateitis 7, no. 3 (2015): 323–29. http://dx.doi.org/10.3846/mla.2015.793.

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An analysis of modern automated integrated analog circuits design methods and their use in integrated filter design is done. Current modern analog circuits automated tools are based on optimization algorithms and/or new circuit generation methods. Most automated integrated filter design methods are only suited to gmC and switched current filter topologies. Here, an algorithm for an active RC integrated filter design is proposed, that can be used in automated filter designs. The algorithm is tested by designing an integrated active RC filter in a 65 nm CMOS technology. Atlikta naujausių integri

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Hu, Zihao. "Applications of Op-Amp in Automatic Circuit Design." Applied and Computational Engineering 126, no. 1 (2025): 169–75. https://doi.org/10.54254/2755-2721/2025.20133.

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Operational amplifiers (op-amps) are widely used in automatic circuits. It can amplify, filter, sum, integrate and differentiate the voltage, current and power, and it is one of the indispensable key components in modern electronic technology. The paper, through a method of literature review, explores the working principle and usage of operational amplifiers. Initially, the paper introduces the basic concepts and principles of operational amplifiers, laying a theoretical foundation for subsequent analysis. Then, it meticulously analyzes typical applications of operational amplifiers in analog

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Wang, Hao, Wei Yang, Ben Hong Li, Xiao Chu Liu, and Quan Peng He. "Design and Simulation Analysis of the Mirror Current Source Circuit Based on Multisim10." Applied Mechanics and Materials 596 (July 2014): 723–26. http://dx.doi.org/10.4028/www.scientific.net/amm.596.723.

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The mirror current source, with the characteristics of small static resistance and dynamic resistance, has been widely used in the analog integrated circuits, commonly used as a bias circuit and active load [1]. Aiming to the problem of the output signal waveform saturation distortion, which caused by the drift effect when the temperature rises in the fixed bias circuit, this paper provides a circuit design of replacing the collector load resistance of by the mirror current source and carrying out simulation analysis by multisim10 software, compared with the theoretical calculation to verify t

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Hu, Jian-Guo, Wen-Zhuo Mei, Jin Wu, Jia-Wei Li, and De-Ming Wang. "A Fully Integrated RFID Reader SoC." Micromachines 14, no. 9 (2023): 1691. http://dx.doi.org/10.3390/mi14091691.

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The traditional RFID reader module relies on a discrete original design. This design integrates a microcontroller, high-frequency RFID reader IC and other multiple chips onto a PCB board, leading to bottlenecks in cost, power consumption, stability and reliability. To align with the trend towards high integration, miniaturization and low power consumption in RFID reader, this paper introduces a fully integrated RFID Reader SoC. The SoC employs the open-source Cortex-M0 core to integrate the RF transceiver, analog circuits, baseband protocol processing, memory and interface circuits into one ch

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Kanazawa, Yusuke, Tetsuya Asai, and Yoshihito Amemiya. "Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses." Journal of Robotics and Mechatronics 15, no. 2 (2003): 208–18. http://dx.doi.org/10.20965/jrm.2003.p0208.

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We discuss the integration architecture of spiking neurons, predicted to be next-generation basic circuits of neural processor and dynamic synapse circuits. A key to development of a brain-like processor is to learn from the brain. Learning from the brain, we try to develop circuits implementing neuron and synapse functions while enabling large-scale integration, so large-scale integrated circuits (LSIs) realize functional behavior of neural networks. With such VLSI, we try to construct a large-scale neural network on a single semiconductor chip. With circuit integration now reaching micron le

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Richelli, Anna, Paolo Faustini, Andrea Rosa, and Luigi Colalongo. "An Investigation of the Operating Principles and Power Consumption of Digital-Based Analog Amplifiers." Journal of Low Power Electronics and Applications 13, no. 3 (2023): 51. http://dx.doi.org/10.3390/jlpea13030051.

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Digital-based differential amplifiers (DDA) are particularly suitable to low voltage digital integrated circuit technologies. This paper presents an exhaustive analysis of digital-based analog amplifiers to take advantage of today’s high-performance digital technologies, and of computer aided design (CAD), which is commonly employed to design integrated circuits. The operating principle and the main mathematical relations of digital-based differential amplifiers are discussed along with an exhaustive explanation of its operating regions and of the corresponding power consumption. These aspects

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Deeb, Ali, Abdalrahman Ibrahim, Mohamed Salem, et al. "A Robust Automated Analog Circuits Classification Involving a Graph Neural Network and a Novel Data Augmentation Strategy." Sensors 23, no. 6 (2023): 2989. http://dx.doi.org/10.3390/s23062989.

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Analog mixed-signal (AMS) verification is one of the essential tasks in the development process of modern systems-on-chip (SoC). Most parts of the AMS verification flow are already automated, except for stimuli generation, which has been performed manually. It is thus challenging and time-consuming. Hence, automation is a necessity. To generate stimuli, subcircuits or subblocks of a given analog circuit module should be identified/classified. However, there currently needs to be a reliable industrial tool that can automatically identify/classify analog sub-circuits (eventually in the frame of

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Yang, Yating, Zheng Li, Mingyang Liu, et al. "Design of a Wide-Range and High-Precision Analog Front-End Circuit for Multi-Parameter Sensors." Electronics 12, no. 13 (2023): 2962. http://dx.doi.org/10.3390/electronics12132962.

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This article presents a wide-range and high-precision analog front-end circuit for multi-parameter sensors that can handle sensor outputs of different types (R, C, V). A rail-to-rail baseline compensation method has been proposed, which further incorporates a fine offset elimination of 0.6 mV/step. Additionally, self-zeroing and correlated double-sampling techniques are integrated to reduce low-frequency noise and offset, prevent sensor signal saturation, and enhance the precision of the analog front-end circuit. By incorporating variable components in the sensor signal acquisition circuit and

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Liu, Yuanhao, and Lan Dai. "Design of 1G/S 10 bit current steering analog-to-digital converter." Journal of Physics: Conference Series 3046, no. 1 (2025): 012004. https://doi.org/10.1088/1742-6596/3046/1/012004.

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Abstract Since the beginning of the 21st century, the integrated circuit (IC) market has developed rapidly, and digital to analog converters (DAC) urgently need to improve their performance to adapt to the rapid development of the market. This article designs a segmented current steering digital to analog converter with a sampling rate of 1 G/S and a resolution of 10. The main structure adopts a 2+4+4 segmented approach, where the analog and digital parts are powered by 2.5 V and 1.8 V power supplies, respectively. This architecture is based on the tsmcN65 process to complete the overall circu

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Chen, Zhifeng, Jiming Chen, Wenli Liao, Yuan Zhao, Jianhua Jiang, and Chengying Chen. "Progress on a Carbon Nanotube Field-Effect Transistor Integrated Circuit: State of the Art, Challenges, and Evolution." Micromachines 15, no. 7 (2024): 817. http://dx.doi.org/10.3390/mi15070817.

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As the traditional silicon-based CMOS technology advances into the nanoscale stage, approaching its physical limits, the Carbon Nanotube Field-effect Transistor (CNTFET) is considered to be the most significant transistor technology beyond Moore’s era. The CNTFET has a quasi-one-dimensional structure so that the carrier can realize ballistic transport and has very high mobility. At the same time, a single CNTFET can integrate hundreds of nanowires as the conductive channels, enabling significant current transport capabilities even in low supply voltage, thereby providing a foundational basis f

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ALARCÓN, EDUARD, GERARD VILLAR, and ALBERTO POVEDA. "CMOS INTEGRATED CIRCUIT CONTROLLERS FOR SWITCHING POWER CONVERTERS." Journal of Circuits, Systems and Computers 13, no. 04 (2004): 789–811. http://dx.doi.org/10.1142/s0218126604001714.

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Two case examples of high-speed CMOS microelectronic implementations of high-performance controllers for switching power converters are presented. The design and implementation of a current-programmed controller and a general-purpose feedforward one-cycle controller are described. The integrated circuit controllers attain high-performance by means of using current-mode analog signal processing, hence allowing high switching frequencies that extend the operation margin compared to previous designs. Global layout-extracted transistor-level simulation results for 0.8 μm and 0.35 μm standard CMOS

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Cam Taskiran, Zehra Gulru, Murat Taşkıran, Mehmet Kıllıoğlu, Nihan Kahraman, and Herman Sedef. "A novel memristive true random number generator design." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 38, no. 6 (2019): 1931–47. http://dx.doi.org/10.1108/compel-11-2018-0463.

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Purpose In this work, a true random number generator is designed by sampling the double-scroll analog continuous-time chaotic circuit signals. Methodology A Chua circuit based on memristance simulator is designed to obtain a non-linear term for a chaotic dynamic system. It is implemented on the board by using commercially available integrated circuits and passive elements. A low precision ADC which is commonly found in the market is used to sample the chaotic signals. The mathematical analysis of the chaotic circuit is verified by experimental results. Originality It is aimed to be one of the

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Redoute, Jean-Michel, and Anna Richelli. "A methodological approach to EMI resistant analog integrated circuit design." IEEE Electromagnetic Compatibility Magazine 4, no. 2 (2015): 92–100. http://dx.doi.org/10.1109/memc.2015.7204058.

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Gusmão, António, Pedro Alves, Nuno Horta, Nuno Lourenço, and Ricardo Martins. "Differentiable Constraints’ Encoding for Gradient-Based Analog Integrated Circuit Placement Optimization." Electronics 12, no. 1 (2022): 110. http://dx.doi.org/10.3390/electronics12010110.

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Analog IC design is characterized by non-systematic re-design iterations, often requiring partial or complete layout re-design. The layout task usually starts with device placement, where the several performance figures and constraints to be met escalate its complexity immensely, and, due to the inherent tradeoffs, an “optimal” floorplan solution does not usually exist. Deep learning models are now establishing for the automation of the placement task of analog integrated circuit layout design, promising to bypass the limitations of existing approaches based on: time-consuming optimization pro

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