Relevant bibliographies by topics / Analog IP Test

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Analog IP Test'

Author: Grafiati
Published: 4 June 2021
Last updated: 7 September 2023

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Journal articles on the topic "Analog IP Test"

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Hasler, Jennifer, Aishwarya Natarajan, and Sihwan Kim. "Enabling Energy-Efficient Physical Computing through Analog Abstraction and IP Reuse." Journal of Low Power Electronics and Applications 8, no. 4 (November 24, 2018): 47. http://dx.doi.org/10.3390/jlpea8040047.

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This paper shows the first step in analog (and mixed signal) abstraction utilized in large-scale Field Programmable Analog Arrays (FPAA), encoded in the open-source SciLab/Xcos based toolset. Having any opportunity of a wide-scale utilization of ultra-low power technology both requires programmability/reconfigurability as well as abstractable tools. Abstraction is essential both make systems rapidly, as well as reduce the barrier for a number of users to use ultra-low power physical computing techniques. Analog devices, circuits, and systems are abstractable and retain their energy efficient opportunities compared with custom digital hardware. We will present the analog (and mixed signal) abstraction developed for the open-source toolkit used for the SoC FPAAs. Abstraction of Blocks in the FPAA block library makes the SoC FPAA ecosystem accessible to system-level designers while still enabling circuit designers the freedom to build at a low level. Multiple working test cases of various levels of complexity illustrate the analog abstraction capability. The FPAA block library provides a starting point for discussing the fundamental block concepts of analog computational approaches.
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Wei, Shu Hua, Lan Dai, Xiao Bo Zhang, and Yan Feng Jiang. "Efficient and Accurate Testing of On-Chip ADC Based on ATE." Applied Mechanics and Materials 380-384 (August 2013): 3378–81. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3378.

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The embedded digital-analog mixed-signal circuit testing has become one of the difficulties to be solved. In this paper, a SoC embedded ADC has been tested based on the Credence Gemini500 verification system. The testing method is studied and verified through the test experiment and results. This testing method is an important reference for general embedded IP core testing.
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Nagarajan, Karthikeyan, Rupshali Roy, Rasit Onur Topaloglu, Sachhidh Kannan, and Swaroop Ghosh. "SCANN: Side Channel Analysis of Spiking Neural Networks." Cryptography 7, no. 2 (March 27, 2023): 17. http://dx.doi.org/10.3390/cryptography7020017.

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Spiking neural networks (SNNs) are quickly gaining traction as a viable alternative to deep neural networks (DNNs). Compared to DNNs, SNNs are computationally more powerful and energy efficient. The design metrics (synaptic weights, membrane threshold, etc.) chosen for such SNN architectures are often proprietary and constitute confidential intellectual property (IP). Our study indicates that SNN architectures implemented using conventional analog neurons are susceptible to side channel attack (SCA). Unlike the conventional SCAs that are aimed to leak private keys from cryptographic implementations, SCANN (SCA̲ of spiking n̲eural n̲etworks) can reveal the sensitive IP implemented within the SNN through the power side channel. We demonstrate eight unique SCANN attacks by taking a common analog neuron (axon hillock neuron) as the test case. We chose this particular model since it is biologically plausible and is hence a good fit for SNNs. Simulation results indicate that different synaptic weights, neurons/layer, neuron membrane thresholds, and neuron capacitor sizes (which are the building blocks of SNN) yield distinct power and spike timing signatures, making them vulnerable to SCA. We show that an adversary can use templates (using foundry-calibrated simulations or fabricating known design parameters in test chips) and analysis to identify the specifications of the implemented SNN.
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ARYANTA, DWI, ARSYAD RAMADHAN DARLIS, and ARDHIANSYAH PRATAMA. "Implementasi Sistem IP PBX menggunakan Briker." ELKOMIKA: Jurnal Teknik Energi Elektrik, Teknik Telekomunikasi, & Teknik Elektronika 1, no. 2 (July 1, 2013): 117. http://dx.doi.org/10.26760/elkomika.v1i2.117.

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ABSTRAKVoIP (Voice over Internet Protocol) adalah komunikasi suara jarak jauh yang digunakan melalui jaringan IP. Pada penelitian ini dirancang sistem IP PBX dengan menggunakan teknologi berbasis VoIP. IP PBX adalah perangkat switching komunikasi telepon dan data berbasis teknologi Internet Protocol (IP) yang mengendalikan ekstension telepon analog maupun ekstension IP Phone. Software VirtualBox digunakan dengan tujuan agar lebih memudahkan dalam sistem pengoperasian Linux yang dimana program untuk membuat IP PBX adalah menggunakan Briker yang bekerja pada Operating System Linux 2.6. Setelah proses penginstalan Briker pada Virtualbox dilakukan implementasi jaringan IP PBX. Setelah mengimplementasikan jaringan IP PBX sesuai dengan topologi, kemudian melakukan pengujian success call rate dan analisis Quality of Service (QoS). Pengukuran QoS menggunakan parameter jitter, delay, dan packet loss yang dihasilkan dalam sistem IP PBX ini. Nilai jitter sesama user Briker (baik pada smartphone maupun komputer) mempunyai rata-rata berada pada nilai 16,77 ms. Sedangkan nilai packetloss yang didapat pada saat terdapat pada saat user 1 sebagai pemanggil telepon adalah 0%. Sedangkan persentase packet loss pada saat user 1 sebagai penerima telepon adalah 0,01%. Nilai delay pada saat berkomunikasi antar user berada pada 11,75 ms. Secara keseluruhan nilai yang didapatkan melalui penelitian ini, dimana hasil pengujian parameter-parameter QOS sesuai dengan standar yang telah direkomendasikan oleh ITU dan didapatkan nilai QoS dengan hasil “baik”.Kata Kunci: Briker, VoIP, QoS, IP PBX, Smartphone.ABSTRACTVoIP (Voice over Internet Protocol) is a long-distance voice communications over IP networks are used. In this study, IP PBX systems designed using VoIP -based technologies. IP PBX is a telephone switching device and data communication technology-based Internet Protocol (IP) which controls the analog phone extensions and IP Phone extensions. VirtualBox software is used in order to make it easier for the Linux operating system to create a program which is using briker IP PBX that works on Linux 2.6 Operating System. After the installation process is done briker on Virtualbox IP PBX network implementation. After implementing the IP PBX network according to the topology, and then do a test call success rate and analysis of Quality of Service (QoS). Measurement of QoS parameters using jitter, delay, and packet loss resulting in the IP PBX system. Jitter value briker fellow users (either on a smartphone or computer) has been on the average value of 16.77 ms. While the values obtained packetloss when there is 1 user when a phone caller is 0%. While the percentage of packet loss at user 1 as a telephone receiver is 0.01%. Delay value when communicating between users located at 11.75 ms. Overall value obtained through this study , where the results of testing the QOS parameters in accordance with the standards recommended by the ITU and the QoS values obtained with the results "good".Keywords: Briker, VoIP, QoS, IP PBX, Smartphone.
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Muthoharo, Muthoharo, Martono Dwi Atmadja, and Abdul Rasyid. "Analysis Of Voice Quality on Aircraft Telephone Through Internet Telephony Gateway in Voice Over Internet Protocol." Jurnal Jartel Jurnal Jaringan Telekomunikasi 12, no. 2 (June 29, 2022): 80–84. http://dx.doi.org/10.33795/jartel.v12i2.309.

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Along with the development of the era, analog telephones have been replaced by IP Phones whose communication range can be wider and more flexible. Therefore, analog telephones are almost forgotten because of the limited communication range. With the addition of ITG (Internet Telephony Gateway) then analog telephones can communicate in VoIP networks. This research will discuss the analysis of voice quality in the communication process between telephone sets via ITG in a VoIP network based on the shape of the input and output, the amplitude response to frequency changes and the delay. Data retrieval is done by using a transmission test set as a substitute for human voice and knowing the amplitude value generated every time there is a change in frequency and an oscilloscope as a tool to determine the shape of the input and output waves as well as the delay. The results of this study indicate that delay generated by communication between analog telephones is <1 ms. When viewed from the form of the information signal generated from communication between telephone sets, that is, the shape of the input and output information signals are both sines, so it can be said that the information signal has not decreased in quality. The amplitude response resulting from frequency changes in communication between analog telephones is, the greater the value of the communication frequency.
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Harris, Hannah Marie, Waseem Gul, Mahmoud A. ElSohly, and Kenneth J. Sufka. "Effects of Cannabidiol and a Novel Cannabidiol Analog against Tactile Allodynia in a Murine Model of Cisplatin-Induced Neuropathy: Enhanced Effects of Sub-Analgesic Doses of Morphine." Medical Cannabis and Cannabinoids 1, no. 1 (June 12, 2018): 54–59. http://dx.doi.org/10.1159/000489077.

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Objective: This research examined whether a cannabidiol (CBD)-opioid pharmacotherapy could attenuate cisplatin-induced tactile allodynia. Methods: Mice (C57BL/6) were given 6 doses of 2.3 mg/kg cisplatin intraperitoneally (IP) on alternating days to induce tactile allodynia as quantified using an electric von Frey (eVF). Test groups in Experiment 1 received either vehicle, 0.1 or 2.5 mg/kg morphine, 1.0 or 2.0 CBD, or the 2 drugs in combination. Test groups in Experiment 2 received either vehicle, 0.1 or 2.5 mg/kg morphine, 1.0, 2.0, 3.0, or 4.0 mg/kg NB2111 (a long-acting CBD analogue), or the 2 drugs in combination. Drugs were administered IP 45 min before eVF assessment. Results: Cisplatin produced tactile allodynia that was attenuated by 2.5 mg/kg morphine. Both CBD and NB2111 produced dose-dependent attenuation of tactile allodynia. CBD and NB2111, given in combination with sub-analgesic doses of morphine, produced attenuation of tactile allodynia equivalent to 2.5 mg/kg morphine. Conclusions: While both CBD and NB2111, either alone or in combination with sub-analgesic doses of opioids, exhibited analgesic effects, NB2111 could be capable of superior analgesia over time by virtue of enhanced pharmacokinetics.
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Nakamaru, Y., Y. Furuta, D. Takagi, N. Oridate, and S. Fukuda. "Preservation of the nasolacrimal duct during endoscopic medial maxillectomy for sinonasal inverted papilloma." Rhinology journal 48, no. 4 (December 1, 2010): 452–56. http://dx.doi.org/10.4193/rhino10.015.

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BACKGROUND: To assess the efficacy of a new endonasal medial maxillectomy technique (EMM) for the treatment of inverted papilloma (IP). METHODOLOGY: A prospective series of 55 consecutive patients diagnosed with IP between March 2002 and April 2009 were entered into this study. The new surgical technique was applied to tumors arising from the anterior part of the maxillary sinus. After conventional EMM, the entire nasolacrimal duct was separated from the bony component of the nasolacrimal canal and preserved. Schirmer`s test and a visual analog scale (VAS) score were used to assess the lacrimal duct function after surgery. RESULTS: Ten of the 55 patients underwent the new surgical procedure. All patients were categorized with stage T3 or T4 tumors. No patients suffered tumor recurrence. There was no difference in lacrimal duct function between the diseased side and healthy side of the nasolacrimal duct. The mean VAS score was 2.8/100. CONCLUSIONS: This new surgical technique preserves the whole length of the nasolacrimal unit. It also offers several advantages including good visualization, nasolacrimal function after surgery and fewer adverse effects such as facial numbness and epiphora.
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Syahrial, Miftah Rahman. "Analisa Quality of Service IP Telephony dengan Metode Low Latency Queuing." Jurnal Telekomunikasi dan Komputer 5, no. 1 (February 27, 2017): 69. http://dx.doi.org/10.22441/incomtech.v5i1.1134.

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Voice over IP pada era modern sekarang ini sudah sangat krusial. Teknologi ini bisa mengatasi permasalahan yang muncul dalam telepon analog atau telepon tradisional ini adalah ketika pengguna, terutama perusahaan, ingin melakukan komunikasi jarak jauh dari pusat ke kantor cabang dimana cost alias biaya yang muncul ketika berkomunikasi dari pusat dan cabang berlangsung lama. Dalam penerapannya, telekomunikasi yang menggunakan teknologi internet, mengalami beberapa hambatan terutama dalam hal packet loss dan delay. Thesis ini membandingkan metode manajemen kongesti Quality of Service (QoS) low latency queuing (LLQ) dengan metode-metode lainnya seperti First in First out (FIFO) dan Class Based Weighted Fair Queuing (CBWFQ). Metode low latency queuing (LLQ) dirancang untuk memprioritaskan paket suara (voice) dan meminimalisir waktu tempuh (delay) yang akan dipakai oleh paket data. Hal ini bisa dicapai karena metode ini adalah gabungan dari metode CBWFQ dan metode Priority Queuing (PQ) yang dirancang untuk memprioritaskan paket suara tapi tidak dirancang untuk memprioritaskan paket data. Hasil yang didapat cukup memuaskan, waktu tempuh (delay) paket suara yang diperoleh dari LLQ untuk ITU-T G.114 (recommended delay untuk one-way connection VoIP) adalah 0,001 detik untuk delay minimumnya dan 0,142 detik untuk delay maksimumnya, dimana jaringan test bed yang dipakai oleh paket data dibuat untuk mencerminkan congested network, sedangkan metode-metode lain seperti FIFO dan CBWFQ melebihi acceptable delay yang direkomendasikan oleh ITU-T G.114. Sedangkan pengaruh implementasi LLQ terhadap codec yang dijalankan tidak banyak berubah, untuk delay yang dihasilkan codec G.729br8 cukup stabil dan delay dari codec G.711ulaw masih cenderung meningkat terkait dari lamanya sesi percakapan walaupun masih sesuai standar yang diterapkan oleh ITU-T.
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Benito, Javier, Beatriz Monteiro, Anne-Marie Lavoie, Guy Beauchamp, B. Duncan X. Lascelles, and Paulo V. Steagall. "Analgesic efficacy of intraperitoneal administration of bupivacaine in cats." Journal of Feline Medicine and Surgery 18, no. 11 (July 11, 2016): 906–12. http://dx.doi.org/10.1177/1098612x15610162.

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Objectives The aim of this study was to evaluate the analgesic efficacy of intraperitoneal (IP) bupivacaine in cats undergoing ovariohysterectomy (OVH). Methods Forty-five cats were included in a randomized, prospective, blinded study after owners’ written consent was obtained. The anesthetic protocol included acepromazine–buprenorphine–propofol–isoflurane. A ventral midline incision was made and cats (n = 15/group) were administered either IP saline 0.9% (negative and positive control groups; NG and PG, respectively) or IP bupivacaine (2 mg/kg; bupivacaine group; BG). Cats in the PG received meloxicam (0.2 mg/kg SC). An OVH was performed and postoperative pain was evaluated using a dynamic interactive visual analog scale (DIVAS), the UNESP-Botucatu multidimensional composite pain scale (MCPS) and mechanical nociceptive thresholds (MNT) for up to 8 h after the end of surgery. Postoperative sedation was evaluated using DIVAS. Rescue analgesia was provided with buprenorphine and/or meloxicam. Repeated measures linear models and a Cochran–Mantel–Haenszel test were used for statistical analysis ( P <0.05). Results There was a significant effect of treatment on the number of times rescue analgesia was administered ( P = 0.002) (PG, n = 2, 13%; NG, n = 12, 80%; BG, n = 4, 27%) with the number of rescues being higher in the NG group than in the PG ( P = 0.0004) and BG ( P = 0.02) groups. The DIVAS, MCPS and MNT were significantly different when compared with baseline values at different time points; however, data were not significantly different among groups. Conclusions and relevance Treatments PG and BG produced similar analgesia in terms of pain scores, number of times rescue analgesia was administered and MNT. Based on rescue analgesia, IP administration of bupivacaine provides analgesia in cats after OVH.
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Spolidoro Paschoal, Natalia de Oliva, Jamil Natour, Flavia S. Machado, Hilda Alcântara Veiga de Oliveira, and Rita Nely Vilar Furtado. "Effectiveness of Triamcinolone Hexacetonide Intraarticular Injection in Interphalangeal Joints: A 12-week Randomized Controlled Trial in Patients with Hand Osteoarthritis." Journal of Rheumatology 42, no. 10 (August 1, 2015): 1869–77. http://dx.doi.org/10.3899/jrheum.140736.

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Objective.To evaluate the effectiveness and tolerance of intraarticular injection (IAI) of triamcinolone hexacetonide (TH) for the treatment of osteoarthritis (OA) of hand interphalangeal (IP) joints.Methods.Sixty patients who underwent IAI at the most symptomatic IP joint were randomly assigned to receive TH/lidocaine (LD; n = 30) with TH 20 mg/ml and LD 2%, or just LD (n = 30). The injected joint was immobilized with a splint for 48 h in both groups. Patients were assessed at baseline and at 1, 4, 8, and 12 weeks by a blinded observer. The following variables were assessed: pain at rest [visual analog scale (VAS)r], pain at movement (VASm), swelling (physician VASs), goniometry, grip and pinch strength, hand function, treatment improvement, daily requirement of paracetamol, and local adverse effects. The proposed treatment (IAI with TH/LD) was successful if statistical improvement (p < 0.05) was achieved in at least 2 of 3 VAS. Repeated-measures ANOVA test was used to analyze intervention response.Results.Fifty-eight patients (96.67%) were women, and the mean age was 60.7 years (± 8.2). The TH/LD group showed greater improvement than the LD group for VASm (p = 0.014) and physician VASs (p = 0.022) from the first week until the end of the study. In other variables, there was no statistical difference between groups. No significant adverse effects were observed.Conclusion.The IAI with TH/LD has been shown to be more effective than the IAI with LD for pain on movement and joint swelling in patients with OA of the IP joints. Regarding pain at rest, there was no difference between groups. Trial registration number: ClinicalTrials.gov (NCT02102620).
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Dissertations / Theses on the topic "Analog IP Test"

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Vasudevamurthy, Rajath. "Time-based All-Digital Technique for Analog Built-in Self Test." Thesis, 2013. http://etd.iisc.ac.in/handle/2005/2841.

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A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis. With technology scaling, the inverter switching times are becoming shorter thus leading to better resolution of edges in time. This time resolution is observed to be superior to voltage resolution in the face of reducing supply voltage and increasing variations as physical dimensions shrink. In this thesis, a new method of observability of analog signals is proposed, which is digital-friendly and scalable to future deep sub-micron (DSM) processes. The low-bandwidth analog test voltage is captured as the delay between a pair of clock signals. The delay thus setup is measured digitally in accordance with the desired resolution. Such an approach lends itself easily to distributed manner, where the routing of analog signals over long paths is minimized. A small piece of circuitry, called sampling head (SpH) placed near each test voltage, acts as a transducer converting the test voltage to a delay between a pair of low-frequency clocks. A probe clock and a sampling clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head, present at each test node consists of a pair of delay cells and a pair of flip-flops, giving rise to as many sub-sampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding sub-sampled signal pair is fed to a Delay Measurement Unit (DMU) to measure the skew between this pair. The concept is validated by designing a test chip in UMC 130 nm CMOS process. Sub-mV accuracy for static signals is demonstrated for a measurement time of few milliseconds and ENOB of 5.29 is demonstrated for low bandwidth signals in the absence of sample-and-hold circuitry. The sampling clock is derived from the probe clock using a PLL and the design equations are worked out for optimal performance. To validate the concept, the duty-cycle of the probe clock, whose ON-time is modulated by a sine wave, is measured by the same DMU. Measurement results from FPGA implementation confirm 9 bits of resolution.
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Vasudevamurthy, Rajath. "Time-based All-Digital Technique for Analog Built-in Self Test." Thesis, 2013. http://hdl.handle.net/2005/2841.

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A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis. With technology scaling, the inverter switching times are becoming shorter thus leading to better resolution of edges in time. This time resolution is observed to be superior to voltage resolution in the face of reducing supply voltage and increasing variations as physical dimensions shrink. In this thesis, a new method of observability of analog signals is proposed, which is digital-friendly and scalable to future deep sub-micron (DSM) processes. The low-bandwidth analog test voltage is captured as the delay between a pair of clock signals. The delay thus setup is measured digitally in accordance with the desired resolution. Such an approach lends itself easily to distributed manner, where the routing of analog signals over long paths is minimized. A small piece of circuitry, called sampling head (SpH) placed near each test voltage, acts as a transducer converting the test voltage to a delay between a pair of low-frequency clocks. A probe clock and a sampling clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head, present at each test node consists of a pair of delay cells and a pair of flip-flops, giving rise to as many sub-sampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding sub-sampled signal pair is fed to a Delay Measurement Unit (DMU) to measure the skew between this pair. The concept is validated by designing a test chip in UMC 130 nm CMOS process. Sub-mV accuracy for static signals is demonstrated for a measurement time of few milliseconds and ENOB of 5.29 is demonstrated for low bandwidth signals in the absence of sample-and-hold circuitry. The sampling clock is derived from the probe clock using a PLL and the design equations are worked out for optimal performance. To validate the concept, the duty-cycle of the probe clock, whose ON-time is modulated by a sine wave, is measured by the same DMU. Measurement results from FPGA implementation confirm 9 bits of resolution.
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Book chapters on the topic "Analog IP Test"

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Conference papers on the topic "Analog IP Test"

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Abdennadher, Salem, Arani Sinha, and Yonghyun Kim. "Analog/Mixed Signal IP DFx from a Foundry perspective." In 2019 IEEE Latin American Test Symposium (LATS). IEEE, 2019. http://dx.doi.org/10.1109/latw.2019.8704563.

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Das, Upoma, Md Rafid Muttaki, Mark M. Tehranipoor, and Farimah Farahmandi. "ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features." In 2022 IEEE International Test Conference (ITC). IEEE, 2022. http://dx.doi.org/10.1109/itc50671.2022.00023.

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Hashida, Takushi, Yuuki Araga, and Makoto Nagata. "A diagnosis testbench of analog IP cores against on-chip environmental disturbances." In 2011 IEEE VLSI Test Symposium (VTS). IEEE, 2011. http://dx.doi.org/10.1109/vts.2011.5783757.

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Reich, T., H. D. B. Prautsch, U. Eichler, and R. Buhl. "Silicon Proof of the Intelligent Analog IP Design Flow for Flexible Automotive Components." In Design, Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2015. http://dx.doi.org/10.7873/date.2015.0232.

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Vasudevamurthy, Rajath, Pratap Kumar Das, and Bharadwaj Amrutur. "A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test." In 2011 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2011. http://dx.doi.org/10.1109/iscas.2011.5937996.

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Bidmeshki, Mohammad-Mahdi, Angelos Antonopoulos, and Yiorgos Makris. "Information flow tracking in analog/mixed-signal designs through proof-carrying hardware IP." In 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017. http://dx.doi.org/10.23919/date.2017.7927268.

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Gomez, Jhon, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, and Georges Gielen. "High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysis." In 2023 IEEE European Test Symposium (ETS). IEEE, 2023. http://dx.doi.org/10.1109/ets56758.2023.10173963.

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