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Dissertations / Theses on the topic 'Analog to Digital Conversion (ADC)'

Author: Grafiati

Published: 5 June 2025

Last updated: 2 August 2025

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1

EL, RACHINI ALI. "Redundant analog to digital conversion architectures in CMOS technology." Doctoral thesis, Università degli Studi di Cagliari, 2015. http://hdl.handle.net/11584/266860.

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The operation of modern electronic devices in different fields as communications, signal processing, and sensor interface is critically affected with robust, high performance and scalable Analog-to-Digital Converter (ADCs), that can be considered as one of the main blocks in many systems, since they are mandatory to make the link between the analog outside world and the evermore-ubiquitous digital computer world. The design of these ADCs come distinct tradeoffs between speed, power, resolution, and die area embodied within many data conversion architectural variations. The flash ADC structure

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2

Itskovich, Mikhail. "Design of a Low Power Delta Sigma Modulator for Analog to Digital Conversion." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/34901.

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The growing demand of “System on a Chip” applications necessitates integration of multiple devices on the same chip. Analog to Digital conversion is essential to interfacing digital systems to external devices such as sensors. This presents a difficulty since high precision analog devices do not mix well with high speed digital circuits. The digital environment constraints put demand on the analog portion to be resource efficient and noise tolerant at the same time. Even more demanding, Analog to Digital converters must consume a small amount of power since “System on a Chip” circuits often ta

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3

Silva, Alexandre Herculano Mendes. "Pipelined analog-to-digital conversion using current-mode reference shifting." Master's thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8265.

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Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores<br>Pipeline Analog-to-digital converters (ADCs) are the most popular architecture for high-speed medium-to-high resolution applications. A fundamental, but often unreferenced building block of pipeline ADCs are the reference voltage circuits. They are required to maintain a stable reference with low output impedance to drive large internal switched capacitor loads quickly. Achieving this usually leads to a scheme that consumes a large portion of the overall power and area. A review of the literature sho

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Li, Sulin. "A Highly Digital VCO-Based ADC With Lookup-Table-Based Background Calibration." Digital WPI, 2019. https://digitalcommons.wpi.edu/etd-dissertations/556.

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CMOS technology scaling has enabled dramatic improvement for digital circuits both in terms of speed and power efficiency. However, most traditional analog-to-digital converter (ADC) architectures are challenged by ever-decreasing supply voltage. The improvement in time resolution enabled by increased digital speeds drives design towards time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The main challenge in VCO-based ADC design is mitigating the nonlinearity of VCO Voltage-to-frequency (V-to-f) characteristics. Achieving signal-to-noise ratio (SNR) performance

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5

Cheng, Yongjie. "Design and Realization of a Single Stage Sigma-Delta ADC With Low Oversampling Ratio." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1561.pdf.

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6

Tao, Sha. "Power-Efficient Continuous-Time Incremental Sigma-Delta Analog-to-Digital Converters." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-164282.

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Over the past decade, there has been a growing interest in the devel- opment of integrated circuits (ICs) for wearable or implantable biosensors, aiming at providing personalized healthcare services and reducing the health-care expenses. In biosensor ICs, the analog-to-digital converter (ADC) is a key building block that acts as a bridge between analog signals and digital processors. Since most of the biosensors are attached to or implanted in hu- man bodies and powered by either portable batteries or harvested energy, ultra-low-power operation is often required. The stringent power budget im-

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7

Li, Xiangtao. "High-speed analog-to-digital conversion in SiGe HBT technology." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24652.

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Thesis (Ph.D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.<br>Committee Chair: Cressler, John D.; Committee Member: Laskar, Joy; Committee Member: Lee, Chin-Hui; Committee Member: Morley, Thomas; Committee Member: Papapolymerou, John

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8

McGinnis, Ryan Edward. "Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1152542196.

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9

Hiremath, Vinayashree. "DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY." Wright State University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500.

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10

Alla, Ravi Chandar. "Design and Implementation of an analog to digital conversion mechanism for an in-situ monitoring microelectrode SOC." University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1227042824.

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11

Souza, Junior Adao Antonio de. "Digital approach for the design of statistical analog data acquisition on SoCs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/11491.

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With the current demand for mixed-signal SoCs, an increasing number of designers are looking for ADC architectures that can be easily implemented over digital substrates. Since ADC performance is strongly dependent upon physical and electrical features, it gets more difficult for them to benefit from more recent technologies, where these features are more variable. This way, analog signal acquisition is not allowed to follow an evolutionary trend compatible with Moore’s Law. In fact, such trend shall get worst, since newer technologies are expected to have more variable characteristics. Also,

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12

Aguirre, Paulo Cesar Comassetto de. "Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/105065.

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Conversores analógico-digitais (ADCs) têm papel fundamental na implementação dos sistemas-em-chip, do inglês System-on-Chip (SoC), atuais. Em razão dos requisitos destes sistemas e dos compromissos entre as características fundamentais dos ADCs, como largura de banda, consumo de energia e exatidão, diversas topologias e estratégias para sua implementação em circuitos integrados (CIs) têm sido desenvolvidas através dos tempos. Dentre estas topologias, os conversores sigma-delta (SDC) têm se destacado pela versatilidade, aliada ao baixo consumo e excelente exatidão. Inicialmente desenvolvidos e

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13

Mas, Alexandre. "Convertisseur analogique-numérique large bande avec correction mixte." Thesis, Université Paris-Saclay (ComUE), 2018. http://www.theses.fr/2018SACLC054/document.

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Les besoins en débit d’information à transmettre ne cessent de croitre. Aussi la généralisation des émetteurs-récepteurs large-bande implique l’intégration de solutions sur une technologie silicium CMOS afin que leur cout soit compatible avec une application grand public. Si l’intégration massive des traitements numériques est facilitée par les dernières technologies CMOS, la fonction de conversion analogique-numérique est quant à elle plus difficile. En effet, afin d’optimiser l’étage frontal analogique, le convertisseur analogique-numérique (CAN) doit répondre à des contraintes très fortes e

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Deza, Julien. "Etude, Conception et Caractérisation de circuits pour la Conversion Analogique Numérique à très hautes performances en technologie TBH InP 0.7µm." Thesis, Cergy-Pontoise, 2013. http://www.theses.fr/2013CERG0680/document.

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Ce travail de thèse concerne les circuits ultra-rapides pour la conversion analogique numérique performante en technologie bipolaire à hétérojonctions sur substrat Indium Phosphore (TBDH/InP). L'étude s'intéresse à la fonction principale qui est l'échantillonnage blocage. Elle a été menée par simulation de l'ensemble des blocs composant cette fonction. En particulier une étude extensive des cœurs des circuits Echantillonneurs/Bloqueurs a été effectuée pour différents paramètres électriques pour aboutir à des valeurs optimales réalisant un compromis entre la bande passante la résolution et la l

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Zeloufi, Mohamed. "Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT115.

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À l’horizon 2024, l’expérience ATLAS prévoit de fonctionner à des luminosités 10 fois supérieures à la configuration actuelle. Par conséquent, l’électronique actuelle de lecture ne correspondra pas aux conditions de ces luminosités. Dans ces conditions, une nouvelle électronique devra être conçue. Cette mise à niveau est rendue nécessaire aussi par les dommages causés par les radiations et le vieillissement. Une nouvelle carte frontale va être intégrée dans l’électronique de lecture du calorimètre LAr. Un élément essentiel de cette carte est le Convertisseur Analogique-Numérique (CAN) présenta

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16

Saucier, Scott. "Multiband Analog-to-Digital Conversion." Fogler Library, University of Maine, 2002. http://www.library.umaine.edu/theses/pdf/SaucierS2002.pdf.

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17

Aldana, Rafael. "Photoelectronic analog to digital conversion /." May be available electronically:, 2008. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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18

Parsons, Colton A. "Variable Precision Tandem Analog-to-Digital Converter (ADC)." DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1255.

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This paper describes an analog-to-digital signal converter which varies its precision as a function of input slew rate (maximum signal rate of change), in order to best follow the input in real time. It uses Flash and Successive Approximation (SAR) conversion techniques in sequence. As part of the design, the concept of "total real-time optimization" is explored, where any delay at all is treated as an error (Error = Delay * Signal Slew Rate). This error metric is proposed for use in digital control systems. The ADC uses a 4-bit Flash converter in tandem with SAR logic that has variable precis

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Orchanian, Shant. "Split Non-Linear Cyclic Analog-to-Digital Converter." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-theses/324.

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Analog-to-Digital Converters (ADC's) are inherently optimized for linearity in order to produce an accurate digital representation of an analog voltage. The Cyclic ADC's linearity is limited by one of its components, the residue amplifier. The residue amplifier is used to amplify the error between the analog voltage and the digital decision by a gain of two in each cycle of a conversion. In previous designs, this was accomplished by using a compound op-amp with a large open loop gain for linearity, and negative feedback to achieve the gain of two. This thesis explores the use of a resistively

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Croughwell, Rosamaria. "A 16-b 10Msample/s Split-Interleaved Analog to Digital Converter." Digital WPI, 2007. https://digitalcommons.wpi.edu/etd-theses/974.

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"This work describes the integrated circuit design of a 16-bit, 10Msample/sec, combination â€˜splitâ€™ interleaved analog to digital converter. Time interleaving of analog to digital converters has been used successfully for many years as a technique to achieve faster speeds using multiple identical converters. However, efforts to achieve higher resolutions with this technique have been difficult due to the precise matching required of the converter channels. The most troublesome errors in these types of converters are gain, offset and timing differences between channels. The â€˜split ADCâ

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Spetla, Hattie. "Split Cyclic Analog to Digital Converter Using A Nonlinear Gain Stage." Digital WPI, 2009. https://digitalcommons.wpi.edu/etd-theses/1014.

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"Previous implementations of digital background calibration for cyclic ADCs have required linear amplifier behavior in the gain stage for accurate correction. Correction is digital decoding of ADC outputs to determine the original ADC input. Permitting nonlinearity in the gain stage of the ADC allows for less demanding amplifier design requirements, reducing power and size. However this requires a method of determining the value of this variable gain during digital correction. Look up tables (LUTs,) are an effective and efficient method of compensating for analog circuit imperfections. The LUT

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22

Levski, Dimitrov Deyan. "A Cyclic Analog to Digital Converter for CMOS image sensors." Thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103193.

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The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple readout speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to

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23

Velazquez, Scott Richard. "Hybrid filter banks for analog/digital conversion." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/10436.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.<br>Includes bibliographical references (leaves 288-291).<br>by Scott Richard Velazquez.<br>Ph.D.

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Radhakrishnan, Venkataraman. "Design of a low power analog to digital converter in a 130nmCMOS technology." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72700.

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Communication technology has become indispensable in a modernsociety. Its importance is growing day by day. One of the main reasonsbehind this growth is the advancement in the analog and mixed signalcircuit design.Analog to digital converter (ADC) is an essential part in a modernreceiver system. Its development is driven by the progress of CMOStechnologies with an aim to reduce area and power consumption. In thearea of RF integrated circuits for wireless application low operationalvoltage, and less current consumption are the central aspects of thedesign. The aim of this master thesis is the d

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Kook, Se Hun. "Low-cost testing of high-precision analog-to-digital converters." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/41170.

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The advent of deep submicron technology has resulted in a new generation of highly integrated mixed-signal system-on-chips (SoCs) and system-on-packages (SoPs). As a result, the cost of electrical products has sharply declined, and their performance has greatly improved. However, a testing throughput still remains one of the major contribution factors to final cost of the electrical products. In addition, highly precise and robust test methods and equipment are needed to promise non-defective products to customers. Hence, the testing is a critical part of the manufacturing process in the semic

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Esparza, Jorge A. "An analog preprocessing architecture for high-speed analog-to-digital conversion." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1993. http://handle.dtic.mil/100.2/ADA276737.

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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 1993.<br>Thesis advisor(s): Phillip E. Pace ; Douglas J. Fouts. "December 1993." Bibliography: p. 154. Also available online.

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Borkowski, Peter (Peter Joseph) 1963 Carleton University Dissertation Engineering Electrical. "Gallium arsenide analog circuits for high-speed analog-to-digital conversion." Ottawa.:, 1989.

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Hassan, Raza Naqvi Syed. "1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8382.

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<p>The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.</p><p>Of all types of ADCs the flash ADC is not only famous for its data conversion

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Tchambake, Yapti Kelly. "Wideband Analog-to-Digital Converter (ADC) design for power amplifiers linearization." Electronic Thesis or Diss., Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLT047.

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De nos jours, la consommation d’énergie devient un des principaux défis à surmonter dans le développement des réseaux de communications mobiles. L’amplificateur de puissance est le composant le plus gourmand en énergie dans les stations de base. La cinquième génération de téléphonie mobile de part ses larges bandes de communication et ses modulations complexes augmente encore plus les contraintes sur l’amplificateur de puissance. Pour palier ce problème, il est courant de faire appel à des techniques de pré-distorsion. Une contrainte importante dans la mise en oeuvre de cette technique est la

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Pishdad, Bardia. "Nyquist-rate analog-to-digital conversion with calibration." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29544.

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Analog-to-Digital Converter (ADC) microcircuits are required to meet stringent accuracy specifications in spite of their analog components' inherent nonidealities as well as the accuracy limitations due to fabrication technology. In this thesis, a 3-step Nyquist rate ADC is presented which makes use of bitstream processing to calibrate the digital-to-analog converter (DAC) and the residue amplifier, while using the same hardware to calibrate the sub-ADC. The system is designed to provide programmability and calibrate undesired circuit characteristics such as offset, gain error, and nonlinearit

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Tarnoff, David. "Episode 2.6 – Analog to Digital Conversion with Arduino." Digital Commons @ East Tennessee State University, 2020. https://dc.etsu.edu/computer-organization-design-oer/12.

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Does capturing analog measurements with a computer sound like so much hocus pocus? In this episode, we will take a stab at lessening some of that mystic by showing how the Arduino platform can be used to perform this conversion.

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Balasubramanian, Sidharth. "STUDIES ON HIGH-SPEED DIGITAL-TO-ANALOG CONVERSION." The Ohio State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=osu1376333781.

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Danesh, Seyed Amir Ali. "Time interleaved counter analog to digital converters." Thesis, University of Edinburgh, 2011. http://hdl.handle.net/1842/5790.

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The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging

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Björsell, Niclas. "Modeling Analog to Digital Converters at Radio Frequency." Doctoral thesis, KTH, Signalbehandling, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4523.

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Det här arbetet handlar om att ta fram beteendemodeller av analog till digital omvandlare avsedda för tillämpningar i radiofrekvensområdet. Det gäller tillämpningar inom telekommunikation men även in test- och mätinstrument där omvandlingen från analoga till digitala signaler ofta är en prestandamässig flaskhals. Modellerna är avsedda att användas för att efterbehandla utdata från omvandlaren och på så sätt förbättra prestanda på den digitala signalen. Genom att skapa modeller av verkliga omvandlare och hur dessa avviker från ett idealt beteende kan ofullständigheter korrigeras genom så kallad

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Docef, Alen. "Efficient structures for oversampling A/D conversion." Thesis, Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/14975.

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36

Ng, Sheung Yan. "A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique." The Ohio State University, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906.

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Petrie, Alexander Craig. "Ultra-Low-Supply-Voltage Analog-to-Digital Converters." BYU ScholarsArchive, 2019. https://scholarsarchive.byu.edu/etd/9122.

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This thesis presents techniques to implement analog-to-digital converters (ADCs) under an ultra-low-supply-voltage of 0.2 V to reduce the power consumption. The thesis proposes a dynamic bulk biasing circuit to adjust the PMOS bulk voltage to balance the NMOS and PMOS drain currents to guarantee functionality in the presence of process, voltage, and temperature variations. The dynamic bulk bias circuit is analyzed rigorously to show its functionality. This thesis also describes a new comparator suitable for a 0.2-V supply using ac-coupling, stacked input pairs, and voltage-boosted load capacit

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Aust, Carrie Ellen. "A Low-Power, Variable-Resolution Analog-to-Digital Converter." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/33737.

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Analog-to-digital converters (ADCs) are used to convert analog signals to the digital domain in digital communications systems. An ADC used in wireless communications should meet the necessary requirements for the worst-case channel condition. However, the worst-case scenario rarely occurs. As a consequence, a high-resolution and subsequently high power ADC designed for the worst case is not required for most operating conditions. A solution to reduce the power dissipation of ADCs in wireless digital communications systems is to detect the current channel condition and to dynamically vary

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Taillefer, Christopher. "Analog-to-digital conversion via time-mode signal processing." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=18669.

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Conventional voltage-mode analog-to-digital converters use voltage amplifiers, voltage comparators, and switch capacitor networks to perform their signal processing. When compared to digital circuitry, these analog circuit blocks consume significant power, occupy large silicon areas, and operate at relatively slow data processing speeds. A signal processing methodology is proposed that performs analog-to-digital conversion on voltage signals while implementing all the circuits in a digital CMOS logic style. This methodology, called time-mode signal processing, uses time-difference variables as

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Siragusa, Eric J. "Digitally enhanced high resolution pipelined analog-to-digital conversion /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3112844.

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Gao, Yueran. "Techniques for Reliable and Efficient Analog to Digital Conversion." OpenSIUC, 2016. https://opensiuc.lib.siu.edu/dissertations/1189.

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Analog-to-Digital conversion (ADC) is an essential process in signal processing. It converts analog signals in the real world to digital codes that can be conveniently processed by digital systems. Among various ADC architectures, pipelined ADC is very attractive since it can achieve high conversion speed and high resolution. In this dissertation, a reconfigurable pipelined ADC is presented. Its stage order programmability enables the capability to minimize process-variation induced performance degradation. In addition, a redundant stage is added to perform online testing and to replace a faul

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Majidi, Rabeeh. "DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-dissertations/275.

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With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter(ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7-bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing s

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Jalali, Mazlouman Shahrzad. "A frequency-translating hybrid architecture for wideband analog-to-digital converters." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/2745.

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Many emerging applications call for wideband analog-to-digital converters and some require medium-to-high resolution. Incorporating such ADCs allows for shifting as much of the signal processing tasks as possible to the digital domain, where more flexible and programmable circuits are available. However, realizing such ADCs with the existing single stage architectures is very challenging. Therefore, parallel ADC architectures such as time-interleaved structures are used. Unfortunately, such architectures require high-speed high-precision sample-and-hold (S/H) stages that are challenging to imp

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Wang, Mingzhen. "High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.

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Zhang, Dai. "Design of Ultra-Low-Power Analog-to-Digital Converters." Licentiate thesis, Linköpings universitet, Elektroniska komponenter, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79276.

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Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, ty

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Sivakumar, Balasubramanian. "A 6-Bit Sub-Ranging High Speed Flash Analog To Digital Converter With Digital Speed And Power Control." The Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=osu1229631191.

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Shahzad, Khurram. "Low-power 8-bit Pipelined ADC with current mode Multiplying Digital-to-Analog Converter (MDAC)." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-20314.

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<p>In order to convert the analog information in the digital domain, pipelined analog-to-digital converter (ADC) offers an optimum balance of resolution, speed, power consumption, size and design effort.</p><p>In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1.5-bit and employ current mode multiplying analog-to-digital converter (MDAC). The main focus is to design and optimize the MDAC. Based on the analysis of "On current mode circuits" discussed in chapter 2, we design and optimize the MDAC circuit for the best possible effective

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Carter, Nathan R. "A 12-b 50Msample/s Pipeline Analog to Digital Converter." Digital WPI, 2000. https://digitalcommons.wpi.edu/etd-theses/749.

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This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage str

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Figueiredo, Michael. "Reference-free high-speed cmos pipeline analog-to-digital converters." Doctoral thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8776.

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Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering of the Faculdade de Ciências e Tecnologia of Universidade Nova de Lisboa<br>More and more signal processing is being transferred to the digital domain to profit from the technological enhancement of digital circuits. Where technology scaling enhances the capabilities of digital circuits, it degrades the performance of analog circuits. However, it is important to note that the impact that technology scaling has on digital circuits is becoming smaller and smaller, wh

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Thandri, Bharath Kumar. "Design of RF/IF analog to digital converters for software radio communication receivers." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5774.

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Software radio architecture can support multiple standards by performing analogto- digital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined radio architecture in which the A/D conversion is performed on intermediate frequency (IF) signals after a single down conversion. The first part of this research deals with the design and implementation of a fourth order continuous time bandpass sigma-delta (CT BP) C based on LC filters for direct

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