Relevant bibliographies by topics / Analog-to-digital converter (ADC)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Analog-to-digital converter (ADC)'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 June 2024

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Journal articles on the topic "Analog-to-digital converter (ADC)"

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Wang, Weihe, and Hongqi Yu. "Pipelined Memristive neural network analog-to-digital converter." Journal of Physics: Conference Series 2632, no. 1 (November 1, 2023): 012004. http://dx.doi.org/10.1088/1742-6596/2632/1/012004.

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Abstract This paper designs a pipelined memristive neural network ADCs. Cascade the sub stages of memristive neural network ADC with pipeline structure to improve the conversion accuracy of memristive neural network ADC. First, the signal flow of the pipeline architecture is optimized, and the compatibility between the 4 bit memristive neural network ADC and the pipeline architecture is solved. Secondly, the application of random disturbance circuits in pipeline architecture was analyzed. Combining the calibration circuit with the pipeline DAC to reduce the power consumption of the calibration circuit. Finally, the circuit model of memristive neural network ADC is built and compared with the existing memristive neural network ADC. The results indicate that the pipeline structure ADC designed in this chapter has the advantage of adaptive calibration in terms of calibration function.
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Chauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 31, 2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.

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After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.
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Faure, Nicolaas, and Saurabh Sinha. "High-speed Cherry Hooper flash analog-to-digital converter." Microelectronics International 34, no. 1 (January 3, 2017): 22–29. http://dx.doi.org/10.1108/mi-08-2015-0075.

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Purpose The 60 GHz unlicensed band is being utilized for high-speed wireless networks with data rates in the gigabit range. To successfully make use of these high-speed signals in a digital system, a high-speed analog-to-digital converter (ADC) is necessary. This paper aims to present the use of a common collector (CC) input tree and Cherry Hooper (C-H) differential amplifier to enable analog-to-digital conversion at high frequencies. Design/methodology/approach The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain bandwidth speeds higher than the comparator stages while using less current than the comparator stages. The C-H differential amplifier is modified to accommodate the low breakdown voltages of the technology node and implemented as a comparator. The comparator stages are biased to obtain a high output voltage swing and have a small signal bandwidth up to 29 GHz. Simulations were performed using foundry development kits to verify circuit operation. A two-bit ADC was prototyped in IBM’s 130 nm SiGe BiCMOS 8HP technology node. Measurements were carried out on test printed circuit boards and compared with simulation results. Findings The use of the added CC input tree showed a simulated bandwidth improvement of approximately 3.23 times when compared to a basic flash architecture, for a two-bit ADC. Measured results showed an effective number of bits (ENOB) of 1.18, from DC up to 2 GHz, whereas the simulated result was 1.5. The maximum measured integral non-linearity and differential non-linearity was 0.33 LSB. The prototype ADC had a figure of merit of 42 pJ/sample. Originality/value The prototype ADC results showed that the group delay for the C-H comparator plays a critical role in ADC performance for high frequency input signals. For minimal component variation, the group delay between channels deviate from each other, causing incorrect output codes. The prototype ADC had a low gain which reduced the comparator performance. The two-bit CC C-H ADC is capable of achieving an ENOB close to 1.18, for frequencies up to 2 GHz, with 180 mW total power consumption.
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Wang, Li, Wenli Chen, Kai Chen, Renjun He, and Wenjian Zhou. "The Research on the Signal Generation Method and Digital Pre-Processing Based on Time-Interleaved Digital-to-Analog Converter for Analog-to-Digital Converter Testing." Applied Sciences 12, no. 3 (February 7, 2022): 1704. http://dx.doi.org/10.3390/app12031704.

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In the high-resolution analog circuit, the performance of chips is an important part. The performance of the chips needs to be determined by testing. According to the test requirements, stimulus signal with better quality and performance is necessary. The main research direction is how to generate high-resolution and high-speed analog signal when there is no suitable high-resolution and high-speed digital-to-analog converter (DAC) chip available. In this paper, we take the high-resolution analog-to-digital converter (ADC) chips test as an example; this article uses high-resolution DAC chips and multiplexers to generate high-resolution high-speed signals that can be used for testing high-resolution ADC chips based on the principle of time-alternating sampling. This article explains its method, analyzes its error and proposes a digital pre-processing method to reduce the error. Finally, the actual circuit is designed, and the method is verified on the circuit. The test results prove the effectiveness of this method for generating high-resolution ADC test signals.
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Park, Joonsung, Jiwon Lee, Jacob A. Abraham, and Byoungho Kim. "A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter." Electronics 13, no. 4 (February 13, 2024): 755. http://dx.doi.org/10.3390/electronics13040755.

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The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as Cn=2×Cn−1, the variable capacitor Cn of ADC1 can be updated to be closest to the sum of Cn−1 of ADC1 and Cn−1 of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the Cn of ADC1 can be connected with two of the Cn−1 of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update Cn. This process is iterated, until Cn is in agreement with the sum of two of Cn−1. Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by 21.8 dB and 6.4 dB, respectively.
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Bialek, J., A. Wickmann, F. Ohnhaeuser, G. Fischer, R. Weigel, and T. Ussmueller. "Implementation of a digital trim scheme for SAR ADCs." Advances in Radio Science 11 (July 4, 2013): 227–30. http://dx.doi.org/10.5194/ars-11-227-2013.

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Abstract. Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.
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Anvekar, Dinesh K., and B. S. Sonde. "Programmable Nonlinear Adc: An Illustrative Example." International Journal of Electrical Engineering & Education 33, no. 3 (July 1996): 216–24. http://dx.doi.org/10.1177/002072099603300303.

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Programmable nonlinear ADC: an illustrative example Programmable nonlinear analog-to-digital conversion is a new topic in EE curricula. With a view to introducing the EE student to the concept of transfer characteristic programmability of an analog-to-digital converter (ADC), a memory-prefetch programmable nonlinear ADC is presented. The design, analytical evaluation, and experimental implementation for the ADC are described.
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Liu, Xiaolu, Jin Shao, Peng Zhang, Guoyu Cui, and Haifeng Qian. "Multi-channel and high-precision analog-to-digital converter chips for power grid detection." Journal of Physics: Conference Series 2584, no. 1 (September 1, 2023): 012139. http://dx.doi.org/10.1088/1742-6596/2584/1/012139.

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Abstract This project focuses on the research of high-precision multi-channel analog-to-digital converter chips for power grid detection and system applications. There have been breakthroughs made in a series of key technologies, such as successive approximation ADC architecture, oversampling ADC architecture, and digital calibration technology. By combining it with multi-channel ADC to achieve high-precision multi-channel analog-to-digital converter design, it provides strong support for China to achieve autonomous and controllable high-precision multi-channel ADC chips and has extremely high application value.
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Li, Donggen. "Comparative Study of High Speed ADCs." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 146–52. http://dx.doi.org/10.54097/hset.v27i.3731.

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With the development of information technology, analog-to-digital converter (ADC) is widely used. In products such as radar, ultra wideband communication system, high-performance digital oscilloscope and so on, the speed performance of analog-to-digital converter is usually the bottleneck of the whole system performance, so the research of high-speed ADC has attracted much attention. ADC is an interface circuit that converts analog signals into digital signals that can be processed by DSP. This paper will start with the basic knowledge of ADC, explain the general working process of ADC, introduce several architectures and working principles suitable for high-speed ADC, and compare and analyze their advantages and disadvantages.
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Mr. Nikhil Surkar, Ms. Shriya Timande. "Analysis of Analog to Digital Converter for Biomedical Applications." International Journal of New Practices in Management and Engineering 1, no. 03 (September 30, 2012): 01–07. http://dx.doi.org/10.17762/ijnpme.v1i03.6.

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This paper presents an ADC which can be used for biomedical application like pacemaker. For the low-power operation, monotonic switching scheme and operating voltage reduction have been implemented in the design. The 10bit 1.8V rail-to-rail (SAR) ADC is realized using UMC 0.18µm CMOS process. Simulations are performed by spectre simulation. From static performance, offset error and full scale error are noticed. This performance issue can be corrected by reducing discharge in capacitor by implementing sampling switch as bootstrapped switch and proper selection of common-mode voltage where 20fF is used as unit capacitance.
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Dissertations / Theses on the topic "Analog-to-digital converter (ADC)"

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Parsons, Colton A. "Variable Precision Tandem Analog-to-Digital Converter (ADC)." DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1255.

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This paper describes an analog-to-digital signal converter which varies its precision as a function of input slew rate (maximum signal rate of change), in order to best follow the input in real time. It uses Flash and Successive Approximation (SAR) conversion techniques in sequence. As part of the design, the concept of "total real-time optimization" is explored, where any delay at all is treated as an error (Error = Delay * Signal Slew Rate). This error metric is proposed for use in digital control systems. The ADC uses a 4-bit Flash converter in tandem with SAR logic that has variable precision (0 to 11 bits). This allows the Tandem ADC to switch from a fast, imprecise converter to a slow, precise converter. The level of precision is determined by the input’s peak rate of change, optimized for minimum real-time error; a secondary goal is to react quickly to input transient spikes. The implementation of the Tandem ADC is described, along with various issues which arise when designing such a converter and how they may be dealt with. These include Flash ADC inaccuracies, rounding issues, and system timing and synchronization. Most of the design is described down to the level of logic gates and related building blocks (e.g. latches and flip-flops), and various logic optimizations are used in the design to reduce calculation delays. The design also avoids active analog circuitry whenever possible – it can be almost entirely implemented with CMOS logic and passive analog components.
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Orchanian, Shant. "Split Non-Linear Cyclic Analog-to-Digital Converter." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-theses/324.

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Analog-to-Digital Converters (ADC's) are inherently optimized for linearity in order to produce an accurate digital representation of an analog voltage. The Cyclic ADC's linearity is limited by one of its components, the residue amplifier. The residue amplifier is used to amplify the error between the analog voltage and the digital decision by a gain of two in each cycle of a conversion. In previous designs, this was accomplished by using a compound op-amp with a large open loop gain for linearity, and negative feedback to achieve the gain of two. This thesis explores the use of a resistively loaded differential pair to achieve this gain. The design reduces die size, power usage, and analog complexity. To correct for this inherent non- linearity, a Split ADC concept is employed to enable digital background calibration and a correction algorithm to account for this non- linearity. The Integrated circuit is designed, laid out, and simulated using the Cadence Integrated Circuit Front to Back design suite (ICFB) in the 0.18um Jazz CMOS process.
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Carter, Nathan R. "A 12-b 50Msample/s Pipeline Analog to Digital Converter." Digital WPI, 2000. https://digitalcommons.wpi.edu/etd-theses/749.

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This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage structure. Correction of the pipeline is accomplished by measuring the offset and gain of each of the first six stages using subsequent stages. The measured values are used to calculate digtal values the compensate for the inaccuracies of the analog pipeline. Corrected digital values for each stage are stored in the pipeline and used to create corrected output codes. Errors caused by measuring the first six stages using uncalibrated stages are minimized by using extra switching circuitry during calibration.
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Croughwell, Rosamaria. "A 16-b 10Msample/s Split-Interleaved Analog to Digital Converter." Digital WPI, 2007. https://digitalcommons.wpi.edu/etd-theses/974.

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"This work describes the integrated circuit design of a 16-bit, 10Msample/sec, combination ‘split’ interleaved analog to digital converter. Time interleaving of analog to digital converters has been used successfully for many years as a technique to achieve faster speeds using multiple identical converters. However, efforts to achieve higher resolutions with this technique have been difficult due to the precise matching required of the converter channels. The most troublesome errors in these types of converters are gain, offset and timing differences between channels. The ‘split ADC’ is a new concept that allows the use of a deterministic, digital, self calibrating algorithm. In this approach, an ADC is split into two paths, producing two output codes from the same input sample. The difference of these two codes is used as the calibration signal for an LMS error estimation algorithm that drives the difference error to zero. The ADC is calibrated when the codes are equal and the output is taken as the average of the two codes. The ‘split’ ADC concept and interleaved architecture are combined in this IC design to form the core of a high speed, high resolution, and self-calibrating ADC system. The dual outputs are used to drive a digital calibration engine to correct for the channel mismatch errors. This system has the speed benefits of interleaving while maintaining high resolution. The hardware for the algorithm as well as the ADC can be implemented in a standard 0.25um CMOS process, resulting in a relatively inexpensive solution. This work is supported by grants from Analog Devices Incorporated (ADI) and the National Science Foundation (NSF). "
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Levski, Dimitrov Deyan. "A Cyclic Analog to Digital Converter for CMOS image sensors." Thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103193.

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The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple readout speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to design, thus employing parallelism in the readout schemes appears to be inevitable for relaxing the analog readout circuits and keeping the same capturing speeds. This transfer however imposes additional demands to parallel ADC designs, mainly related to achievable accuracy, area and power. In this work a 12-bit Cyclic ADC (CADC) aimed for column-parallel readout implementation in CMOS image sensors is presented. The aim of the conducted study is to cover multiple CADC sub-component architectures and provide an analysis onto the latter to a mid-level of depth. A few various Multiplying DAC (MDAC) structures have been re-examined and a preliminary redundant signed-digit CADC design based on a 1.5-bit modified flip-over MDAC has been conducted. Three comparator architectures have been explored and a dynamic interpolative Sub-ADC is presented. Finally, some weak spots degrading the performance of the carried-out design have been analyzed. As an architectural improvement possibility two MDAC capacitor mismatch error reduction techniques have been presented.
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Spetla, Hattie. "Split Cyclic Analog to Digital Converter Using A Nonlinear Gain Stage." Digital WPI, 2009. https://digitalcommons.wpi.edu/etd-theses/1014.

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"Previous implementations of digital background calibration for cyclic ADCs have required linear amplifier behavior in the gain stage for accurate correction. Correction is digital decoding of ADC outputs to determine the original ADC input. Permitting nonlinearity in the gain stage of the ADC allows for less demanding amplifier design requirements, reducing power and size. However this requires a method of determining the value of this variable gain during digital correction. Look up tables (LUTs,) are an effective and efficient method of compensating for analog circuit imperfections. The LUT correction and calibration method discussed in this work has been simulated using Cadence integrated circuit simulation ADC specifications and MATLAB."
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Tchambake, Yapti Kelly. "Wideband Analog-to-Digital Converter (ADC) design for power amplifiers linearization." Electronic Thesis or Diss., Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLT047.

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De nos jours, la consommation d’énergie devient un des principaux défis à surmonter dans le développement des réseaux de communications mobiles. L’amplificateur de puissance est le composant le plus gourmand en énergie dans les stations de base. La cinquième génération de téléphonie mobile de part ses larges bandes de communication et ses modulations complexes augmente encore plus les contraintes sur l’amplificateur de puissance. Pour palier ce problème, il est courant de faire appel à des techniques de pré-distorsion. Une contrainte importante dans la mise en oeuvre de cette technique est la numérisation de la sortie de l’amplificateur qui, dû aux non-linéarités, s’étale sur un spectre significativement plus large que le signal utile, environ 5 fois en pratique voire plus. Habituellement, pour cette opération de numérisation, un Convertisseur Analogique Numérique (CAN) du type pipeline est utilisé car il permet d’obtenir des résolutions supérieures à 10 bits sur une bande de plusieurs dizaines voire centaines de MHz. Cependant, sa consommation d’énergie élevée pousse à explorer d’autres pistes. L’architecture "Multi Stage Noise Band Cancellation" (MSNBC) à base de modulateurs Delta Sigma a l’avantage de réaliser des dynamiques différentes par sous bande et est ainsi un candidat de choix pour le CAN de la boucle de retour des techniques de pré-distortion. L’objectif de ce travail est de démontrer la faisabilité de l’architecture MSNBC qui jusqu’à présent a été uniquement étudiée au niveau système. Ces études nous ont permis de proposer une architecture adaptée pour la numérisation d’un signal de bande RF 20 MHz avec des résolutions différentes par sous bande. Une architecture Zéro-IF tempscontinu avec un modulateur primaire du second ordre et un modulateur secondaire du quatrième ordre avec des quantificateurs 4 bits a été adoptée. Cette architecture a été implémentée en une technologie CMOS 65 nm. Les simulations électriques du MSNBC 2-4 avec un signal LTE ont permis d’obtenir 84.5 dB de SNDR dans la bande principale et 29.2 dB dans la bande adjacente contenant les produits d’intermodulation
Power consumption is nowadays one of the main challenges to overcome in the development of mobile communications networks. The power amplifier (PA) is the most power hungry component in base transceiver stations. The upcoming fifth generation of mobile telephony with wider communication bands and complex modulations further increases the constraints on the PA. To overcome this problem, it is common to use predistortion techniques that enable the power amplifier to operate with greater linearity and efficiency. An important constraint in the implementation of this technique is the digitization of the output of the amplifier which, due to non-linearities, spreads over a significantly wider spectrum than the initial signal, about 5 times in practice or even more. Pipeline Analog-to-Digital Converters (ADCs) are commonly used for this operation because it allows resolutions of greater than 10 bits to be obtained over a band of several tens or even hundreds of MHz. However, its high energy consumption pushes to find a better solution. The "Multi Stage Noise Band Cancellation" (MSNBC) architecture based on Delta Sigma modulators has the advantage of realizing different dynamics per subband and is thus a prime candidate for the feedback loop ADC of predistortion techniques. The purpose of this work is to demonstrate the feasibility of the MSNBC architecture that has so far only been studied at the system level. Our investigations allowed us to propose a suitable architecture to digitize a 20 MHz RF band signal with different resolutions per subband. A continuous time Zero-IF architecture with a second-order primary modulator and a fourth-order secondary modulator with 4-bit quantizers was adopted. This architecture has been implemented in a 65 nm CMOS technology. Transistor level simulations of the 2-4 MSNBC architecture simulations with an LTE test signal resulted in 84.5 dB SNDR in the main band and 29.2 dB in the adjacent band which contains the intermodulation products
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Aust, Carrie Ellen. "A Low-Power, Variable-Resolution Analog-to-Digital Converter." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/33737.

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Analog-to-digital converters (ADCs) are used to convert analog signals to the digital domain in digital communications systems. An ADC used in wireless communications should meet the necessary requirements for the worst-case channel condition. However, the worst-case scenario rarely occurs. As a consequence, a high-resolution and subsequently high power ADC designed for the worst case is not required for most operating conditions. A solution to reduce the power dissipation of ADCs in wireless digital communications systems is to detect the current channel condition and to dynamically vary the resolution of the ADC according to the given channel condition. In this thesis, we investigated an ADC that can change its resolution dynamically and, consequently, its power dissipation. Our ADC is a switched-current, redundant signed-digit (RSD) cyclic implementation that easily incorporates variable resolution. Furthermore, the RSD cyclic algorithm is insensitive to offsets, allowing simple, low-power comparators. Our ADC is implemented in a 0.35 um CMOS technology with a single-ended 3.3 V power supply. Our ADC has a maximum power dissipation of 6.35 mW for a 12-bit resolution and dissipates an average of 10 percent less power when the resolution is decreased by two bits. Simulation results indicate our ADC achieves a bit rate of 1.7 MHz and has a SNR of 84 dB for the maximum input frequency of 8.3 kHz.
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Radhakrishnan, Venkataraman. "Design of a low power analog to digital converter in a 130nmCMOS technology." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72700.

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Communication technology has become indispensable in a modernsociety. Its importance is growing day by day. One of the main reasonsbehind this growth is the advancement in the analog and mixed signalcircuit design.Analog to digital converter (ADC) is an essential part in a modernreceiver system. Its development is driven by the progress of CMOStechnologies with an aim to reduce area and power consumption. In thearea of RF integrated circuits for wireless application low operationalvoltage, and less current consumption are the central aspects of thedesign. The aim of this master thesis is the development and design ofa low-power analog to digital converter for RF applications.The basic specifications are:· High Speed, Low Current (1.5 V supply voltage)· Maximum input frequency 3.5 MHz· 8-bit resolution· Sampling rate < 100 MHzThus, this work comprises a theoretical concept phase in whichdifferent ADC topologies will be investigated. Based on which anappropriate ADC architecture will be fixed. Later, the chosen design willbe implemented in an industrial 130 nm CMOS process.
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Danesh, Seyed Amir Ali. "Time interleaved counter analog to digital converters." Thesis, University of Edinburgh, 2011. http://hdl.handle.net/1842/5790.

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The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration.
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Books on the topic "Analog-to-digital converter (ADC)"

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Motorola. Modular microcontroller family ADC analog-to-digital converter reference manual. Phoenix, AZ: Motorola, 1993.

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Ruiz-Amaya, Jesus. Device-level modeling and synthesis of high-performance pipeline ADCs. New York: Springer, 2011.

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Ahmed, Imran. Pipelined ADC design and enhancement techniques. Heidelberg: Springer, 2010.

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1938-, Huijsing Johan H., ed. High-resolution IF-to-baseband [Sigma-Delta] ADC for car radios. [New York]: Springer, 2008.

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Murmann, Boris. Digitally assisted pipeline ADCs: Theory and implementation. Boston: Kluwer Academic Publishers, 2004.

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Cao, Zhiheng. Low-Power High-Speed ADCs for Nanometer CMOS Integration. Dordrecht: Springer Science + Business Media B.V, 2008.

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C, Vital João, and Franca José, eds. Systematic design for optimisation of pipelined ADCs. Boston: Kluwer Academic Publishers, 2001.

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Jiang, Linda. DsPIC33E/PIC24E FRM - Section 16. Analog-To-Digital Converter (ADC). Microchip Technology Incorporated, 2016.

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Mahar, Nanci. Using the Analog-To-Digital Converter with Computation (ADC²) Module. Microchip Technology Incorporated, 2018.

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Zhu, Juliet. FRM PIC32 Section 17. 10-Bit Analog-to-Digital Converter (ADC). Microchip Technology Incorporated, 2014.

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Book chapters on the topic "Analog-to-digital converter (ADC)"

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Gadre, Dhananjay V., and Sarthak Gupta. "Analog to Digital Converter (ADC)." In Getting Started with Tiva ARM Cortex M4 Microcontrollers, 183–209. New Delhi: Springer India, 2017. http://dx.doi.org/10.1007/978-81-322-3766-2_14.

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Asadi, Farzin. "Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC)." In Essentials of Arduino™ Boards Programming, 127–59. Berkeley, CA: Apress, 2023. http://dx.doi.org/10.1007/978-1-4842-9600-4_3.

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Karmakar, Supriya. "Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) Using Quantum Dot Gate Field-Effect Transistor (QDGFET)." In Novel Three-state Quantum Dot Gate Field Effect Transistor, 81–104. New Delhi: Springer India, 2013. http://dx.doi.org/10.1007/978-81-322-1635-3_7.

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Kutre, Tejaswini Jayawant, Sujata N. Patil, Sheela Kore, and V. M. Aparanji. "Advanced Architecture of Analog to Digital Converter Derived from Half Flash ADC." In Lecture Notes in Electrical Engineering, 141–51. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2281-7_14.

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Anh, Phan Vo Kim, and Hoang Trang. "Retracted: A Pipelined Analog – To – Digital Converter (ADC) Using Umc 0.25μm Technology for Pacemaker Application." In IFMBE Proceedings, 47–49. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-32183-2_13.

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Anh, Phan Vo Kim, and Hoang Trang. "Retraction Note to: A Pipelined Analog – To – Digital Converter (ADC) Using Umc 0.25μm Technology for Pacemaker Application." In IFMBE Proceedings, E1. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-32183-2_96.

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Louwsma, Simon, Ed van Tuijl, and Bram Nauta. "Sub-ADC Architectures for Time-interleaved ADCs." In Time-interleaved Analog-to-Digital Converters, 39–69. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-90-481-9716-3_3.

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Ohnhäuser, Frank. "Advanced SAR ADC Design." In Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Converters, 119–206. Berlin, Heidelberg: Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-47020-6_3.

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Louwsma, Simon, Ed van Tuijl, and Bram Nauta. "Implementation of a High-speed Time-interleaved ADC." In Time-interleaved Analog-to-Digital Converters, 71–124. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-90-481-9716-3_4.

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Verbruggen, Bob. "Digitally Assisted Analog to Digital Converters." In High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing, 25–44. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-07938-7_2.

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Conference papers on the topic "Analog-to-digital converter (ADC)"

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Prusten, Mark J., and Arthur F. Gmitro. "An Optical Flash Analog to Digital Converter." In Optical Computing. Washington, D.C.: Optica Publishing Group, 1995. http://dx.doi.org/10.1364/optcomp.1995.otue3.

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Fast analog-to-digital (A/D) converters are important in a number of applications. Several systems have been proposed for fast A/D converters using optical technology1-4. The most common types of converters are the successive approximation and Flash converters. In a Flash converter there is a separate comparator for each possible output bit code. Each comparator is biased with a reference level that is a specific increment of the full scale value. Since comparators in a Flash converter operate in parallel, this architecture is intrinsically fast. However, as the accuracy requirements increase, the number of comparators increases as 2N where N is the number of bits. In the case of an 8 bit Flash ADC, there are 256 comparators. The 256 comparator output signals are routed to a decoder circuit that produces and 8 bit digital word. The schematic for a Flash converter is shown in Fig. 1. The focus of this paper is on a new implementation of an 8 bit Flash converter utilizing optical technologies.
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Larson, Eric D. "Serial pixel analog-to-digital converter (ADC)." In OPTO, edited by Shibin Jiang, Michel J. F. Digonnet, John W. Glesener, and J. Christopher Dries. SPIE, 2010. http://dx.doi.org/10.1117/12.845801.

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Abhirami, S., D. Vishnu, S. Sreelal, A. Sajeena, and Anu Assis. "Second-order Oversampled Delta-sigma Analog to Digital Converter." In 2nd International Conference on Modern Trends in Engineering Technology and Management. AIJR Publisher, 2023. http://dx.doi.org/10.21467/proceedings.160.18.

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The Delta Sigma modulation technology has been around for a while, but because of technological advancements, the devices are now more widely used and feasible. The work proposes a multi-bit Delta Sigma ADC of second order having a very low power consumption. MATLAB Simulink is used to develop both the Delta Sigma ADCs of first and second order and the digital output is passed through a digital filter to recreate the original signal. According to simulation results, at 100 KHz frequency of output sampling, the Delta-Sigma modulator exhibits a Spurious Free Dynamic Range of 95.38 dB, and also it demonstrates that the designed Delta-Sigma ADC is capable of achieving an ENOB (Effective Number of Bits) of 11.83 bits and an SNR of 72.99 dB.
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Takhti, Mohammad, Amir M. Sodagar, and Reza Lotfi. "Domino ADC: A novel analog-to-digital converter architecture." In 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010. IEEE, 2010. http://dx.doi.org/10.1109/iscas.2010.5537633.

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Bakar, Faizah Abu, Tero Nieminen, Qaiser Nehal, Pekka Ukkonen, Ville Saari, and Kari Halonen. "Analog baseband chain with analog to digital converter (ADC) of Synthetic Aperture Radar (SAR) receiver." In ESSCIRC 2011 - 37th European Solid State Circuits Conference. IEEE, 2011. http://dx.doi.org/10.1109/esscirc.2011.6044901.

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Pribadi, Eka Fitrah, Rajeev Kumar Pandey, and Paul C. P. Chao. "A High-Resolution and Low Offset Delta-Sigma Analog to Digital Converter for Detecting Photoplethysmography Signal." In ASME 2021 30th Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2021. http://dx.doi.org/10.1115/isps2021-65248.

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Abstract A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.
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Mei Yee Ng. "0.18um low voltage 12-bit successive-approximation-register analog-to-digital converter (SAR ADC)." In 2011 3rd Asia Symposium on Quality Electronic Design (ASQED 2011). IEEE, 2011. http://dx.doi.org/10.1109/asqed.2011.6111760.

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Yip, T. Gary, and Elizabeth B. Nadworny. "A Successive Approximation ADC Simulation Project." In ASME 1992 International Computers in Engineering Conference and Exposition. American Society of Mechanical Engineers, 1992. http://dx.doi.org/10.1115/cie1992-0067.

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Abstract This paper describes a three week long project designed for first year graduate students in mechanical engineering taking a course in Modern Instrumentation. The project entails constructing a successive approximation analog-to-digital converter without a controller, developing a control sequence, and implementing it to produce a digital representation of an analog input voltage. The course is made up of a series of laboratory activities that start with the fundamentals of equipment control and data acquisition, then increase in difficulty by requiring students to develop systems and control sequences on their own. The project teaches computer based data acquisition skills, the fundamental logic of a successive approximation ADC, and provides hands on experience using digital signals to control a system.
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McCoy, Michael, Christopher Isert, Douglas Jackson, and John Naber. "A Frequency Counter Based Analog-to-Digital Converter for a Low-Power RFID Biomedical Telemetry System." In ASME 2007 2nd Frontiers in Biomedical Devices Conference. ASMEDC, 2007. http://dx.doi.org/10.1115/biomed2007-38114.

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This paper describes a method for determining a digital representation of a remote sensing element using a novel and lower power method of analog to digital conversion [1]. This conversion process is most effective for low-frequency and very low current Radio Frequency Identification (RFID) sensing systems where the sensing element tags are powered by an inductively coupled carrier signal of fixed frequency. This method eliminates the need for a traditional, large and power-hungry Analog-to-Digital Converter (ADC). This approach is being developed for an orthopedic application that measures the invivo strain on titanium rods to help surgeons better understand the progress of fusion in spinal fusion surgery [2]. Previous work has been shown using the difference of two clocks for sending digital data from the reader to the tag [3], whereas this approach is optimized for sending digital data in the other direction, from tag to the reader. The sensor element may be a resistive or capacitive device integrated into an oscillator of variable frequency. This variable oscillation signal is then divided down and used as the time base to a frequency counter clocked by the recovered carrier signal. In recovering and using the carrier signal as an internal clock, an additional on chip oscillator is not necessary. The resultant value then undergoes additional post processing to add a unique identification string, a CRC check word, Manchester encoding, and Frequency-Shift Key (FSK) encoding for load modulation transmission [3,4].
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Quah, A. C. T., C. Q. Chen, G. B. Ang, D. Nagalingam, Y. Li, J. Zhu, S. P. Neo, and S. P. Zhao. "Applications of Nanoprobing for Localization of Design for Manufacturing Issues on Analogue-to-Digital Converter on Advanced Technology Node." In ISTFA 2013. ASM International, 2013. http://dx.doi.org/10.31399/asm.cp.istfa2013p0260.

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Abstract This paper describes 2 case studies where device characterizations using Atomic Force Probe (AFP) nanoprobing, allow for the localization and verification of design weakness and process variations on the Analog-to-Digital (ADC) block that resulted in degraded device performance and severe yield loss. In these cases, the sensitive resistor structures in the ADC block was impacted due to design pattern density interaction with process fabrication steps. In addition, close collaboration with customer was also essential for quick root cause identification, design and process fix.
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Reports on the topic "Analog-to-digital converter (ADC)"

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Bowers, M., B. Deri, R. Haigh, M. Lowry, P. Sargis, R. Stafford, and T. Tong. LDRD final report: photonic analog-to-digital converter (ADC) technology. Office of Scientific and Technical Information (OSTI), February 1999. http://dx.doi.org/10.2172/13923.

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Mahurin, Eric, and Ray Siford. GaAs Sigma-Delta Modulator Modeling for Analog to Digital Converters (ADCS). Fort Belvoir, VA: Defense Technical Information Center, December 1992. http://dx.doi.org/10.21236/ada263419.

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