Journal articles: 'Analog-to-digital converter (ADC)'

1

Wang, Weihe, and Hongqi Yu. "Pipelined Memristive neural network analog-to-digital converter." Journal of Physics: Conference Series 2632, no. 1 (November 1, 2023): 012004. http://dx.doi.org/10.1088/1742-6596/2632/1/012004.

Full text

Abstract:

Abstract This paper designs a pipelined memristive neural network ADCs. Cascade the sub stages of memristive neural network ADC with pipeline structure to improve the conversion accuracy of memristive neural network ADC. First, the signal flow of the pipeline architecture is optimized, and the compatibility between the 4 bit memristive neural network ADC and the pipeline architecture is solved. Secondly, the application of random disturbance circuits in pipeline architecture was analyzed. Combining the calibration circuit with the pipeline DAC to reduce the power consumption of the calibration circuit. Finally, the circuit model of memristive neural network ADC is built and compared with the existing memristive neural network ADC. The results indicate that the pipeline structure ADC designed in this chapter has the advantage of adaptive calibration in terms of calibration function.

APA, Harvard, Vancouver, ISO, and other styles

2

Chauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 31, 2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.

Full text

Abstract:

After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.

APA, Harvard, Vancouver, ISO, and other styles

3

Faure, Nicolaas, and Saurabh Sinha. "High-speed Cherry Hooper flash analog-to-digital converter." Microelectronics International 34, no. 1 (January 3, 2017): 22–29. http://dx.doi.org/10.1108/mi-08-2015-0075.

Full text

Abstract:

Purpose The 60 GHz unlicensed band is being utilized for high-speed wireless networks with data rates in the gigabit range. To successfully make use of these high-speed signals in a digital system, a high-speed analog-to-digital converter (ADC) is necessary. This paper aims to present the use of a common collector (CC) input tree and Cherry Hooper (C-H) differential amplifier to enable analog-to-digital conversion at high frequencies. Design/methodology/approach The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain bandwidth speeds higher than the comparator stages while using less current than the comparator stages. The C-H differential amplifier is modified to accommodate the low breakdown voltages of the technology node and implemented as a comparator. The comparator stages are biased to obtain a high output voltage swing and have a small signal bandwidth up to 29 GHz. Simulations were performed using foundry development kits to verify circuit operation. A two-bit ADC was prototyped in IBM’s 130 nm SiGe BiCMOS 8HP technology node. Measurements were carried out on test printed circuit boards and compared with simulation results. Findings The use of the added CC input tree showed a simulated bandwidth improvement of approximately 3.23 times when compared to a basic flash architecture, for a two-bit ADC. Measured results showed an effective number of bits (ENOB) of 1.18, from DC up to 2 GHz, whereas the simulated result was 1.5. The maximum measured integral non-linearity and differential non-linearity was 0.33 LSB. The prototype ADC had a figure of merit of 42 pJ/sample. Originality/value The prototype ADC results showed that the group delay for the C-H comparator plays a critical role in ADC performance for high frequency input signals. For minimal component variation, the group delay between channels deviate from each other, causing incorrect output codes. The prototype ADC had a low gain which reduced the comparator performance. The two-bit CC C-H ADC is capable of achieving an ENOB close to 1.18, for frequencies up to 2 GHz, with 180 mW total power consumption.

APA, Harvard, Vancouver, ISO, and other styles

4

Wang, Li, Wenli Chen, Kai Chen, Renjun He, and Wenjian Zhou. "The Research on the Signal Generation Method and Digital Pre-Processing Based on Time-Interleaved Digital-to-Analog Converter for Analog-to-Digital Converter Testing." Applied Sciences 12, no. 3 (February 7, 2022): 1704. http://dx.doi.org/10.3390/app12031704.

Full text

Abstract:

In the high-resolution analog circuit, the performance of chips is an important part. The performance of the chips needs to be determined by testing. According to the test requirements, stimulus signal with better quality and performance is necessary. The main research direction is how to generate high-resolution and high-speed analog signal when there is no suitable high-resolution and high-speed digital-to-analog converter (DAC) chip available. In this paper, we take the high-resolution analog-to-digital converter (ADC) chips test as an example; this article uses high-resolution DAC chips and multiplexers to generate high-resolution high-speed signals that can be used for testing high-resolution ADC chips based on the principle of time-alternating sampling. This article explains its method, analyzes its error and proposes a digital pre-processing method to reduce the error. Finally, the actual circuit is designed, and the method is verified on the circuit. The test results prove the effectiveness of this method for generating high-resolution ADC test signals.

APA, Harvard, Vancouver, ISO, and other styles

5

Park, Joonsung, Jiwon Lee, Jacob A. Abraham, and Byoungho Kim. "A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter." Electronics 13, no. 4 (February 13, 2024): 755. http://dx.doi.org/10.3390/electronics13040755.

Full text

Abstract:

The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as Cn=2×Cn−1, the variable capacitor Cn of ADC1 can be updated to be closest to the sum of Cn−1 of ADC1 and Cn−1 of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the Cn of ADC1 can be connected with two of the Cn−1 of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update Cn. This process is iterated, until Cn is in agreement with the sum of two of Cn−1. Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by 21.8 dB and 6.4 dB, respectively.

APA, Harvard, Vancouver, ISO, and other styles

6

Bialek, J., A. Wickmann, F. Ohnhaeuser, G. Fischer, R. Weigel, and T. Ussmueller. "Implementation of a digital trim scheme for SAR ADCs." Advances in Radio Science 11 (July 4, 2013): 227–30. http://dx.doi.org/10.5194/ars-11-227-2013.

Full text

Abstract:

Abstract. Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.

APA, Harvard, Vancouver, ISO, and other styles

7

Anvekar, Dinesh K., and B. S. Sonde. "Programmable Nonlinear Adc: An Illustrative Example." International Journal of Electrical Engineering & Education 33, no. 3 (July 1996): 216–24. http://dx.doi.org/10.1177/002072099603300303.

Full text

Abstract:

Programmable nonlinear ADC: an illustrative example Programmable nonlinear analog-to-digital conversion is a new topic in EE curricula. With a view to introducing the EE student to the concept of transfer characteristic programmability of an analog-to-digital converter (ADC), a memory-prefetch programmable nonlinear ADC is presented. The design, analytical evaluation, and experimental implementation for the ADC are described.

APA, Harvard, Vancouver, ISO, and other styles

8

Liu, Xiaolu, Jin Shao, Peng Zhang, Guoyu Cui, and Haifeng Qian. "Multi-channel and high-precision analog-to-digital converter chips for power grid detection." Journal of Physics: Conference Series 2584, no. 1 (September 1, 2023): 012139. http://dx.doi.org/10.1088/1742-6596/2584/1/012139.

Full text

Abstract:

Abstract This project focuses on the research of high-precision multi-channel analog-to-digital converter chips for power grid detection and system applications. There have been breakthroughs made in a series of key technologies, such as successive approximation ADC architecture, oversampling ADC architecture, and digital calibration technology. By combining it with multi-channel ADC to achieve high-precision multi-channel analog-to-digital converter design, it provides strong support for China to achieve autonomous and controllable high-precision multi-channel ADC chips and has extremely high application value.

APA, Harvard, Vancouver, ISO, and other styles

9

Li, Donggen. "Comparative Study of High Speed ADCs." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 146–52. http://dx.doi.org/10.54097/hset.v27i.3731.

Full text

Abstract:

With the development of information technology, analog-to-digital converter (ADC) is widely used. In products such as radar, ultra wideband communication system, high-performance digital oscilloscope and so on, the speed performance of analog-to-digital converter is usually the bottleneck of the whole system performance, so the research of high-speed ADC has attracted much attention. ADC is an interface circuit that converts analog signals into digital signals that can be processed by DSP. This paper will start with the basic knowledge of ADC, explain the general working process of ADC, introduce several architectures and working principles suitable for high-speed ADC, and compare and analyze their advantages and disadvantages.

APA, Harvard, Vancouver, ISO, and other styles

10

Mr. Nikhil Surkar, Ms. Shriya Timande. "Analysis of Analog to Digital Converter for Biomedical Applications." International Journal of New Practices in Management and Engineering 1, no. 03 (September 30, 2012): 01–07. http://dx.doi.org/10.17762/ijnpme.v1i03.6.

Full text

Abstract:

This paper presents an ADC which can be used for biomedical application like pacemaker. For the low-power operation, monotonic switching scheme and operating voltage reduction have been implemented in the design. The 10bit 1.8V rail-to-rail (SAR) ADC is realized using UMC 0.18µm CMOS process. Simulations are performed by spectre simulation. From static performance, offset error and full scale error are noticed. This performance issue can be corrected by reducing discharge in capacitor by implementing sampling switch as bootstrapped switch and proper selection of common-mode voltage where 20fF is used as unit capacitance.

APA, Harvard, Vancouver, ISO, and other styles

11

NING, NING, LING DU, HUA CHEN, SHUANGYI WU, QI YU, and YANG LIU. "A DITHERING TECHNIQUE FOR SHA_LESS PIPELINED ADC." Journal of Circuits, Systems and Computers 23, no. 01 (January 2014): 1450006. http://dx.doi.org/10.1142/s0218126614500066.

Full text

Abstract:

A dithering technique for pipelined analog-to-digital converter (ADC) without sample-and-hold amplifier (SHA) is proposed in this paper. The dither signals are injected to the output of the first stage multiplying digital-to-analog converter (MDAC) and the input of the first stage Sub_ADC simultaneously. The equivalent input voltage of the first stage Sub_ADC is consistent with that of the first stage MDAC with dither. To subtract the dither signal precisely, all of the dither signals are quantified by the ADC itself before normal conversion, and the digital codes representing dither signals are stored. During normal conversion, a dither signal selected randomly is added to the analog input and the corresponding digital code is subtracted from the digital output. The proposed dithering technique is verified by behavior simulation. The simulation results show that the spurious free dynamic range (SFDR) is improved effectively and the degradation of signal-to-noise ratio (SNR) can be minimized.

APA, Harvard, Vancouver, ISO, and other styles

12

Seo, Dong-Hwan, Sunghoon Cho, Jung-Gyun Kim, and Byung-Geun Lee. "A Self-Calibration of Capacitor Mismatch Error for Pipeline ADCs." Applied Sciences 13, no. 22 (November 14, 2023): 12322. http://dx.doi.org/10.3390/app132212322.

Full text

Abstract:

This study proposes self-calibration of capacitor mismatch errors for high-resolution pipeline analog-to-digital converters (ADCs). The proposed calibration circuit recursively amplifies the capacitor mismatch error by re-utilizing a multiplying digital-to-analog converter in a pipeline stage without increasing the circuit complexity, and the amplified error voltage is converted into digital code by utilizing the remaining pipeline stages. Error correction is performed by subtracting the digital code from the ADC output during normal operation. A prototype of a 12-bit pipeline ADC is fabricated in a 0.18 µm standard CMOS process. The ADC comprises eight 1.5-bit stages, followed by a 4-bit flash ADC as the final stage; the capacitor mismatch errors in the first two pipeline stages are corrected by utilizing the proposed self-calibration technique. Although the calibration method is employed in a 1.5-bit stage architecture, which uses a gain-of-two switched-capacitor amplifier, it is applicable to different bit-per-stage architectures. The ADC linearity significantly improves after calibration, and this is verified through simulations and measurements.

APA, Harvard, Vancouver, ISO, and other styles

13

Gaude, Disha, Bathini Poornima, Sudharshan K. M., and Prashant V. Joshi. "Design and Simulation of 4-Bit Flash Analog to Digital Converter (ADC) for High Speed Applications." Indian Journal of Science and Technology 12, no. 36 (September 20, 2019): 1–7. http://dx.doi.org/10.17485/ijst/2019/v12i36/148021.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Laoudias, Costas, George Souliotis, and Fotis Plessas. "A High ENOB 14-Bit ADC without Calibration." Electronics 13, no. 3 (January 31, 2024): 570. http://dx.doi.org/10.3390/electronics13030570.

Full text

Abstract:

This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, without using any calibration mechanism for fast power-on operation. The CDAC capacitor unit has been optimized for improved linearity without calibration technique. The SAR ADC has a differential input range 3.6 Vpp, with a SNDR of 80.45 dB, ENOB of 13.07, SFDR of 87.16 dB and dissipates an average power of 0.8 mW, while operating at 2.5 V/1 V for analog/digital power supply. The INL and DNL is +0.22/−0.34 LSB and +0.42/−0.3 LSB, respectively. A prototype ADC has been fabricated in a conventional CMOS 65 nm technology process.

APA, Harvard, Vancouver, ISO, and other styles

15

Miyata, Takeo, Satoshi Nidaira, Kazushi Shimizu, and Kousuke Tsukamoto. "An Analog-to-Digital Converter with Frequency Dependent Effective Resolution." IEEJ Transactions on Electronics, Information and Systems 112, no. 4 (1992): 216–20. http://dx.doi.org/10.1541/ieejeiss1987.112.4_216.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Chen, Guo Ping, Xian Zhong Jian, and Er Liang Xiao. "Design and Simulation of a Pipeline Analog-to-Digital Converter." Applied Mechanics and Materials 182-183 (June 2012): 1154–58. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.1154.

Full text

Abstract:

The pipeline Analog-to-Digital Converter is highlight for its high resolution, accuracy, speed and low power consumption. In this paper, we have completed the design and simulation of a pipeline ADC with the SIMULINK toolbox of MATLAB. The model of 1.5 bit per stage was set up, and nine stages were connected to establish the system model. The system model can work correctly at 100MHz sampling frequency and reach 10 bit resolution. The simulation results can verify the correction of the pipeline ADC theory.

APA, Harvard, Vancouver, ISO, and other styles

17

Chavhan, Sarvesh S., and K. M. Bogawar. "Energy Efficient Quaternary Capacitive DAC Switching Scheme for SAR -ADC." Journal of Advance Research in Electrical & Electronics Engineering (ISSN: 2208-2395) 2, no. 6 (June 30, 2015): 13–16. http://dx.doi.org/10.53555/nneee.v2i6.191.

Full text

Abstract:

This paper presents energy efficient 4-bit successive approximation register analog to digital converter (SAR-ADC) for neural recording front end interface of neural prosthetic system(Brain machine interface). The energy efficient quaternary capacitive switching scheme (QCS) in the implementation of capacitive digital to analog converter (C-DAC) is employed which makes the energy consumption in the C-DAC independent of the output digital code. The proposed quaternary capacitive technique in C-DAC achieves a 50% reduction in the average energy consumption. The design is implemented in 0.25um standard complementary metal-oxide semiconductor technology (CMOS).

APA, Harvard, Vancouver, ISO, and other styles

18

Arafa, Kawther I., Dina M. Ellaithy, Abdelhalim Zekry, Mohamed Abouelatta, and Heba Shawkey. "Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications." Active and Passive Electronic Components 2023 (January 4, 2023): 1–29. http://dx.doi.org/10.1155/2023/3669255.

Full text

Abstract:

This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

APA, Harvard, Vancouver, ISO, and other styles

19

Kelly, Brandon M., Alexander T. DiLello, and David W. Graham. "Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion." Journal of Low Power Electronics and Applications 9, no. 3 (August 12, 2019): 25. http://dx.doi.org/10.3390/jlpea9030025.

Full text

Abstract:

Wearable medical devices, wireless sensor networks, and other energy-constrained sensing devices are often concerned with finding specific data within more-complex signals while maintaining low power consumption. Traditional analog-to-digital converters (ADCs) can capture the sensor information at a high resolution to enable a subsequent digital system to process for the desired data. However, traditional ADCs can be inefficient for applications that only require specific points of data. This work offers an alternative path to lower the energy expenditure in the quantization stage—asynchronous content-dependent sampling. This asynchronous sampling scheme is achieved by pairing a flexible analog front-end with an asynchronous successive-approximation ADC and a time-to-digital converter. The versatility and reprogrammability of this system allows a multitude of event-driven, asynchronous, or even purely data-driven quantization methods to be implemented for a variety of different applications. The system, fabricated in standard 0.5 μ m and 0.35 μ m processes, is demonstrated along with example applications with voice, EMG, and ECG signals.

APA, Harvard, Vancouver, ISO, and other styles

20

Fahmy, Ghazal A., and Mohamed Zorkany. "Design of a Memristor-Based Digital to Analog Converter (DAC)." Electronics 10, no. 5 (March 7, 2021): 622. http://dx.doi.org/10.3390/electronics10050622.

Full text

Abstract:

A memristor element has been highlighted in recent years and has been applied to several applications. In this work, a memristor-based digital to analog converter (DAC) was proposed due to the fact that a memristor has low area, low power, and a low threshold voltage. The proposed memristor DAC depends on the basic DAC cell, consisting of two memristors connected in opposite directions. This basic DAC cell was used to build and simulate both a 4 bit and an 8 bit DAC. Moreover, a sneak path issue was illustrated and its solution was provided. The proposed design reduced the area by 40%. The 8 bit memristor DAC has been designed and used in a successive approximation register analog to digital converter (SAR-ADC) instead of in a capacitor DAC (which would require a large area and consume more switching power). The SAR-ADC with a memristor-based DAC achieves a signal to noise and distortion ratio (SNDR) of 49.3 dB and a spurious free dynamic range (SFDR) of 61 dB with a power supply of 1.2 V and a consumption of 21 µW. The figure of merit (FoM) of the proposed SAR-ADC is 87.9 fj/Conv.-step. The proposed designs were simulated with optimized parameters using a voltage threshold adaptive memristor (VTEAM) model.

APA, Harvard, Vancouver, ISO, and other styles

21

Yurish, Sergey Y. "Advanced Analog-to-Digital Conversion Using Voltage-to-Frequency Converters for Remote Sensors." Key Engineering Materials 381-382 (June 2008): 623–26. http://dx.doi.org/10.4028/www.scientific.net/kem.381-382.623.

Full text

Abstract:

This paper presents an advanced analog-to-digital conversion technique based on a voltage-to-frequency-to-digital conversion that is suitable for remote sensors, telemetry applications and multichannel data acquisition systems. A voltage-to-frequency conversion part can be based, for example, on high performance, charge-balance voltage-to-frequency converter (VFC), where monostable is replaced by a bistable, driven by an external clock, or other existing high performance VFCs. The frequency-to-digital converter “bottleneck” problem in such promised ADC scheme was solved due to proposed advanced method of the dependent count for frequency-to-digital conversion. This ADC technique lets receive many advantages such as high accuracy, relatively low power consumption, low cost solution, wide dynamic range, great stability and faster conversion time in comparison with existing VFC-based techniques. The conversion rate (6.25 µs to 6.25 ms) in such ADC scheme is programmable, non-redundant, shorter than for pulse counting technique and comparable with successive-approximation and Σ- ADC.

APA, Harvard, Vancouver, ISO, and other styles

22

Belega, Daniel, and Dan Stoiciu. "Polynomial approximation of the transfer function of an analog-to-digital converter." Facta universitatis - series: Electronics and Energetics 17, no. 3 (2004): 443–53. http://dx.doi.org/10.2298/fuee0403443b.

Full text

Abstract:

In this paper the polynomial approximation of the transfer function of an analog-to-digital converter (ADC) affected by harmonic distortions is investigated. The theoretical expression of the polynomial approximation of the transfer function of an ADC with harmonic components up to 5th order in the case of a sine wave test signal is derived. Also, a practical method to determine the polynomial approximation of an ADC is proposed. The simulation effected confirmed that the results obtained by this method are very accurate. Moreover, an ADC test system, developed to determine the polynomial approximation of the transfer function of an ADC by the proposed method is presented. Some experimental results obtained with this test system are given.

APA, Harvard, Vancouver, ISO, and other styles

23

Zhao, Xing Sheng, Xiao Jun Wang, Dan Niu, and Chao Li. "Voltage Measurement with Improved Multi-Slope Integral Analog-to-Digital Converter." Applied Mechanics and Materials 742 (March 2015): 90–94. http://dx.doi.org/10.4028/www.scientific.net/amm.742.90.

Full text

Abstract:

This paper presents a 20 Hz to 200K Hz alternating current (AC) and direct current (DC) analog-to-digital converter (ADC). The strange to minimize the zero crossing noise adopts hysteresis comparison technique. Multi-slope integral technique is also employed to enhance measurement accuracy. Furthermore, an algorism is designed to eliminate measure error. The prototype ADC achieves millivolt precision.

APA, Harvard, Vancouver, ISO, and other styles

24

Wang, Deming, Jing Hu, Xin Huang, and Qinghua Zhong. "Design of a 12-Bit SAR ADC with Calibration Technology." Electronics 13, no. 3 (January 30, 2024): 548. http://dx.doi.org/10.3390/electronics13030548.

Full text

Abstract:

Successive approximation register (SAR) analog-to-digital converters (ADC) have the advantages of a simple structure, low power consumption and a small area compared with other types of ADCs, and thus, high-performance SAR ADCs have always been a hot research topic in the industry. In this paper, a 12-bit SAR ADC design with calibration using a hybrid RC digital-to-analog converter(RC DAC) structure is proposed to improve the conversion accuracy of the ADC and reduce the circuit area at the same time. The analog supply voltage and reference voltage of the ADC are 3.3 V, and the digital supply voltage is 1.2 V. The ADC adopts a mixed digital–analog design scheme, in which the internal comparator, latch, DAC capacitor array, etc., are analog parts, and the rest of the SAR algorithms and calibration algorithms are all implemented in digital Verilog code, with a conversion accuracy of 0.8 mV and a calibration accuracy of 0.5 LSB. The ADC can be selectively calibrated, and the simulation shows that the accuracy of the calibrated ADC can be guaranteed to be within 2 LSB under a 14 MHz digital clock with a sampling rate of 1 MHz. After simulation at a sampling rate of 1 MHz and an input frequency of 244 Hz sine wave, the effective bit count of the ADC is 9.54 bits and the SFDR is 63.71 dB. The circuit consumes 1.78 mW with a 3.3 V supply voltage. The overall layout core area is 411 μm × 517 μm.

APA, Harvard, Vancouver, ISO, and other styles

25

Banu, Sufia, and Shweta Gupta. "Low Power Analog to Digital Converter for Neuro Stimulator using Cadence Tool." Journal of Physics: Conference Series 2325, no. 1 (August 1, 2022): 012005. http://dx.doi.org/10.1088/1742-6596/2325/1/012005.

Full text

Abstract:

Abstract A Digital-to-Analog Converter (ADC) converts various forms of communication in the real world to portable digital integers. ADCs play a vital role as it interfaces between the analog world and digital world. Wireless sensor networks and biomedical interfaces are common examples of applications that demand ultra-low power consumption in the ADC. This research paper shows reduction in the energy consumption of an ADC used in neurostimulator which stimulates the brain for the people suffering from various disorders which includes Tumours, Parkinson’s disease, Obsessive Compulsive Disorder (OCD), Epilepsy, and many more. The simulation is carried out by Cadence Virtuoso tool using various technologies.

APA, Harvard, Vancouver, ISO, and other styles

26

Jung, Inseok, Kyung Ki Kim, and Yong-Bin Kim. "A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC." Journal of Integrated Circuits and Systems 10, no. 3 (December 28, 2015): 187–200. http://dx.doi.org/10.29292/jics.v10i3.422.

Full text

Abstract:

This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.

APA, Harvard, Vancouver, ISO, and other styles

27

Bchir, Mounira, Thouraya Ettaghzouti, and Néjib Hassen. "A Novel High Frequency Low Voltage Low Power Current Mode Analog to Digital Converter Pipeline." Journal of Low Power Electronics 15, no. 4 (December 1, 2019): 368–78. http://dx.doi.org/10.1166/jolpe.2019.1621.

Full text

Abstract:

This paper introduces a novel structure for the realization of a low voltage, low power current-mode analog to the digital converter (ADC) pipeline (12 bits). The proposed structure of the ADC is based on a novel design of a current comparator and Digital to Analog Converter (DAC) structure. This modification allows us to reach a higher speed, lower voltage, and lower power dissipation. ELDO simulators using 0.18 μm, CMOS and TSMC parameters are performed to confirm the workability of this architecture. The proposed ADC is powered with a 1 V supply voltage. It is characterized by wide conversion frequency (350 MHz) and low power consumption that is 2.76 mW.

APA, Harvard, Vancouver, ISO, and other styles

28

Jovanović, Jelena, and Dragan Denić. "A Cost-effective Method for Resolution Increase of the Twostage Piecewise Linear ADC Used for Sensor Linearization." Measurement Science Review 16, no. 1 (February 1, 2016): 28–34. http://dx.doi.org/10.1515/msr-2016-0005.

Full text

Abstract:

Abstract A cost-effective method for resolution increase of a two-stage piecewise linear analog-to-digital converter used for sensor linearization is proposed in this paper. In both conversion stages flash analog-to-digital converters are employed. Resolution increase by one bit per conversion stage is performed by introducing one additional comparator in front of each of two flash analog-to-digital converters, while the converters’ resolutions remain the same. As a result, the number of employed comparators, as well as the circuit complexity and the power consumption originating from employed comparators are for almost 50 % lower in comparison to the same parameters referring to the linearization circuit of the conventional design and of the same resolution. Since the number of employed comparators is significantly reduced according to the proposed method, special modifications of the linearization circuit are needed in order to properly adjust reference voltages of employed comparators.

APA, Harvard, Vancouver, ISO, and other styles

29

Quenzer-Hohmuth, Samuel, Thoralf Rosahl, Steffen Ritzmann, and Bernhard Wicht. "Challenges and implementation aspects of switched-mode power supplies with digital control for automotive applications." Advances in Radio Science 14 (September 28, 2016): 85–90. http://dx.doi.org/10.5194/ars-14-85-2016.

Full text

Abstract:

Abstract. Switched-mode power supplies (SMPS) convert an input DC-voltage into a higher or lower output voltage. In automotive, analog control is mostly used in order to keep the required output voltages constant and resistant to disturbances. The design of robust analog control for SMPS faces parameter variations of integrated and external passive components. Using digital control, parameter variations can be eliminated and the required area for the integrated circuit can be reduced at the same time. Digital control design bears challenges like the prevention of limit cycle oscillations and controller-wind-up. This paper reviews how to prevent these effects. Digital control loops introduce new sources for dead times in the control loop, for example the latency of the analog-to-digital-converter (ADC). Dead times have negative influence on the stability of the control loop, because they lead to phase delays. Consequently, low latency is one of the key requirements for analog-to-digital-converters in digitally controlled SMPS. Exploiting the example of a 500 kHz-buck converter with a crossover frequency of 70 kHz, this paper shows that the 5 µs-latency of a ΔΣ-analog-to-digital-converter leads to a reduction in phase margin of 126°. The latency is less critical for boost converters because of their inherent lower crossover frequencies. Finally, the paper shows a comparison between analog and digital control of SMPS with regard to chip area and test costs.

APA, Harvard, Vancouver, ISO, and other styles

30

Marcinkevičius, Albinas J., and V. Jasonis. "The Calculation of Dynamic Errors in Signal Transformation Circuits of Analog-to-Digital Converters for Mechatronic Systems." Solid State Phenomena 113 (June 2006): 131–36. http://dx.doi.org/10.4028/www.scientific.net/ssp.113.131.

Full text

Abstract:

Precision and wide-band analog-to-digital converters (ADC) are used for information processing in mechatronic systems. The analog signal transformation circuits, such as sample, and hold circuit (SHC) and an analog signal interpolation circuit (ASIC), are applied with the aim of increasing the precision of converters. These circuits allow for reducing the quantity of comparators in the converter and increase their dynamic stability. The models of SHC and ASIC as well as the results of the calculation precision and dynamic parameters of such circuits are presented in this paper. Equations for the calculation of the aperture error in the Gaussian and a sinusoidal input signal were derived. The structural model, proposed for SHC, evaluates the nonlinearity of a transfer characteristic, and the influence of noise in the signal and strobe channels. The results of the theoretical research and analytical equations for the evaluation of the number of signal interpolation block differential amplifiers, which depends on the analog signal’s maximal frequency and the number of segments of the converter, are presented. The results of this work allow one to estimate the main precision and dynamic parameters of ADC transformation circuits.

APA, Harvard, Vancouver, ISO, and other styles

31

Zhang, Zhenwei, Yizhe Hu, Lili Lang, and Yemin Dong. "A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse." Electronics 13, no. 8 (April 12, 2024): 1474. http://dx.doi.org/10.3390/electronics13081474.

Full text

Abstract:

A 16-bit 125 MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.18 μm CMOS process is presented in this paper. A sample-and-hold amplifier-less (SHA-less) modified 2.5-bit front-end is adopted, which splits the sampling capacitor in half to eliminate the common-mode voltage buffer. The multiplying-digital-to-analog converter (MDAC) in the first pipeline stage is modified by reusing the sampling capacitor in a foreground digital calibration for improving the ADC linearity. This design can circumvent a dedicated reference buffer to generate the calibration voltages at all comparator thresholds. By calibrating the ADC in the digital domain, the integral non-linearity (INL) is improved from −9.2/10 LSB to −3/2.2 LSB, and the spurious-free dynamic range (SFDR) is optimized by over 8dB. The ADC consumes 154mW (reference buffer and clock included) from a 1.8 V supply.

APA, Harvard, Vancouver, ISO, and other styles

32

Al-Naamani, Yahya Mohammed Ali, K. Lokesh Krishna, and A. M. Guna Sekhar. "A Successive Approximation Register Analog to Digital Converter for Low Power Applications." Journal of Computational and Theoretical Nanoscience 17, no. 1 (January 1, 2020): 451–55. http://dx.doi.org/10.1166/jctn.2020.8689.

Full text

Abstract:

In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less die area poses a stringent requirement in designing and fabricating an ultra-low power ADCs. Among the diverse converter architectures existing, Successive Approximation Register (SAR) type converter architecture has shown better capabilities in terms of ultra-low power operation, medium resolution, less form factor and less silicon area. In this described paper a novel power effective, better resolution SAR type ADC to be used for biomedical related applications. The proposed work consists of capacitive type Digital to Analog Converter (DAC) based on charge distribution, a CMOS comparator, and SAR logic implemented using D-flip-flops. The different blocks of SAR architecture are simulated using EDA tools in CMOS 180 nm N-well process operated at VDD = 1.5 V voltage (VDD). The circuit is measured under various input frequencies with a sampling speed of 50 MHz and it consumes 22.6 μW. The proposed ADC technology shows SNDR of 48.6 dB and occupies a circuit area of 0.11 mm2 and the measured INL and DNL is calculated to be fewer than 0.54 LSB and 0.45 LSB respectively.

APA, Harvard, Vancouver, ISO, and other styles

33

Yadav, Nandakishor, Youngbae Kim, Mahmoud Alashi, and Kyuwon Ken Choi. "Sensitive, Linear, Robust Current-To-Time Converter Circuit for Vehicle Automation Application." Electronics 9, no. 3 (March 16, 2020): 490. http://dx.doi.org/10.3390/electronics9030490.

Full text

Abstract:

Voltage-to-time and current-to-time converters have been used in many recent works as a voltage-to-digital converter for artificial intelligence applications. In general, most of the previous designs use the current-starved technique or a capacitor-based delay unit, which is non-linear, expensive, and requires a large area. In this paper, we propose a highly linear current-to-digital converter. An optimization method is also proposed to generate the optimal converter design containing the smallest number of PMOS and sensitive circuits such as a differential amplifier. This enabled our design to be more stable and robust toward negative bias temperature instability (NBTI) and process variation. The proposed converter circuit implements the point-wise conversion from current-to-time, and it can be used directly for a variety of applications, such as analog-to-digital converters (ADC), used in built-in computational random access (C-RAM) memory. The conversion gain of the proposed circuit is 3.86 ms/A, which is 52 times greater than the conversion gains of state-of-the-art designs. Further, various time-to-digital converter (TDC) circuits are reviewed for the proposed current-to-time converter, and we recommend one circuit for a complete ADC design.

APA, Harvard, Vancouver, ISO, and other styles

34

Watson, Jeff, and Maithil Pachchigar. "A Low Power, Precision SAR Analog to Digital Converter for High Temperature Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000053–57. http://dx.doi.org/10.4071/hitec-ta26.

Full text

Abstract:

A growing number of industries are calling for low power electronics that operate reliably at temperatures of 175°C and higher. Many of these applications require a precision data acquisition signal chain in order to digitize analog data so that it can be collected and processed. Designing circuits that meet these needs can be very challenging, requiring a data converter that can deliver high performance and reliability in these harsh environments. There are currently a very limited number of integrated circuits commercially available that are specified for operation at these temperatures, and no low power precision data converters with sample rates greater than 100kSPS. This paper presents a new 210°C rated precision analog to digital converter capable of sample rates up to 600 kSPS with 16 bit resolution while maintaining low power consumption and packaged in a small form factor. We will explore the converter architecture of this ADC, present initial test results, and show how high reliability is achieved through qualification and advanced packaging techniques.

APA, Harvard, Vancouver, ISO, and other styles

35

Kang, Min-seong, and Kwang S. Yoon. "Design of A Reconfigurable Low Power High Resolution Hybrid Analog to Digital Converter." Journal of the Institute of Electronics and Information Engineers 59, no. 9 (September 30, 2022): 23–29. http://dx.doi.org/10.5573/ieie.2022.59.9.23.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Chakir, Mostafa, Hicham Akhamal, and Hassan Qjidaa. "A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor." Scientific World Journal 2017 (2017): 1–15. http://dx.doi.org/10.1155/2017/8418042.

Full text

Abstract:

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

APA, Harvard, Vancouver, ISO, and other styles

37

Pham, Duy Phong, Thanh Pham Xuan, Nguyen Thi Viet Ha, and Manh Kha Hoang. "Designing and simulation a 15-bit successive approximation register analog-to-digital converter." Journal of Military Science and Technology 87 (May 25, 2023): 1–8. http://dx.doi.org/10.54939/1859-1043.j.mst.87.2023.1-8.

Full text

Abstract:

Analog-to-digital converters (ADC) are widely employed to monitor long-term signal characteristics in wireless sensor networks and healthcare electronic devices. It is critical in these applications to use an energy-efficient ADC to extend battery life. This paper presents a 15-bit successive-approximation register (SAR) ADC for using in biomedical processing systems. The segmentation degrees (the amount of bits in each divided capacitive sub-array) are optimized to minimize switching power and area based on linearity and matching requirements. The proposed SAR ADC is simulated by using Simulink of Matlab. The simulated results show that the ADC achieves 14.78-bit of effective numbers of bits (ENoB), 111.5 dB of the spurious-free dynamic range (SFDR) with 90.74 dB of signal-to-noise ratio (SNR) at a sampling rate of 10MHz.

APA, Harvard, Vancouver, ISO, and other styles

38

Chen, Dongdong, Xinhui Cui, Qidong Zhang, Di Li, Wenyang Cheng, Chunlong Fei, and Yintang Yang. "A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System." Micromachines 13, no. 1 (January 11, 2022): 114. http://dx.doi.org/10.3390/mi13010114.

Full text

Abstract:

As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. The performance of integrated circuits (ICs) in portable UIS obviously affects the effectiveness and quality of ultrasonic imaging. In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital signal processing (DSP) or microcontroller unit (MCU). The accuracy and speed of the ADC determine the precision and efficiency of UIS. Therefore, it is necessary to systematically review and summarize the characteristics of different types of ADCs for UIS, which can provide valuable guidance to design and fabricate high-performance ADC for miniaturized high resolution UIS. In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced. In addition, comparisons and discussions of different types of ADCs are presented. Finally, this paper is summarized, and presents the challenges and prospects of ADC ICs for miniaturized high resolution UIS.

APA, Harvard, Vancouver, ISO, and other styles

39

Shukla, Mohit. "A 13.42ps Resolution, Low-Power Time-to-Digital Converter and 0.519fJ Energy-Efficient Novel Voltage-to-Time Converter for High-Speed Time-Based ADC Application." Journal of University of Shanghai for Science and Technology 24, no. 02 (February 19, 2022): 1020–30. http://dx.doi.org/10.51201/jusst/21/10878.

Full text

Abstract:

Voltage domain ADC architectures require high gain and high bandwidth opamps to amplify the signal for successive stages. The opamp design gets a bit challenging due to noise, small gain and lower overdrive voltage. Due to these limitations, the inclination shifted towards high-speed converters which don’t require opamps. Time based Analog to Digital Converters (TBADC) is one such category of circuits. TBADCs are constituted from VTC followed by TDC with an encoder in the end. This work is concerned around the design of a high-resolution time to digital converter (TDC) and proposing a novel high-speed, low power consuming voltage to time converter (VTC) circuit. Both the circuits were implemented in Cadence Virtuoso EDA tool version 6.1.7 and Spectre was employed for running the simulations. TDC circuits had resolution of 13.425 ps and consume power of 1.873 μW. Process corner analysis and Monte Carlo analysis were performed on VTC design to determine worst possible deviations in performance. The proposed VTC exhibited delay of 23.79 ps with power consumption of 21.83 μW at 1 Volt. The presented TDC and VTC circuits can be used to design high-speed time-based Analog to Digital Converters.

APA, Harvard, Vancouver, ISO, and other styles

40

Wael Saad Ahmed, Zahraa mehssen agheeb, and Walead kaled sleaman. "Calibration of Cyclic-Pipelined ADCs Using CMOS for Area-Efficiency." Global Journal of Engineering and Technology Advances 15, no. 3 (June 30, 2023): 008–16. http://dx.doi.org/10.30574/gjeta.2023.15.3.0104.

Full text

Abstract:

One of the principal obstacles in the development of pipeline analog-to-digital converters (ADCs) is the imprecision associated with residue amplification. Operational amplifiers (Op-Amps) that possess high gain and speed are recognized for their excessive power consumption, making them unsuitable for employment in proficient analog-to-digital converters (ADCs). The study presents a new method for foreground calibration that addresses amplification differences in cyclic-pipelined ADCs, reducing the need for internal amplifier DC gain. The calibration technique was applied to a cyclic-pipelined ADC with a sampling rate of 2 MS/s and 16-bit resolution. The design of this ADC was optimized for area efficiency, and its fabrication utilized 180 nm CMOS technology. The analog-to-digital converter (ADC) used a 5-bit resolution sub-ADC performing 4 cycles to reduce potential errors. Each cycle contained one bit of redundancy. A fixed-point iterative algorithm was used to find the exact gain for each amplifier. Simulation data shows a SINAD of 100. 6 dB, despite a 57 dB DC gain amplifier. The ADC's active area is 1. 8 mm2 at 30 consumption. 43 mW.

APA, Harvard, Vancouver, ISO, and other styles

41

Saifutdinov, A. I., and S. S. Sysoev. "Development of a Probe System for Measuring the Plasma Parameters and the High-Energy Part of the Electron-Energy Distribution Function." Instruments and Experimental Techniques 65, no. 1 (February 2022): 75–79. http://dx.doi.org/10.1134/s0020441222010195.

Full text

Abstract:

Abstract— A probe system has been developed on the basis of an external ADC/DAC module (ADC is the analog-to-digital converter and DAC is the digital-to-analog converter). Using this system, it is possible to determine all the main plasma parameters of continuous and pulsed gas discharges. A program for the Windows operating system has been developed in C++ to control the probe system. The probe system can be used for diagnostics of plasma devices and can be included in modern microplasma analyzers of gas mixtures.

APA, Harvard, Vancouver, ISO, and other styles

42

Elgreatly, Ahmed, Ahmed Dessouki, Hassan Mostafa, Rania Abdalla, and El-sayed El-Rabaie. "A Novel Highly Linear Voltage-To-Time Converter (VTC) Circuit for Time-Based Analog-To-Digital Converters (ADC) Using Body Biasing." Electronics 9, no. 12 (December 1, 2020): 2033. http://dx.doi.org/10.3390/electronics9122033.

Full text

Abstract:

Time-based analog-to-digital converter is considered a crucial part in the design of software-defined radio receivers for its higher performance than other analog-to-digital converters in terms of operation speed, input dynamic range and power consumption. In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These novel converters exhibit better linearity, which is analytically proven in this paper. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800 mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology. These novel designs consist of only a single inverter stage, which results in reducing the layout area and the power consumption. The overall power consumption is 18 μW for the first proposed circuit and 15 μW for the second proposed circuit. The novel converter circuits have a resolution of 5 bits and operate at a maximum clock frequency of 500 MHz.

APA, Harvard, Vancouver, ISO, and other styles

43

Sokolov, Kamenskij, Novikov, and Ivetić. "How to Increase the Analog-to-Digital Converter Speed in Optoelectronic Systems of the Seed Quality Rapid Analyzer." Inventions 4, no. 4 (October 6, 2019): 61. http://dx.doi.org/10.3390/inventions4040061.

Full text

Abstract:

This invention is relevant when working as part of optoelectronic systems, including non-destructive quality control of forest seeds. The possibility of synthesis of the ultrafast optical analog-to-digital converter (ADC) providing conversion of analog information to digital in the sub-GHz range is considered. The functional scheme of the optical ADC, containing technologically well-developed optical elements is given; the principle of operation is described in detail. The possibility of increasing the speed of the ADC to make it potentially possible for optical data processing schemes is shown.

APA, Harvard, Vancouver, ISO, and other styles

44

Vančura, P., J. Gečnuk, J. Jakovenko, Z. Janoška, J. Jirsa, V. Kafka, O. Korchak, et al. "A low power asynchronous column-parallel 10-bit analog to digital converter with a high input impedance." Journal of Instrumentation 17, no. 05 (May 1, 2022): T05016. http://dx.doi.org/10.1088/1748-0221/17/05/t05016.

Full text

Abstract:

Abstract This paper proposes a low power 10-bit asynchronous fully-differential column analog to digital converter (ADC) with successive approximation (SAR) and charge redistribution in a 180 nm SoI technology. The ADC is designed for use in Spacepix-2 monolithic active pixel sensor. A novel folded architecture of internal capacitive digital to analog converter (CDAC) is proposed. The total capacitance of CDAC is 512 fF, with a single unit capacitor capacitance only 0.5 fF and a size of 2.5 × 1.4 μm2. The total input capacitance of the proposed column ADC is only 220 fF. Two columns of a pixel matrix share a single ADC to double layout width. The layout area is 120 × 923 μm2. The sample rate is 4 MSps with power consumption of 225 μW from 1.8 V power supply.

APA, Harvard, Vancouver, ISO, and other styles

45

Wang, Jiaqi. "A 10-bit 160 MS/s Asynchronous SAR ADC design." Journal of Physics: Conference Series 2645, no. 1 (November 1, 2023): 012001. http://dx.doi.org/10.1088/1742-6596/2645/1/012001.

Full text

Abstract:

Abstract This study describes a 10-bit 160 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) design in a 40 nm CMOS technical process. The SAR ADC is provided with an improved capacitive digital-to-analog converter (CDAC), and the capacitor array is featured by six split high-bit capacitors and a combination of splitting and monotonic switching schemes. This structure and switching scheme can both save power and improve speed while introducing negligible common-mode voltage change. An improved double-tail comparator and TSPC D flip-flops are implemented to further enhance the speed. Simulation results show that the ADC achieves SFDR 72.17 dB, SNDR 61.37 dB, and ENOB 9.90 bits at Nyquist input frequency. The power consumption of the ADC under a 1.2 V power supply is 2.808 mW, achieving 18.4 fJ/conv FoM.

APA, Harvard, Vancouver, ISO, and other styles

46

Wang, Jia Rong, Xiao Dong Xia, Zong Da Zhang, and Han Yang. "Using Dual-Channel D/A Converters Design Successive Approximation A/D Converter." Applied Mechanics and Materials 719-720 (January 2015): 611–14. http://dx.doi.org/10.4028/www.scientific.net/amm.719-720.611.

Full text

Abstract:

The successive approximation analog-to-digital converter (ADC) has been widely used in electronic devices due to the corresponding characteristics which are low cost, low power consumption, high accuracy and so on. This paper expounds a design of successive approximation A / D converter to show how to use TCL5615 which is a dual-channel serial 10-bit D/A converter (DAC) to make the conversion accuracy to reach 14-bit.

APA, Harvard, Vancouver, ISO, and other styles

47

Zhang, Mengdi, Ye Zhao, Yong Chen, Paolo Crovetti, Yanji Wang, Xinshun Ning, and Shushan Qiao. "A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components." Sensors 22, no. 15 (August 5, 2022): 5852. http://dx.doi.org/10.3390/s22155852.

Full text

Abstract:

A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input—driven by the analog input and by the reference slope generated by an FPGA output buffer—is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between −0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from −0.72 to 0.78 LSB.

APA, Harvard, Vancouver, ISO, and other styles

48

-, Elgamar Syam. "Analisa dan Implementasi Transformasi Analog to Digital Converter (ADC) untuk Mengkonversi Suara Kebentuk Teks." SATIN - Sains dan Teknologi Informasi 3, no. 2 (July 31, 2018): 71–77. http://dx.doi.org/10.33372/stn.v3i2.369.

Full text

Abstract:

Teknologi telah banyak membawa perubahan pada kehidupan manusia, sehingga memberikan dampak positif dan negatif. Menurut hasil beberapa penelitian menunjukkan bahwa daya serap manusia terhadap sebuah informasi adanya ketidaksamaan tingkatan, salah satu yang menyebabkan demikian adalah pilihan jenis media yang digunakan. Jenis media komunikasi audio visual ternyata yang paling tinggi, audio, dan selanjutnya berupa teks. Transformasi Analog to Digital Converter (ADC) merupakan piranti yang berfungsi merubah sinyal analog menjadi sinyal digital. Dalam sub sistem ADC,untuk mendapatkan frekuensi yang di inginkan, melalui tiga tahapan yaitu sampling, quantizing, dan pengkodean, kemudian membandingkan frekuensi ini dengan frekuensi sinyal digital suara yang masuk dengan database kata-kata yang sudah di inputkan sebelumnya sehingga menghasilkan sebuah output berupa text-on-screen

APA, Harvard, Vancouver, ISO, and other styles

49

Gujjula, Ramana Reddy, Chitra Perumal, Prakash Kodali, and Bodapati Venkata Rajanna. "Design and analysis of dual-mode numerically controlled oscillators based controlled oscillator frequency modulation." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 5 (October 1, 2022): 4935. http://dx.doi.org/10.11591/ijece.v12i5.pp4935-4943.

Full text

Abstract:

In this paper, the design and analysis of dual-mode numerically controlled oscillators (NCO) based controlled oscillator frequency Modulation is implemented. Initially, input is given to the analog to digital (ADC) converter. This will change the input from analog to digital converter. After that, the pulse skipping mode (PSM) logic and proportional integral (PI) are applied to the converted data. After applying PSM logic, data is directly transferred to the connection block. The proportional and integral block will transfer the data will be decoded using the decoder. After decoding the values, it is saved using a modulo accumulator. After that, it is converted from one hot residue (OHR) to binary converter. The converted data is saved in the register. Now both data will pass through the gate driver circuit and output will be obtained finally. From simulation results, it can observe that the usage of metal oxide semiconductor field effect transistors (MOSFETs) and total nodes are very less in dual-mode NCO-based controlled oscillator frequency modulation.

APA, Harvard, Vancouver, ISO, and other styles

50

KOCAK, TASKIN, GEORGE R. HARRIS, and RONALD F. DEMARA. "SELF-TIMED ARCHITECTURE FOR MASKED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION." Journal of Circuits, Systems and Computers 16, no. 01 (February 2007): 1–14. http://dx.doi.org/10.1142/s0218126607003551.

Full text

Abstract:

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Analog-to-digital converter (ADC)'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles