Relevant bibliographies by topics / Analog-to-digital converters (ADCs)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Analog-to-digital converters (ADCs)'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 September 2023

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Journal articles on the topic "Analog-to-digital converters (ADCs)"

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Ulyashin, Aleksander, and Aleksander Velichko. "Comparative analysis of methods for constructing analog-to-digital converters." Transaction of Scientific Papers of the Novosibirsk State Technical University, no. 4 (December 18, 2020): 38–49. http://dx.doi.org/10.17212/2307-6879-2020-4-38-49.

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This paper is devoted to the comparative analysis of modern integrated analog-to-digital converters (ADCs). At the moment, a number of foreign companies, such as Analog Devices, Texas Instruments and Microchip, produce ADCs in integrated design. Each manufacturer uses its own method of implementing the device. The main task of such devices is to convert voltage to binary code. ADCs are used wherever it is necessary to receive an analog signal and process it in digital form. Examples include applications such as communications and telecommunications, various radio systems, and measurement technology. Very important characteristics of such equipment are dynamic range, ease of implementation and speed. The means of analog-to-digital conversion are constantly being improved, which leads to an increase in the speed of the converters and the frequency band of the converted signals, an increase in the dynamic range, sensitivity and accuracy of the ADC. Significant interest in high-speed ADCs with a large dynamic range is explained by the fact that in the vast majority of telecommunications and radio engineering systems, direct signal conversion schemes without intermediate frequency conversion are increasingly used. Broadband applications have also been developed. The main requirement in these applications is the high sensitivity and wide dynamic range of the transducer for simultaneous detection of strong and weak signals. In this paper, a comparative analysis of the main types of analog-to-digital converters offered on the market is carried out in order to identify the most optimal construction method for using it in modern equipment.
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Wael Saad Ahmed, Zahraa mehssen agheeb, and Walead kaled sleaman. "Calibration of Cyclic-Pipelined ADCs Using CMOS for Area-Efficiency." Global Journal of Engineering and Technology Advances 15, no. 3 (2023): 008–16. http://dx.doi.org/10.30574/gjeta.2023.15.3.0104.

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One of the principal obstacles in the development of pipeline analog-to-digital converters (ADCs) is the imprecision associated with residue amplification. Operational amplifiers (Op-Amps) that possess high gain and speed are recognized for their excessive power consumption, making them unsuitable for employment in proficient analog-to-digital converters (ADCs). The study presents a new method for foreground calibration that addresses amplification differences in cyclic-pipelined ADCs, reducing the need for internal amplifier DC gain. The calibration technique was applied to a cyclic-pipelined ADC with a sampling rate of 2 MS/s and 16-bit resolution. The design of this ADC was optimized for area efficiency, and its fabrication utilized 180 nm CMOS technology. The analog-to-digital converter (ADC) used a 5-bit resolution sub-ADC performing 4 cycles to reduce potential errors. Each cycle contained one bit of redundancy. A fixed-point iterative algorithm was used to find the exact gain for each amplifier. Simulation data shows a SINAD of 100. 6 dB, despite a 57 dB DC gain amplifier. The ADC's active area is 1. 8 mm2 at 30 consumption. 43 mW.
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Kelly, Brandon M., Alexander T. DiLello, and David W. Graham. "Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion." Journal of Low Power Electronics and Applications 9, no. 3 (2019): 25. http://dx.doi.org/10.3390/jlpea9030025.

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Wearable medical devices, wireless sensor networks, and other energy-constrained sensing devices are often concerned with finding specific data within more-complex signals while maintaining low power consumption. Traditional analog-to-digital converters (ADCs) can capture the sensor information at a high resolution to enable a subsequent digital system to process for the desired data. However, traditional ADCs can be inefficient for applications that only require specific points of data. This work offers an alternative path to lower the energy expenditure in the quantization stage—asynchronous content-dependent sampling. This asynchronous sampling scheme is achieved by pairing a flexible analog front-end with an asynchronous successive-approximation ADC and a time-to-digital converter. The versatility and reprogrammability of this system allows a multitude of event-driven, asynchronous, or even purely data-driven quantization methods to be implemented for a variety of different applications. The system, fabricated in standard 0.5 μ m and 0.35 μ m processes, is demonstrated along with example applications with voice, EMG, and ECG signals.
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Pun-García, Ernesto, and Marisa López-Vallejo. "A Survey of Analog-to-Digital Converters for Operation under Radiation Environments." Electronics 9, no. 10 (2020): 1694. http://dx.doi.org/10.3390/electronics9101694.

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In this work, we analyze in depth multiple characteristic data of a representative population of radenv-ADCs (analog-to-digital converters able to operate under radiation). Selected ADCs behave without latch-up below 50 MeV·cm2/mg and are able to bear doses of ionizing radiation above 50 krad(Si). An exhaustive search of ADCs with radiation characterization data has been carried out throughout the literature. The obtained collection is analyzed and compared against the state of the art of scientific ADCs, which reached years ago the electrical performance that radenv-ADCs provide nowadays. In fact, for a given Nyquist sampling rate, radenv-ADCs require significantly more power to achieve lower effective resolution. The extracted performance patterns and conclusions from our study aim to serve as reference for new developments towards more efficient implementations. As tools for this purpose, we have conceived FOMTID and FOMSET, two new figures of merit to compare radenv-ADCs that consider electrical and radiation performance.
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Dalmia, Hemlata, and Sanjeet K. Sinha. "Analog to Digital Converters (ADC): A Literature Review." E3S Web of Conferences 184 (2020): 01025. http://dx.doi.org/10.1051/e3sconf/202018401025.

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The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.
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Saeidiyan, Zeinab, Mohammad Hosein Fatehi, Mehdi Taghizadeh, and Mohammad Mehdi Ghanbarian. "Enhancing the Accuracy and Speed of Sampling in Image Sensors by Designing Analog to Digital Converter with Power Decrease Approach." Journal of Sensors 2022 (January 24, 2022): 1–16. http://dx.doi.org/10.1155/2022/5075823.

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Analog to digital converters (ADCs) enable the processing of real-world analog signals in the digital realm. These converters are widely used in sensor systems, medical components, multimedia systems, image sensors, and wireless sensor nodes. Today, in portable devices that are powered by batteries, low power consumption and small area are a major and important need. Therefore, methods that can reduce power consumption and area have a variety of applications and are of great importance. Power consumption is one of the most important features of an integrated analog to digital converter. In this paper, a new design of low-power and fast analog to digital converter is presented. This design is used for specific applications for image processing. The suggested approach for rereading the image for limited number of pixels was designed and simulated, showing a considerable power decrease compared to the suggested state that depends on the pixel values.
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Bialek, J., A. Wickmann, F. Ohnhaeuser, G. Fischer, R. Weigel, and T. Ussmueller. "Implementation of a digital trim scheme for SAR ADCs." Advances in Radio Science 11 (July 4, 2013): 227–30. http://dx.doi.org/10.5194/ars-11-227-2013.

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Abstract. Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.
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KARMAKAR, SUPRIYA, JOHN A. CHANDY, and FAQUIR C. JAIN. "APPLICATION OF 25 NM QUANTUM DOT GATE FETs TO THE DESIGN OF ADC AND DAC CIRCUITS." International Journal of High Speed Electronics and Systems 20, no. 03 (2011): 653–68. http://dx.doi.org/10.1142/s0129156411006945.

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This paper describes design of analog-to-digital converters (ADCs) and digital-to-analog onverters (DACs) using field-effect transistors that exhibit three states in their transfer characteristics. An intermediate state " i " has been observed in the transfer characteristics (drain current-gate voltage) of FETs when two layers of cladded quantum dots (e.g. SiO x - Si and GeO x - Ge ) are introduced in the gate region above the tunnel insulator between the source and drain regions. Three states in such a transistor, defined as quantum dot gate field-effect transistor (QDG-FET) include two stable states (ON and OFF) and a low-current saturation state " i " in its transfer characteristics. QDG-FETs are quite different in construction than nanodot based nonvolatile memories, reported in the literature, where the quantum dots are sandwiched between a tunnel gate insulator and a relatively thick control gate dielectric. In this paper we present analog-to-digital converters (ADCs) using comparators based on QDG-FETs. A comparator is designed with fewer three-state QDG-FETs. Designs of 3-bit ADC, using 25 nm QDG-FETs, are simulated showing a signal-to-noise ratio (SNR) of ~18. In addition, the R-2R ladder problem, encountered in conventional analog-to digital converters (ADCs), is absent in QDG-FET based architecture.
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Bojja Venkatakrishnan, Satheesh, Elias A. Alwan, and John L. Volakis. "Challenges in Clock Synchronization for On-Site Coding Digital Beamformer." International Journal of Reconfigurable Computing 2017 (2017): 1–8. http://dx.doi.org/10.1155/2017/7802735.

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Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.
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BARRA, SAMIR, ABDELGHANI DENDOUGA, SOUHIL KOUDA, and NOUR-EDDINE BOUGUECHAL. "CONTRIBUTION TO THE ANALYSIS AND MODELING OF THE NON-IDEAL EFFECTS OF PIPELINED ADCs USING MATLAB." Journal of Circuits, Systems and Computers 22, no. 02 (2013): 1250085. http://dx.doi.org/10.1142/s0218126612500855.

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The present work analyses the non-ideal effects of pipelined analog-to-digital converters (ADCs), also sometimes referred to as pipeline ADCs, including the non-ideal effects in operational amplifiers (op-amps or OAs), switches and sampling circuits. We study these nonlinear effects in pipelined ADCs built using CMOS technology and switched-capacitor (SC) techniques. The proposed improved model of a pipelined ADC includes most of the non-idealities which affect its performance. This model, simulated using MATLAB, can determine the basic blocks specifications that allow the designer to meet given data converter requirements.
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Dissertations / Theses on the topic "Analog-to-digital converters (ADCs)"

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Tang, Yi. "Digitally-assisted sigma-delta ADCs for scaled CMOS technology /." Thesis, Connect to this title online; UW restricted, 2007. http://hdl.handle.net/1773/5958.

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Andersson, Ola. "Modeling and Implementation of Current-Steering Digital-to-Analog Converters." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5062.

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Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.
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Tourabaly, Jamil A. "A jittered-sampling correction technique for ADCs." Connect to thesis, 2008. http://portal.ecu.edu.au/adt-public/adt-ECU2008.0009.html.

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Zhong, Jian Yu. "Design of high-speed power-efficient SAR-type ADCs." Thesis, University of Macau, 2017. http://umaclib3.umac.mo/record=b3691882.

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Brady, Philomena C. "Offset correction in flash ADCs using floating-gate circuits." Thesis, Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/14832.

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Nordick, Brent C. "Dynamic Element Matching Techniques For Delta-Sigma ADCs With Large Internal Quantizers." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd466.pdf.

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Jalali, Farahani Bahar. "Adaptive digital calibration techniques for high speed, high resolution SIGMA DELTA ADCs for broadband wireless applications." Columbus, Ohio : Ohio State University, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1133192371.

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Kerzerho, Vincent. ""Analogue Network of Converters": a DfT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SoC." Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2008. http://tel.archives-ouvertes.fr/tel-00364546.

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Une nouvelle méthode de test pour les convertisseurs ADC et DAC embarqués dans un système complexe a été développée en prenant en compte les nouvelles contraintes affectant le test. Ces contraintes, dues aux tendances de design de systèmes, sont un nombre réduit de point d'accès aux entrées/sorties des blocs analogiques du système et une augmentation galopante du nombre et des performances des convertisseurs intégrés. La méthode proposée consiste à connecter les convertisseurs DAC et ADC dans le domaine analogique pour n'avoir besoin que d'instruments de test numériques pour générer et capturer les signaux de test. Un algorithme de traitement du signal a été développé pour discriminer les erreurs des DACs et ADCs. Cet algorithme a été validé par simulation et par expérimentation sur des produits commercialisés par NXP. La dernière partie de la thèse a consisté à développer de nouvelles applications pour l'algorithme.
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Ohlsson, Henrik. "Studies on Design and Implementation of Low-Complexity Digital Filters." Doctoral thesis, Linköping : Dept. of Electrical Engineering, Univ, 2005. http://www.ep.liu.se/diss/science_technology/09/49/index.html.

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Wei, He Gong. "High speed power/area optimized multi-bit/cycle SAR ADCs." Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2489844.

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Books on the topic "Analog-to-digital converters (ADCs)"

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Ruiz-Amaya, Jesus. Device-level modeling and synthesis of high-performance pipeline ADCs. Springer, 2011.

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Ahmed, Imran. Pipelined ADC design and enhancement techniques. Springer, 2010.

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Murmann, Boris. Digitally assisted pipeline ADCs: Theory and implementation. Kluwer Academic Publishers, 2004.

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Cao, Zhiheng. Low-Power High-Speed ADCs for Nanometer CMOS Integration. Springer Science + Business Media B.V, 2008.

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C, Vital João, and Franca José, eds. Systematic design for optimisation of pipelined ADCs. Kluwer Academic Publishers, 2001.

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Motorola. Modular microcontroller family ADC analog-to-digital converter reference manual. Motorola, 1993.

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1938-, Huijsing Johan H., ed. High-resolution IF-to-baseband [Sigma-Delta] ADC for car radios. Springer, 2008.

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1938-, Huijsing Johan H., Steyaert Michiel 1959-, and Roermund, Arthur H. M. van., eds. Analog circuit design: Sensor and actuator interface electronics, integrated high-voltage electronics and power management, low-power and high-resolution ADC's. Kluwer Academic, 2004.

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Delgado-Restituto, Manuel, Ángel Rodríguez-Vázquez, and Jesús Ruiz-Amaya. Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs. Springer, 2014.

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Rabuske, Taimur, and Jorge Fernandes. Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications. Springer, 2018.

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Book chapters on the topic "Analog-to-digital converters (ADCs)"

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Louwsma, Simon, Ed van Tuijl, and Bram Nauta. "Sub-ADC Architectures for Time-interleaved ADCs." In Time-interleaved Analog-to-Digital Converters. Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-90-481-9716-3_3.

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Ohnhäuser, Frank. "ADCs Based on Successive Approximation." In Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Converters. Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-47020-6_2.

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Ohnhäuser, Frank. "Continuous-Time Delta-Sigma ADCs." In Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Converters. Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-47020-6_5.

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Ohnhäuser, Frank. "External Driver Circuitry and Test of ADCs." In Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Converters. Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-47020-6_6.

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Bajdechi, Ovidiu, and Johan H. Huijsing. "Architecture-Level Analysis of Sigma-Delta ADCs." In Systematic Design of Sigma-Delta Analog-to-Digital Converters. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4020-7946-7_2.

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Bajdechi, Ovidiu, and Johan H. Huijsing. "Computer Aided Design of Sigma-Delta ADCs." In Systematic Design of Sigma-Delta Analog-to-Digital Converters. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4020-7946-7_5.

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Xing, Xinpeng, Peng Zhu, and Georges Gielen. "VCO-Based ADCs." In Design of Power-Efficient Highly Digital Analog-to-Digital Converters for Next-Generation Wireless Communication Systems. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-66565-8_4.

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Xing, Xinpeng, Peng Zhu, and Georges Gielen. "CT DSM ADCs with VCO-Based Quantization." In Design of Power-Efficient Highly Digital Analog-to-Digital Converters for Next-Generation Wireless Communication Systems. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-66565-8_5.

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Gadre, Dhananjay V., and Sarthak Gupta. "Analog to Digital Converter (ADC)." In Getting Started with Tiva ARM Cortex M4 Microcontrollers. Springer India, 2017. http://dx.doi.org/10.1007/978-81-322-3766-2_14.

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Asadi, Farzin. "Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC)." In Essentials of Arduino™ Boards Programming. Apress, 2023. http://dx.doi.org/10.1007/978-1-4842-9600-4_3.

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Conference papers on the topic "Analog-to-digital converters (ADCs)"

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Wang, Michael R., and Tomasz Jannson. "Electrooptic multiwavelength analog-to-digital converters and modulators for optical computing." In OSA Annual Meeting. Optica Publishing Group, 1991. http://dx.doi.org/10.1364/oam.1991.wd3.

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An entirely new class of electrooptic analog-to- digital converters (ADCs) and modulators for optical computing and optical signal processing uses is presented. This new device, based on wavelength division multiplexing and utilizing an integrated high speed tunable single-mode channel waveguide Fabry-Perot etalon, can function as a binary or a multivalued ADC or wavelength modulator. The new wavelength modulation is parallel to existing modulation concepts including phase, intensity, polarization or mode conversion modulation, and frequency to space domain modulation(such as in acoustooptic spectrum analyzers.) The advantages of this A/D conversion/modulation concept include external A/D conversion/modulation and multivalued logical capability with self identification, eliminating the need for a sampling optical pulse and electronic comparators needed by other ADCs. Long distance digital optical signal transmission capability, electronically reconfigurable logical weights through initial bias, and high speed operation are also unique features. Additional advantages include its simple structure, high SNR, low BER, high dynamic range, excellent power budge, and thermal stability. The new wavelength modulation concept makes multiwavelength coding possible for use in highly secure optical communication for military and commercial purposes.
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Mostafa, Hassan, and Yehea I. Ismail. "Highly-linear voltage-to-time converter (VTC) circuit for time-based analog-to-digital converters (T-ADCs)." In 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS). IEEE, 2013. http://dx.doi.org/10.1109/icecs.2013.6815376.

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Prusten, Mark J., and Arthur F. Gmitro. "An Optical Flash Analog to Digital Converter." In Optical Computing. Optica Publishing Group, 1995. http://dx.doi.org/10.1364/optcomp.1995.otue3.

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Fast analog-to-digital (A/D) converters are important in a number of applications. Several systems have been proposed for fast A/D converters using optical technology1-4. The most common types of converters are the successive approximation and Flash converters. In a Flash converter there is a separate comparator for each possible output bit code. Each comparator is biased with a reference level that is a specific increment of the full scale value. Since comparators in a Flash converter operate in parallel, this architecture is intrinsically fast. However, as the accuracy requirements increase, the number of comparators increases as 2N where N is the number of bits. In the case of an 8 bit Flash ADC, there are 256 comparators. The 256 comparator output signals are routed to a decoder circuit that produces and 8 bit digital word. The schematic for a Flash converter is shown in Fig. 1. The focus of this paper is on a new implementation of an 8 bit Flash converter utilizing optical technologies.
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Suresh, A., S. Shyama, Sangeeta Srivastava, and Nihar Ranjan. "Multichannel ADC IP Core on Xilinx SoC FPGA." In 10th International Conference on Natural Language Processing (NLP 2021). Academy and Industry Research Collaboration Center (AIRCC), 2021. http://dx.doi.org/10.5121/csit.2021.112326.

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Sensing of analogue signals such as voltage, temperature, pressure, current etc. is required to acquire the real time analog signals in the form digital streams. Most of the static analog signals are converted into voltage using sensors, transducers etc. and then measured using ADCs. The digitized samples from ADC are collected either through serial or parallel interface and processed by the programmable chips such as processors, controllers, FPGAs, SOCs etc. In some cases, Multichannel supported ADCs are used to save the layout area when the functionalities are to be realized in a small form factor. In such scenarios, parallel interface for each channel is not a preferred interface considering the more number of interfaces / traces between the components. Hence, Custom, Sink synchronized, Configurable multichannel ADC soft IP core has been developed using VHDL coding to interwork with multichannel supported, time division multiplexed ADCs with serial interface. The developed IP core can be used either as it is with the SPI interface as specified in this paper or with necessary modifications / configurations. The configurations can be the number of channels, sample size, sampling frequency, data transfer clock, type of synchronization – source / sink, control signals and the sequence of the operations performed to configure ADC. The efficiency of implementation is validated using the measurements of throughput, and accuracy for the required range of input with acceptable tolerances. ZYNQ FPGA and LTC2358 ADC are used to evaluate the developed IP core. Integrated Logic Analyser (ILA) which is an integrated verification tool of Vivado is used for Verification.
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5

Larson, Eric D. "Serial pixel analog-to-digital converter (ADC)." In OPTO, edited by Shibin Jiang, Michel J. F. Digonnet, John W. Glesener, and J. Christopher Dries. SPIE, 2010. http://dx.doi.org/10.1117/12.845801.

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Lu, Chi-Chang, and Sheng-Yan Lai. "Capacitive digital-to-analog converter for low-power SAR ADCs." In 2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW). IEEE, 2019. http://dx.doi.org/10.1109/icce-tw46550.2019.8991923.

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7

Khorami, Ata, and Mohammad Sharifkhani. "An ultra low-power digital to analog converter for SAR ADCs." In 2017 29th International Conference on Microelectronics (ICM). IEEE, 2017. http://dx.doi.org/10.1109/icm.2017.8268844.

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8

Malarich, Nathan A., Kevin Cossel, Fabrizio Giorgetta, et al. "Countering nonlinearity in digitization for precise dual-frequency comb spectroscopy." In Optics and Photonics for Sensing the Environment. Optica Publishing Group, 2022. http://dx.doi.org/10.1364/es.2022.em3d.2.

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In order to measure gas concentrations with sub-percent accuracy, we measure, simulate and propose solutions for removing analog to digital converter (ADC) imposed bias on the recorded interferograms in dual comb spectroscopy.
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9

Yip, T. Gary, and Elizabeth B. Nadworny. "A Successive Approximation ADC Simulation Project." In ASME 1992 International Computers in Engineering Conference and Exposition. American Society of Mechanical Engineers, 1992. http://dx.doi.org/10.1115/cie1992-0067.

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Abstract This paper describes a three week long project designed for first year graduate students in mechanical engineering taking a course in Modern Instrumentation. The project entails constructing a successive approximation analog-to-digital converter without a controller, developing a control sequence, and implementing it to produce a digital representation of an analog input voltage. The course is made up of a series of laboratory activities that start with the fundamentals of equipment control and data acquisition, then increase in difficulty by requiring students to develop systems and control sequences on their own. The project teaches computer based data acquisition skills, the fundamental logic of a successive approximation ADC, and provides hands on experience using digital signals to control a system.
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10

Zhang, Shenmao, Xiaoxiao Dai, Zhuo Chen, et al. "Demonstration of real-time receiver for 30-GBaud PAM-6 signal in IM/DD system." In Optical Fiber Communication Conference. Optica Publishing Group, 2023. http://dx.doi.org/10.1364/ofc.2023.w4e.2.

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Using baud-rate timing recovery algorithm and a simple blind synchronization method, we experimentally demonstrate a real-time reception of 30-GBaud 6-level pulse amplitude modulation (PAM-6) signal with a baud-rate analog-to-digital converter (ADC).
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Reports on the topic "Analog-to-digital converters (ADCs)"

1

Mahurin, Eric, and Ray Siford. GaAs Sigma-Delta Modulator Modeling for Analog to Digital Converters (ADCS). Defense Technical Information Center, 1992. http://dx.doi.org/10.21236/ada263419.

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2

Bowers, M., B. Deri, R. Haigh, et al. LDRD final report: photonic analog-to-digital converter (ADC) technology. Office of Scientific and Technical Information (OSTI), 1999. http://dx.doi.org/10.2172/13923.

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