Dissertations / Theses on the topic 'Analog-to-digital converters (ADCs)'

The thesis demonstrates a low-cost, low-bandwidth and low-resolution Analog-to- Digital Converter(ADC) in 0.35 um CMOS Process. A second-order Sigma-Delta modulator is used as the basis of the A/D Converter. A Semi-Uniform quantizer is used with the modulator to take advantage of input distributions that are dominated by smaller-amplitude signals e.g. Audio, Voice and Image-sensor signals. A Single-bit feedback topology is used with a multi-bit quantizer in the modulator. This topology avoids the use of a multi-bit DAC in the feedback loop – hence the system does not need to use digital correction techniques to compensate for a multi-bit DAC nonlinearity.

High-Level Simulations of the second-order Sigma-Delta modulator single-bit feedback topology along with a Semi-Uniform quantizer are performed in Cadence. Results indicate that a 5-bit Semi-Uniform quantizer with a Over-Sampling Ratio of 32, can achieve a resolution of 10 bits, in addition, a semi-uniform quantizer exhibits a 5-6 dB gain in SNR over its uniform counterpart for input amplitudes smaller than –10 dB. Finally, this system is designed in 0.35um CMOS process.

Denna avhandling behandlar analog-digitalomvandling. I synnerhet behandlas postkorrektion av analog-digitalomvandlare (A/D-omvandlare). A/D-omvandlare är i praktiken behäftade med vissa fel som i sin tur ger upphov till distorsion i omvandlarens utsignal. Om felen har ett systematiskt samband med utsignalen kan de avhjälpas genom att korrigera utsignalen i efterhand. Detta verk behandlar den form av postkorrektion som implementeras med hjälp av en tabell ur vilken korrektionsvärden hämtas.

Innan en A/D-omvandlare kan korrigeras måste felen i den mätas upp. Detta görs genom att estimera omvandlarens överföringsfunktion. I detta arbete behandlas speciellt problemet att skatta kvantiseringsintervallens mittpunkter. Det antas härvid att en referenssignal finns tillgänglig som grund för skattningen. En skattare som baseras på sorterade data visas vara bättre än den vanligtvis använda skattaren baserad på sampelmedelvärde.

Nästa huvudbidrag visar hur resultatet efter korrigering av en A/D-omvandlare kan predikteras. Omvandlaren antas här ha en viss differentiell olinjäritet och insignalen antas påverkad av ett slumpmässigt brus. Ett postkorrektionssystem, implementerat med begränsad precision, korrigerar utsignalen från A/D-omvandlaren. Ett utryck härleds som beskriver signal-brusförhållandet efter postkorrektion. Förhållandet visar sig bero på den differentiella olinjäritetens varians, det slumpmässiga brusets varians, omvandlarens upplösning samt precisionen med vilken korrektionstermerna beskrivs.

Till sist behandlas indexering av korrektionstabeller. Valet av metod för att indexera en korrektionstabell påverkar såväl tabellens storlek som förmågan att beskriva och korrigera dynamiska fel. I avhandlingen behandlas i synnerhet tillståndsmodellbaserade metoder, det vill säga metoder där tabellindex bildas som en funktion utav flera på varandra följande sampel. Allmänt gäller att ju fler sampel som används för att bilda ett tabellindex, desto större blir tabellen, samtidigt som förmågan att beskriva dynamiska fel ökar. En indexeringsmetod som endast använder en delmängd av bitarna i varje sampel föreslås här. Vidare så påvisas hur valet av indexeringsbitar kan göras optimalt, och experimentella utvärderingar åskådliggör att tabellstorleken kan reduceras avsevärt utan att fördenskull minska prestanda mer än marginellt.

De teorier och resultat som framförs här har utvärderats med experimentella A/D-omvandlardata eller genom datorsimuleringar.

Analog-to-digital conversion and quantization constitute the topic of this thesis. Post-correction of analog-to-digital converters (ADCs) is considered in particular. ADCs usually exhibit non-ideal behavior in practice. These non-idealities spawn distortions in the converters output. Whenever the errors are systematic, it is possible to mitigate them by mapping the output into a corrected value. The work herein is focused on problems associated with post-correction using look-up tables. All results presented are supported by experiments or simulations.

The first problem considered is characterization of the ADC. This is in fact an estimation problem, where the transfer function of the converter should be determined. This thesis deals with estimation of quantization region midpoints, aided by a reference signal. A novel estimator based on order statistics is proposed, and is shown to have superior performance compared with the sample mean traditionally used.

The second major area deals with predicting the performance of an ADC after post-correction. A converter with static differential nonlinearities and random input noise is considered. A post-correction is applied, but with limited (fixed-point) resolution in the corrected values. An expression for the signal-to-noise and distortion ratio after post-correction is provided. It is shown that the performance is dependent on the variance of the differential nonlinearity, the variance of the random noise, the resolution of the converter and the precision of the correction values.

Finally, the problem of addressing, or indexing, the correction look-up table is dealt with. The indexing method determines both the memory requirements of the table and the ability to describe and correct dynamically dependent error effects. The work here is devoted to state-space--type indexing schemes, which determine the index from a number of consecutive samples. There is a tradeoff between table size and dynamics: more samples used for indexing gives a higher dependence on dynamic, but also a larger table. An indexing scheme that uses only a subset of the bits in each sample is proposed. It is shown how the selection of bits can be optimized, and the exemplary results show that a substantial reduction in memory size is possible with only marginal reduction of performance.

QC 20150422

The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.

Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.

High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.

To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.

The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.

The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.

A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.