Journal articles: 'Analog-to-digital converters (ADCs)'

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Ulyashin, Aleksander, and Aleksander Velichko. "Comparative analysis of methods for constructing analog-to-digital converters." Transaction of Scientific Papers of the Novosibirsk State Technical University, no. 4 (December 18, 2020): 38–49. http://dx.doi.org/10.17212/2307-6879-2020-4-38-49.

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This paper is devoted to the comparative analysis of modern integrated analog-to-digital converters (ADCs). At the moment, a number of foreign companies, such as Analog Devices, Texas Instruments and Microchip, produce ADCs in integrated design. Each manufacturer uses its own method of implementing the device. The main task of such devices is to convert voltage to binary code. ADCs are used wherever it is necessary to receive an analog signal and process it in digital form. Examples include applications such as communications and telecommunications, various radio systems, and measurement technology. Very important characteristics of such equipment are dynamic range, ease of implementation and speed. The means of analog-to-digital conversion are constantly being improved, which leads to an increase in the speed of the converters and the frequency band of the converted signals, an increase in the dynamic range, sensitivity and accuracy of the ADC. Significant interest in high-speed ADCs with a large dynamic range is explained by the fact that in the vast majority of telecommunications and radio engineering systems, direct signal conversion schemes without intermediate frequency conversion are increasingly used. Broadband applications have also been developed. The main requirement in these applications is the high sensitivity and wide dynamic range of the transducer for simultaneous detection of strong and weak signals. In this paper, a comparative analysis of the main types of analog-to-digital converters offered on the market is carried out in order to identify the most optimal construction method for using it in modern equipment.

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Wael Saad Ahmed, Zahraa mehssen agheeb, and Walead kaled sleaman. "Calibration of Cyclic-Pipelined ADCs Using CMOS for Area-Efficiency." Global Journal of Engineering and Technology Advances 15, no. 3 (June 30, 2023): 008–16. http://dx.doi.org/10.30574/gjeta.2023.15.3.0104.

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One of the principal obstacles in the development of pipeline analog-to-digital converters (ADCs) is the imprecision associated with residue amplification. Operational amplifiers (Op-Amps) that possess high gain and speed are recognized for their excessive power consumption, making them unsuitable for employment in proficient analog-to-digital converters (ADCs). The study presents a new method for foreground calibration that addresses amplification differences in cyclic-pipelined ADCs, reducing the need for internal amplifier DC gain. The calibration technique was applied to a cyclic-pipelined ADC with a sampling rate of 2 MS/s and 16-bit resolution. The design of this ADC was optimized for area efficiency, and its fabrication utilized 180 nm CMOS technology. The analog-to-digital converter (ADC) used a 5-bit resolution sub-ADC performing 4 cycles to reduce potential errors. Each cycle contained one bit of redundancy. A fixed-point iterative algorithm was used to find the exact gain for each amplifier. Simulation data shows a SINAD of 100. 6 dB, despite a 57 dB DC gain amplifier. The ADC's active area is 1. 8 mm2 at 30 consumption. 43 mW.

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Kelly, Brandon M., Alexander T. DiLello, and David W. Graham. "Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion." Journal of Low Power Electronics and Applications 9, no. 3 (August 12, 2019): 25. http://dx.doi.org/10.3390/jlpea9030025.

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Wearable medical devices, wireless sensor networks, and other energy-constrained sensing devices are often concerned with finding specific data within more-complex signals while maintaining low power consumption. Traditional analog-to-digital converters (ADCs) can capture the sensor information at a high resolution to enable a subsequent digital system to process for the desired data. However, traditional ADCs can be inefficient for applications that only require specific points of data. This work offers an alternative path to lower the energy expenditure in the quantization stage—asynchronous content-dependent sampling. This asynchronous sampling scheme is achieved by pairing a flexible analog front-end with an asynchronous successive-approximation ADC and a time-to-digital converter. The versatility and reprogrammability of this system allows a multitude of event-driven, asynchronous, or even purely data-driven quantization methods to be implemented for a variety of different applications. The system, fabricated in standard 0.5 μ m and 0.35 μ m processes, is demonstrated along with example applications with voice, EMG, and ECG signals.

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Pun-García, Ernesto, and Marisa López-Vallejo. "A Survey of Analog-to-Digital Converters for Operation under Radiation Environments." Electronics 9, no. 10 (October 15, 2020): 1694. http://dx.doi.org/10.3390/electronics9101694.

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In this work, we analyze in depth multiple characteristic data of a representative population of radenv-ADCs (analog-to-digital converters able to operate under radiation). Selected ADCs behave without latch-up below 50 MeV·cm2/mg and are able to bear doses of ionizing radiation above 50 krad(Si). An exhaustive search of ADCs with radiation characterization data has been carried out throughout the literature. The obtained collection is analyzed and compared against the state of the art of scientific ADCs, which reached years ago the electrical performance that radenv-ADCs provide nowadays. In fact, for a given Nyquist sampling rate, radenv-ADCs require significantly more power to achieve lower effective resolution. The extracted performance patterns and conclusions from our study aim to serve as reference for new developments towards more efficient implementations. As tools for this purpose, we have conceived FOMTID and FOMSET, two new figures of merit to compare radenv-ADCs that consider electrical and radiation performance.

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Dalmia, Hemlata, and Sanjeet K. Sinha. "Analog to Digital Converters (ADC): A Literature Review." E3S Web of Conferences 184 (2020): 01025. http://dx.doi.org/10.1051/e3sconf/202018401025.

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The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.

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Saeidiyan, Zeinab, Mohammad Hosein Fatehi, Mehdi Taghizadeh, and Mohammad Mehdi Ghanbarian. "Enhancing the Accuracy and Speed of Sampling in Image Sensors by Designing Analog to Digital Converter with Power Decrease Approach." Journal of Sensors 2022 (January 24, 2022): 1–16. http://dx.doi.org/10.1155/2022/5075823.

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Analog to digital converters (ADCs) enable the processing of real-world analog signals in the digital realm. These converters are widely used in sensor systems, medical components, multimedia systems, image sensors, and wireless sensor nodes. Today, in portable devices that are powered by batteries, low power consumption and small area are a major and important need. Therefore, methods that can reduce power consumption and area have a variety of applications and are of great importance. Power consumption is one of the most important features of an integrated analog to digital converter. In this paper, a new design of low-power and fast analog to digital converter is presented. This design is used for specific applications for image processing. The suggested approach for rereading the image for limited number of pixels was designed and simulated, showing a considerable power decrease compared to the suggested state that depends on the pixel values.

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Bialek, J., A. Wickmann, F. Ohnhaeuser, G. Fischer, R. Weigel, and T. Ussmueller. "Implementation of a digital trim scheme for SAR ADCs." Advances in Radio Science 11 (July 4, 2013): 227–30. http://dx.doi.org/10.5194/ars-11-227-2013.

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Abstract. Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.

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KARMAKAR, SUPRIYA, JOHN A. CHANDY, and FAQUIR C. JAIN. "APPLICATION OF 25 NM QUANTUM DOT GATE FETs TO THE DESIGN OF ADC AND DAC CIRCUITS." International Journal of High Speed Electronics and Systems 20, no. 03 (September 2011): 653–68. http://dx.doi.org/10.1142/s0129156411006945.

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This paper describes design of analog-to-digital converters (ADCs) and digital-to-analog onverters (DACs) using field-effect transistors that exhibit three states in their transfer characteristics. An intermediate state " i " has been observed in the transfer characteristics (drain current-gate voltage) of FETs when two layers of cladded quantum dots (e.g. SiO x - Si and GeO x - Ge ) are introduced in the gate region above the tunnel insulator between the source and drain regions. Three states in such a transistor, defined as quantum dot gate field-effect transistor (QDG-FET) include two stable states (ON and OFF) and a low-current saturation state " i " in its transfer characteristics. QDG-FETs are quite different in construction than nanodot based nonvolatile memories, reported in the literature, where the quantum dots are sandwiched between a tunnel gate insulator and a relatively thick control gate dielectric. In this paper we present analog-to-digital converters (ADCs) using comparators based on QDG-FETs. A comparator is designed with fewer three-state QDG-FETs. Designs of 3-bit ADC, using 25 nm QDG-FETs, are simulated showing a signal-to-noise ratio (SNR) of ~18. In addition, the R-2R ladder problem, encountered in conventional analog-to digital converters (ADCs), is absent in QDG-FET based architecture.

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Bojja Venkatakrishnan, Satheesh, Elias A. Alwan, and John L. Volakis. "Challenges in Clock Synchronization for On-Site Coding Digital Beamformer." International Journal of Reconfigurable Computing 2017 (2017): 1–8. http://dx.doi.org/10.1155/2017/7802735.

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Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.

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BARRA, SAMIR, ABDELGHANI DENDOUGA, SOUHIL KOUDA, and NOUR-EDDINE BOUGUECHAL. "CONTRIBUTION TO THE ANALYSIS AND MODELING OF THE NON-IDEAL EFFECTS OF PIPELINED ADCs USING MATLAB." Journal of Circuits, Systems and Computers 22, no. 02 (February 2013): 1250085. http://dx.doi.org/10.1142/s0218126612500855.

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The present work analyses the non-ideal effects of pipelined analog-to-digital converters (ADCs), also sometimes referred to as pipeline ADCs, including the non-ideal effects in operational amplifiers (op-amps or OAs), switches and sampling circuits. We study these nonlinear effects in pipelined ADCs built using CMOS technology and switched-capacitor (SC) techniques. The proposed improved model of a pipelined ADC includes most of the non-idealities which affect its performance. This model, simulated using MATLAB, can determine the basic blocks specifications that allow the designer to meet given data converter requirements.

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Zhang, Xianyu, Xiaoqiang Qiao, Tao Liang, and Kang An. "Secure performance analysis and pilot spoofing attack detection in cell-free massive MIMO systems with finite-resolution ADCs." International Journal of Distributed Sensor Networks 18, no. 1 (January 2022): 155014772110677. http://dx.doi.org/10.1177/15501477211067743.

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In this article, the secure communication in cell-free massive multiple-input multiple-output system with low-resolution analog-to-digital converters is investigated in the presence of an active eavesdropper. Specifically, in this article, the deterioration caused by the analog-to-digital converter imperfections on the accuracy of the channel estimation and secure transmission performance is studied. Besides, the additive quantization noise model is utilized to analyze the impacts of the low-resolution analog-to-digital converters. The minimum mean square error channel estimation results show that there is a nonzero floor caused by the coarse analog-to-digital converters. Then, the closed-form expressions for both the legitimate users achievable ergodic rate and the information leakage to the eavesdropper are derived, respectively. Moreover, tight approximated ergodic secrecy rate expression is also presented with respect to analog-to-digital converters quantization bits, number of antennas, pilot power, and so on. To degrade the impacts of the pilot spoofing attack, an active attack detection approach based on random matrix theory is proposed which can only be operated at one access point. Simulation results are provided to corroborate the obtained results and analyze the impacts of various parameters on system secrecy performance. Also, the superiority of the proposed active attacks detection method is confirmed via simulation results.

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BAHATSKYI, Valentine, Maxim OBERTYUKH, and Serhii ZAKHARCHENKO. "HIGHLY-PRODUCTIVE ADC WITH COMBINED BALANCING." Herald of Khmelnytskyi National University. Technical sciences 315, no. 6(2) (December 29, 2022): 132–37. http://dx.doi.org/10.31891/2307-5732-2022-315-6(2)-132-137.

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Today analog-to-digital converters are used in computing and control systems which have greatly expanded in the era of the digital revolution. Increasing the accuracy, speed, energy efficiency, and reliability of analog-to-digital converters is extremely important. One of the most classic types of analog-to-digital converters is the sequential approximation and tracking type ADCs. The conversion time of the tracking type ADC is variable and is determined by the difference between the two readings of the input voltage. Therefore, combining the tracking approach and the method of successive approximation in the case of sharp jumps in the input signal allows you to significantly improve the conversion characteristic. Also the use of redundant counting systems for the weights of the ADC digits has significant advantages, which makes it possible to significantly increase the linearity of the conversion characteristic. The methods of construction of ADCs working on the principle of successive approximation and analog-digital converters whose operation algorithm is tracking are considered. A method of constructing a combined type ADC is proposed, which combines a follow-up conversion algorithm and a sequential approximation algorithm, which allows to improve the characteristics of ADC conversion. The expediency of using a combined type of redundant positional counting systems in ADCs has been proven. The analyzed property of redundant positional counting systems, which is inherent in them when the real weights of the digits deviate from their theoretical values, ensures the absence of “gaps” in the conversion characteristic, as well as the ability to perform the procedure of self-calibration of the weights of the ADC digits, thereby significantly improving the linearity of the conversion characteristic. It is indicated that even with the lengthening of the bit grid for ADCs built on the basis of redundant positional counting systems, their performance does not decrease.

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Zhu, Donglin, Maliang Liu, and Zhangming Zhu. "A High Energy Efficiency and Low Common-Mode Voltage Variation Switching Scheme for SAR ADCs." Journal of Circuits, Systems and Computers 27, no. 01 (August 23, 2017): 1850010. http://dx.doi.org/10.1142/s021812661850010x.

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In this paper, a high energy saving digital-to-analog converter (DAC) switching scheme with common-mode voltage variation in 1LSB is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). Based on the third reference ([Formula: see text]), split-capacitor technique and complementary switching method, the proposed switching scheme achieves a 99.6% switching energy reduction and a 75% area reduction compared to the conventional architecture, furthermore, the common-mode voltage varies only 1LSB during a conversion cycle.

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Dinčić, Milan R., Zoran H. Perić, Dragan B. Denić, and Zoran Stamenković. "Design of Robust Quantizers for Low-Bit Analog-to-Digital Converters for Gaussian Source." Journal of Circuits, Systems and Computers 28, supp01 (December 1, 2019): 1940002. http://dx.doi.org/10.1142/s0218126619400024.

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This paper considers the design of robust logarithmic [Formula: see text]-law companding quantizers for the use in analog-to-digital converters (ADCs) in communication system receivers. The quantizers are designed for signals with the Gaussian distribution, since signals at the receivers of communication systems can be very well modeled by this type of distribution. Furthermore, linearization of the logarithmic [Formula: see text]-law companding function is performed to simplify hardware implementation of the quantizers. In order to reduce energy consumption, low-resolution quantizers are considered (up to 5 bits per sample). The main advantage of these quantizers is high robustness — they can provide approximately constant SNR in a wide range of signal power (this is very important since the signal power at receivers can vary in wide range, due to fading and other transmission effects). Using the logarithmic [Formula: see text]-law companding quantizers there is no need for using automatic gain control (AGC), which reduces the implementation complexity and increases the speed of the ADCs due to the absence of AGC delay. Numerical results show that the proposed model achieves good performances, better than a uniform quantizer, especially in a wide range of signal power. The proposed low-bit ADCs can be used in MIMO and 5G massive MIMO systems, where due to very high operating frequencies and a large number of receiving channels (and consequently a large number of ADCs), the reduction of ADC complexity and energy consumption becomes a significant goal.

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Proskurin, M. P. "Optical analog-to-digital converters of UHF range of parallel type: review of approaches and designs." Optoelectronic Information-Power Technologies 41, no. 1 (July 28, 2021): 5–12. http://dx.doi.org/10.31649/1681-7893-2021-41-1-5-12.

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An overview of methods, architecture, block diagrams and designs of optical analog-to-digital converters (ADC) of direct conversion "radiation intensity - digital code" is given. Original design and technological solutions are proposed to improve the characteristics of optical ADCs of this type.

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Mai, Ziqi, Xiang Zhu, Hongwei Li, Jianwei Han, and Tao He. "Experiment Study of Single Event Functional Interrupt in Analog-to-Digital Converters Using a Pulsed Laser." Electronics 12, no. 13 (June 22, 2023): 2774. http://dx.doi.org/10.3390/electronics12132774.

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Single Event Functional Interrupt (SEFI) poses a severe threat to the normal operation of spacecraft. This paper investigates SEFI in Analog-to-Digital Converters (ADCs) with storage units using precision positioning of pulsed lasers. Based on the experiment, it was discovered that a bit flip in the configuration registers in ADCs results in changes in parameters such as digital filter frequency, operating mode, and gain, leading to an upward or downward offset of ADC output codes. Similarly, a bit flip in the calibration registers also causes ADC output codes to shift upwards or downwards, or even output a value of zero. Furthermore, it was observed that SEFI phenomena can occur due to current latch-up in ADC input pins, causing the inability to read or write data in ADC storage units. This current latch-up can be resolved through power cycling or configuring the pins into a high-impedance state. This work highlights the significance of SEFI phenomena in ADCs, emphasizing the serious threat posed by storage unit flipping-induced SEFI to the proper functioning of ADCs. Moreover, the SEFI phenomenon caused by current latch-up in input pins is difficult to detect in practice, making it highly elusive. Once it occurs, it severely impacts the functionality of ADCs.

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Suszyński, Robert, and Krzysztof Wawryn. "Rapid Prototyping of Third-Order Sigma-Delta A/D Converters." International Journal of Electronics and Telecommunications 59, no. 1 (March 1, 2013): 99–104. http://dx.doi.org/10.2478/eletel-2013-0012.

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Abstract Prototyping of third-order sigma-delta analog to digital converters (ΣΔ ADCs) has been presented in the paper. The method is based on implementation of field programmable analog arrays (FPAA) to configure and reconfigure proposed circuits. Three third-order ΣΔ ADC structures have been considered. The circuit characteristics have been measured and then the structure of the converters have been reconfigured to satisfy input specifications.

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Lingalugari, Murali, John Chandy, Faquir Jain, El-Sayed Hasaneen, and Evan Heller. "Compact Low-Power Analog-to-Digital Converters using Multi-State Spatial Wavefunction-Switched (SWS) FETs." International Journal of High Speed Electronics and Systems 23, no. 01n02 (March 2014): 1450005. http://dx.doi.org/10.1142/s0129156414500050.

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In this paper, we propose a new architecture for analog-to-digital converters (ADCs) using multistate spatial wavefunction-switched field-effect transistors (SWSFETs). SWSFETs are multiple quantum coupled well devices, where the wells are stacked vertically and the electron wavefunction switches from one well to another with the change in gate voltage. Quantum mechanical simulations of 3-well InGaAs-AlInAs SWSFET structures are presented. The designs and simulations of 2-bit and 3-bit ADCs using SWSFETs result in low power consumption and reduced device count which improves the speed of the data conversion.

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Min, Moonsik, Jae-Ik Kong, and Tae-Kyoung Kim. "Non-Orthogonal Multiple Access with One-Bit Analog-to-Digital Converters Using Threshold Adaptation." Sensors 23, no. 13 (June 28, 2023): 6004. http://dx.doi.org/10.3390/s23136004.

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In digital communication systems featuring high-resolution analog-to-digital converters (ADCs), the utilization of successive interference cancellation and detection can enhance the capacity of a Gaussian multiple access channel (MAC) by combining signals from multiple transmitters in a non-orthogonal manner. Conversely, in systems employing one-bit ADCs, it is exceedingly difficult to eliminate non-orthogonal interference using digital signal processing due to the considerable distortion present in the received signal when employing such ADCs. As a result, the Gaussian MAC does not yield significant capacity gains in such cases. To address this issue, we demonstrate that, under a given deterministic interference, the capacity of a one-bit-quantized channel becomes equivalent to the capacity without interference when an appropriate threshold value is chosen. This finding suggests the potential for indirect interference cancellation in the analog domain, facilitating the proposition of an efficient successive interference cancellation and detection scheme. We analyze the achievable rate of the proposed scheme by deriving the mutual information between the transmitted and received signals at each detection stage. The obtained results indicate that the sum rate of the proposed scheme generally outperforms conventional methods, with the achievable upper bound being twice as high as that of the conventional methods. Additionally, we have developed an optimal transmit power allocation algorithm to maximize the sum rate in fading channels.

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de la Rosa, Jose M. "Bandpass Sigma–Delta Modulation: The Path toward RF-to-Digital Conversion in Software-Defined Radio." Chips 2, no. 1 (March 2, 2023): 44–69. http://dx.doi.org/10.3390/chips2010004.

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This paper reviews the state of the art on bandpass ΣΔ modulators (BP-ΣΔMs) intended to digitize radio frequency (RF) signals. A priori, this is the most direct way to implement software-defined radio (SDR) systems since the analog/digital interface is placed closer to the antenna, thus reducing the analog circuitry and doing most of the signal processing in the digital domain. In spite of their higher programmability and scalability, RF BP-ΣΔM analog-to-digital converters (ADCs) require more energy to operate in the GHz range as compared with their low-pass (LP) counterparts. This makes conventional direct conversion receivers (DCRs) the commonplace approach due to their overall smaller energy consumption. This paper surveys some circuits and systems techniques which can make RF ADCs and SDR-based transceivers more efficient and feasible to be embedded in mobile terminals.

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García-Vellisca, Mariano Alberto, Carlos Quiterio Gómez Muñoz, María Sofía Martínez-García, and Angel de Castro. "Automatic Word Length Selection with Boundary Conditions for HIL of Power Converters." Electronics 12, no. 16 (August 17, 2023): 3488. http://dx.doi.org/10.3390/electronics12163488.

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Hardware-in-the-loop (HIL) is a common technique used for testing in power electronics. It draws upon FPGAs (field-programmable gate arrays) because they allow for reaching real-time simulation for mid-high switching frequencies. FPGA area and delay are keys to reaching a compromise between performance and accuracy. To minimize area and delay, signal word length (WL) is critical. Furthermore, the input and output’s WL should be carefully chosen because these signals come from ADCs (analog-to-digital converters) or go to DACs (digital-to-analog converters). In other words, the role of ADCs and DACs is the boundary condition when assigning all the signal WLs in an HIL model. This research presents an automatic method for computing the signal WLs in the corresponding model by considering input/output boundary conditions. This automatic method needs a single simulation to decide both the integer and fractional width of every signal. Our method accelerates the process, showing an advantage over manual methods and those requiring multiple simulations. The proposed method is applied to create all the WL assignments to the signals involved in a fixed-point coded buck converter model, which shows its feasibility.

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Luo, Jian, Jing Li, Shuangyi Wu, Ning Ning, and Yang Liu. "A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters." Journal of Circuits, Systems and Computers 28, no. 06 (June 12, 2019): 1950090. http://dx.doi.org/10.1142/s0218126619500907.

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In time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches, caused by the limited bandwidth of input signal traces and sample circuits, seriously deteriorate the spurious-free dynamic range (SFDR) of the system. This paper analyzes the influence of bandwidth mismatch errors under different sampling sequences. Eventually, based on a randomization technique and the simulated annealing algorithm (SAA), a bandwidth mismatch optimization technique is presented that can work well with other bandwidth mismatch calibration methods. The behavior simulation results indicate that an improvement of 7[Formula: see text]dB in the SFDR can be achieved with this technique in a 16-channel TI-ADC after timing and gain calibration.

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Ahiadormey, Roger Kwao, and Kwonhue Choi. "Performance Analysis of Rate Splitting in Massive MIMO Systems with Low Resolution ADCs/DACs." Applied Sciences 11, no. 20 (October 11, 2021): 9409. http://dx.doi.org/10.3390/app11209409.

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In this paper, we propose rate-splitting (RS) multiple access to mitigate the effects of quantization noise (QN) inherent in low-resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). We consider the downlink (DL) of a multiuser massive multiple-input multiple-output (MIMO) system where the base station (BS) is equipped with low-resolution ADCs/DACs. The BS employs the RS scheme for data transmission. Under imperfect channel state information (CSI), we characterize the spectral efficiency (SE) and energy efficiency (EE) by deriving the asymptotic signal-to-interference-and-noise ratio (SINR). For 1-bit resolution, the QN is very high, and the RS scheme shows no rate gain over the non-RS scheme. As the ADC/DAC resolution increases (i.e., 2–3 bits), the RS scheme achieves higher SE in the high signal-to-noise ratio (SNR) regime compared to that of the non-RS scheme. For a 3-bit resolution, the number of antennas can be reduced by 27% in the RS scheme to achieve the same SE as the non-RS scheme. Low-resolution DACs degrades the system performance more than low-resolution ADCs. Hence, it is preferable to equip the system with low-resolution ADCs than low-resolution DACs. The system achieves the best SE/EE tradeoff for 4-bit resolution ADCs/DACs.

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Li, Xin, Cheng Huang, Desheng Ding, and Jianhui Wu. "A Review on Calibration Methods of Timing-Skew in Time-Interleaved ADCs." Journal of Circuits, Systems and Computers 29, no. 02 (April 26, 2019): 2030002. http://dx.doi.org/10.1142/s0218126620300020.

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Time-interleaving has been a popular choice for multi-GHz analog-to-digital converters (ADCs) with a resolution of 8–14 bits. Unfortunately, inherent defects such as offset, gain, timing-skew mismatches among sub-ADCs degrade overall performance seriously. At present, the method for eliminating offset and gain mismatch is fairly straightforward; however, calibration for timing-skew is still in a state of exploration. A systematic overview of various calibration methods for timing-skew in time-interleaved ADCs (TI-ADCs) has been provided in this paper. Meanwhile, current state-of-the-art TI-ADCs recently are reported and several noteworthy trends can be observed from the statistical results.

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Song, Jinpeng, Shulin Tian, Yu-Hen Hu, Peng Ye, Kuojun Yang, Lianping Guo, and Wentao Wei. "Digital Estimation and Compensation of Analog Errors in Frequency-Interleaved ADCs." Journal of Circuits, Systems and Computers 28, no. 08 (July 2019): 1950134. http://dx.doi.org/10.1142/s0218126619501342.

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A novel digital compensation scheme for measuring, estimating and correcting linear weakly time-varying analog errors in frequency-interleaved analog-to-digital converters (FI-ADCs) is presented. This method features three important improvements over existing approaches: First, the Wigner–Ville distribution (WVD) is used to better estimate the nonstationary analog channel frequency response (ACFR) spectrum. Secondly, the estimated ACFR spectrum is approximated with a rational polynomial model using the [Formula: see text]-norm metric. The corresponding [Formula: see text]-norm minimization problem is solved using a primal-relaxed dual global optimization (PRD-GOP) method. Thirdly, the digital compensation circuitry is designed utilizing a preconditioned biconjugate gradient stabilized (BICGSTAB) algorithm that yields a computationally efficient solution. Numerical experimentations have been conducted and the outcomes validate the feasibility and superior performance of this proposed method.

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TSAI, CHIA-CHUN, KAI-WEI HONG, and TRONG-YEN LEE. "A BISECTION-BASED POWER REDUCTION DESIGN FOR CMOS FLASH ANALOG-TO-DIGITAL CONVERTERS." Journal of Circuits, Systems and Computers 18, no. 05 (August 2009): 933–45. http://dx.doi.org/10.1142/s0218126609005459.

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In this paper, we present a bisection-based power reduction design for CMOS flash analog-to-digital converters (ADCs). A comparator-based inverter is employed along with two switches of an NMOS and a PMOS, the bisection method can let only half of comparators in a flash ADC work in every clock cycle for reducing power consumption. A practical example of 6-bit flash ADC operates at 200 MHz sampling rate and 3.3 V supply voltage is demonstrated. The power consumption of proposed circuit is only 40.75 mW with HSPICE simulation. Compared with the traditional flash ADC, our bisection method can reduce up to 43.18% in terms of power dissipation.

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Choi, Seong-Wook, Kiho Seong, Sukho Lee, Kwang-Hyun Baek, and Yong Shim. "Noise Immunity-Enhanced Capacitance Readout Circuit for Human Interaction Detection in Human Body Communication Systems." Electronics 11, no. 4 (February 14, 2022): 577. http://dx.doi.org/10.3390/electronics11040577.

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Recent healthcare systems based on human body communication (HBC) require human interaction sensors. Due to the conductive properties of the human body, capacitive sensors are most widely known and are applied to many electronic gadgets for communication. Capacitance fluctuations due to the fact of human interaction are typically converted to voltage levels using some analog circuits, and then analog-to-digital converters (ADCs) are used to convert analog voltages into digital codes for further processing. However, signals detected by human touch naturally contain large noise, and an active analog filter that consumes a lot of power is required. In addition, the inclusion of ADCs causes the system to use a large area and amount of power. The proposed structure adopts a digital-based moving average filter (MAF) that can effectively operate as a low-pass filter (LPF) instead of a large-area and high-power consumption analog filter. In addition, the proposed ∆C detection algorithm can distinguish between human interaction and object interaction. As a result, two individual digital signals of touch/release and movement can be generated, and the type and strength of the touch can be effectively expressed without the help of an ADC. The prototype chip of the proposed capacitive sensing circuit was fabricated with commercial 65 nm CMOS process technology, and its functionality was fully verified through testing and measurement. The prototype core occupies an active area of 0.0067 mm2, consumes 7.5 uW of power, and has a conversion time of 105 ms.

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Espitia Castillo, Juan David Espitia, Enrique Cantó Navarro, and Enric Vidal-Idiarte. "Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA." Electronics 11, no. 3 (February 2, 2022): 447. http://dx.doi.org/10.3390/electronics11030447.

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The flexibility provided by FPGAs permits the implementation of several ADCs, each one configured with the required bit resolution and sampling frequency. The paper presents the design and implementation of scalable and parametrizable analog-to-digital converters (ADC), based on a successive approximation register (SAR), on FPGAs (field programmable gate arrays). Firstly, the work develops a systematic methodology for the implementation of a parametrizable SAR-based ADC from a set of building modules, such as the pulse-width modulator (PWM), external low-pass filter (LPF) and the analog comparator. The presented method allows choosing the LPF parameters for the required performance (resolution bits and sampling frequency) of a SAR-based ADC. Secondly, the paper also presents several optimizations on the PWM module to enhance the sampling frequency of implemented ADCs, and the method to choose the LPF parameters is adapted. The PWM and SAR logic are synthesizable and parametrizable, using a low number of resources, in order to be portable for low-cost FPGA families. The methodology and PWM optimizations are tested on a Zynq-7000 device from Xilinx; however, they can be adapted to any other FPGA.

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Tychuk, Ruslan B., and Sergii D. Petrovych. "ВИКОРИСТАННЯ ПРОГРАМ-ЕМУЛЯТОРІВ У НАВЧАННІ ФІЗИКИ МАЙБУТНІХ ТЕХНІКІВ ПРОГРАМІСТІВ." Information Technologies and Learning Tools 56, no. 6 (December 30, 2016): 137. http://dx.doi.org/10.33407/itlt.v56i6.1505.

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A modern gauge has been fused with digital and processor means of managing and processing information. Digital-to-analog (DACs) and analog-to-digital converters (ADCs) are widely used in various fields of modern science and technology. It is proposed to use the computer on the physics lessons and related subjects as the universal electric measuring device, which is based on using ADC and DAC audio adapter with an emphasis on the use of elements, means and principles of programming in its software. The study considers two aspects: methodology of teaching physics, gaining the professional competencies by engineer-programmers.

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EL-SANKARY, KAMAL, ALI ASSI, and MOHAMAD SAWAN. "NEW SAMPLING METHOD TO IMPROVE THE SFDR OF WIDE BANDWIDTH ADC DEDICATED TO NEXT GENERATION WIRELESS TRANSCEIVER." Journal of Circuits, Systems and Computers 13, no. 06 (December 2004): 1183–201. http://dx.doi.org/10.1142/s021812660400191x.

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Modern wireless communication standards that support high rates of voice and video streaming need high-speed Analog-to-Digital Converters (ADCs) with wide Spurious-Free Dynamic Range (SFDR). Conventional time-interleaved ADCs suffer from spurious components that seriously affect the SFDR. In this paper, we present the mathematical background describing the effect of randomizing the samples among the interleaved ADCs and we propose a digitally oriented method based on this analysis to randomize the mismatches among the ADC channels. Analyses and simulations show the effectiveness of the proposed approach in multi-channel ADCs with arbitrary bit resolution, channel's number and sampling rate. For a 10-bit 500 MS/s ADC, the SFDR achieved using the proposed randomizing method can be as wide as 75 dB, which is an enhancement of more than 26 dB comparing to the conventional time interleaved ADC.

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Wang, Hongzhe, Junjie Wang, Hao Hu, Guo Li, Shaogang Hu, Qi Yu, Zhen Liu, Tupei Chen, Shijie Zhou, and Yang Liu. "Ultra-High-Speed Accelerator Architecture for Convolutional Neural Network Based on Processing-in-Memory Using Resistive Random Access Memory." Sensors 23, no. 5 (February 21, 2023): 2401. http://dx.doi.org/10.3390/s23052401.

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Processing-in-Memory (PIM) based on Resistive Random Access Memory (RRAM) is an emerging acceleration architecture for artificial neural networks. This paper proposes an RRAM PIM accelerator architecture that does not use Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs). Additionally, no additional memory usage is required to avoid the need for a large amount of data transportation in convolution computation. Partial quantization is introduced to reduce the accuracy loss. The proposed architecture can substantially reduce the overall power consumption and accelerate computation. The simulation results show that the image recognition rate for the Convolutional Neural Network (CNN) algorithm can reach 284 frames per second at 50 MHz using this architecture. The accuracy of the partial quantization remains almost unchanged compared to the algorithm without quantization.

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Peralías, E. J., M. A. Jalón, and A. Rueda. "Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach." VLSI Design 2008 (July 22, 2008): 1–8. http://dx.doi.org/10.1155/2008/657207.

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This work presents a new method to estimate the nonlinearity characteristics of analog-to-digital converters (ADCs). The method is based on a nonnecessarily polynomial continuous and differentiable mathematical model of the converter transfer function, and on the spectral processing of the converter output under a sinusoidal input excitation. The simulation and experiments performed on different ADC examples prove the feasibility of the proposed method, even when the ADC nonlinearity pattern has very strong discontinuities. When compared with the traditional code histogram method, it also shows its low cost and efficiency since a significant lower number of output samples can be used still giving very realistic INL signature values.

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Mueller, Jan Henning, Sebastian Strache, Laurens Busch, Ralf Wunderlich, and Stefan Heinen. "The Impact of Noise and Mismatch on SAR ADCs and a Calibratable Capacitance Array Based Approach for High Resolutions." International Journal of Electronics and Telecommunications 59, no. 2 (June 1, 2013): 161–67. http://dx.doi.org/10.2478/eletel-2013-0019.

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Abstract This paper describes widely used capacitor structures for charge-redistribution (CR) successive approximation register (SAR) based analog-to-digital converters (ADCs) and analyzes their linearity limitations due to kT/C noise, mismatch and parasitics. Results of mathematical considerations and statistical simulations are presented which show that most widespread dimensioning rules are overcritical. For high-resolution CR SAR ADCs in current CMOS technologies, matching of the capacitors, influenced by local mismatch and parasitics, is a limiting factor. For high-resolution medium-speed CR SAR ADCs, a novel capacitance array based approach using in-field calibration is proposed. This architecture promises a high resolution with small unit capacitances and without expensive factory calibration as laser trimming.

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LI, JING, YANG LIU, SHUANGYI WU, NING NING, and QI YU. "DIGITAL BACKGROUND CALIBRATION FOR TIMING SKEW IN TIME-INTERLEAVED ADC." Journal of Circuits, Systems and Computers 23, no. 08 (June 18, 2014): 1450117. http://dx.doi.org/10.1142/s0218126614501175.

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This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). The timing error is detected by using the first derivative of the channel ADCs and a least-mean-square (LMS) loop is exploited to compensate the timing skew. The proposed scheme is effective within the entire frequency range of 0–fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes lesser power and smaller area.

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Chen, Ziyan, and Zun Yang. "A Study on Design and Optimization methods in Latch Type Comparator." Journal of Physics: Conference Series 2221, no. 1 (May 1, 2022): 012023. http://dx.doi.org/10.1088/1742-6596/2221/1/012023.

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Abstract The current state-of-the-art communication systems require analog-to-digital converters (ADCs) to sample the analog signals in digital representation at high speed and low power consumption with very high accuracy. Performance demand for ADCs directly promote the advancement of their basic component - the comparator. The traditional Strong-Arm dynamic comparator has been widely accepted for its fast decision, but it is limited by its significant voltage headroom and kickback noise. The double-tail latched dynamic comparator mitigates the aforementioned problems by allowing separate stages for the pre-amplifier and the latch so that it can have near- operation. However, energy consumption and propagation delay are still problems to be solved. In this article, we present a review of the recent improvements for the dynamic comparator architecture. The advantages and disadvantages of these techniques are also illustrated with simulation and measurement results.

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Magerramov, R. V. "APPLICATION OF THE PLL CONTROL AT THE REALIZATION OF A 16-THROUGH ADC." Issues of radio electronics, no. 8 (August 20, 2018): 6–12. http://dx.doi.org/10.21778/2218-5453-2018-8-6-12.

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This article describes the method of converting an analog signal into a digital code using a phase locked loop (PLL) circuit. The functional structure of the voltage-to-digital conversion circuit is considered. The application of the principle of phase-locked loop for controlling the duty cycle of the output signal of a phase detector when the voltage at the positive input of the operational amplifier included in the low-pass filter is investigated. In the modern world, analog-to-digital converters (ADCs) are available in almost every electronic device. The application of different ADC architectures is determined by their parameters and features by circuit and technological implementation. The phase-locked loop with a digital part (16-bit counter, storage register and data transfer interface) allows to obtain a precision analog-to-digital converter, based on a relatively simple circuit design, which has high accuracy and low noise level. Negative feedback of the PLL loop makes it possible to level the error of the passive elements of the low-pass filter (LPF) and the voltage controlled oscillator (VCO). The result of this work is an analysis of the ADC characteristics in the technological basis of 250 nm.

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Rahmani, Najmeh, Ebrahim Farshidi, and Esmaeil Fatemi-Behbahani. "Analysis and Modeling of Imperfections in Multi-Bit Per Stage Pipelined ADCs." Journal of Circuits, Systems and Computers 25, no. 07 (April 22, 2016): 1650079. http://dx.doi.org/10.1142/s0218126616500791.

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In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters.

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Liu, Changjian, and Houjun Wang. "Wideband Sparse Signal Acquisition Based on Serial Multi-Coset Sampling." Mathematical Problems in Engineering 2018 (July 3, 2018): 1–7. http://dx.doi.org/10.1155/2018/9208568.

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Traditional parallel multi-coset sampling (MCS), which has several sub-Analog-to-Digital-Converters (sub-ADCs) working parallelly, is an attractive sub-Nyquist sampling technique for wideband sparse signals. However, the mismatch among sub-ADCs in traditional parallel MCS, such as bias, gain, and timing skew mismatch, degrades the signal acquisition performance greatly. In this paper, a serial MCS scheme based on clocking single ADC with nonuniform clock is proposed. The nonuniform sampling clock is generated by a pseudo-random binary sequence generator. An additional Sample/Hold (S/H) is used to improve the analog bandwidth of the serial MCS. Moreover, universal sampling pattern is designed for the proposed serial MCS. The sampling pattern design should not only maximize the Kruskal rank of compressed sensing matrix but also take the ADC’s sub-Nyquist sampling rate into consideration. Numeral experiments are presented demonstrating that the mismatch among sub-ADCs in traditional parallel MCS degrades the reconstruction performance greatly, and the proposed serial MCS can avoid the mismatch tactfully.

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Nguyen, Hoang Trong, and Trang Hoang. "A Novel Framework of Genetic Algorithm and Spectre to Optimize Delay and Power Consumption in Designing Dynamic Comparators." Electronics 12, no. 16 (August 9, 2023): 3392. http://dx.doi.org/10.3390/electronics12163392.

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In integrated circuit (IC) design, analog circuits contribute significantly as the interface between real and digital world signals. Although they make up a relatively small portion of the overall circuit, their design process is often most time-consuming, mostly from the phase of manual iteration of circuit parameters to meet design specifications. Therefore, the design automation of analog circuits with the help of efficient optimization techniques arises as a promising candidate to address the issue. Among optimization algorithms, while the genetic algorithm (GA) has been shown to be effective in finding near-optimal solutions, it has not been extensively applied to the field of analog circuit design. Hence, this paper proposes a method to utilize GA in the optimization of a widely used circuit topology, namely the comparator. The comparator is considered the fundamental block in the design of most analog-to-digital converters (ADCs). For high-speed ADCs, dynamic comparators are usually chosen for the purpose of high speed and power efficiency. In summary, this paper introduces an innovative GA-Spectre architecture to optimize the dynamic comparator with respect to delay and power consumption. The post-optimized results are optimistic with a 72.61 ps delay and 3.11 µW power dissipation.

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D’Arco, Mauro, Ettore Napoli, Efstratios Zacharelos, Leopoldo Angrisani, and Antonio Giuseppe Maria Strollo. "Enabling Fine Sample Rate Settings in DSOs with Time-Interleaved ADCs." Sensors 22, no. 1 (December 29, 2021): 234. http://dx.doi.org/10.3390/s22010234.

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The time-base used by digital storage oscilloscopes allows limited selections of the sample rate, namely constrained to a few integer submultiples of the maximum sample rate. This limitation offers the advantage of simplifying the data transfer from the analog-to-digital converter to the acquisition memory, and of assuring stability performances, expressed in terms of absolute jitter, that are independent of the chosen sample rate. On the counterpart, it prevents an optimal usage of the memory resources of the oscilloscope and compels to post processing operations in several applications. A time-base that allows selecting the sample rate with very fine frequency resolution, in particular as a rational submultiple of the maximum rate, is proposed. The proposal addresses the oscilloscopes with time-interleaved converters, that require a dedicated and multifaceted approach with respect to architectures where a single monolithic converter is in charge of signal digitization. The proposed time-base allows selecting with fine frequency resolution sample rate values up to 200 GHz and beyond, still assuring jitter performances independent of the sample rate selection.

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Aminzadeh, Hamed, Mohammad Ali Dashti, and Mohammad Miralaei. "Nano-Scale Silicon Quantum Dot-Based Single-Electron Transistors and Their Application to Design of Analog-to-Digital Convertors at Room Temperature." Journal of Circuits, Systems and Computers 26, no. 12 (August 2017): 1750201. http://dx.doi.org/10.1142/s0218126617502012.

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Room-temperature analog-to-digital converters (ADCs) based on nanoscale silicon (Si) quantum dot (QD)-based single-electron transistors (SETs) can be very attractive for high-speed processors embedded in future generation nanosystems. This paper focuses on the design and modeling of advanced single-electron converters suited for operation at room temperature. In contrast to conventional SETs with metallic QD, the use of sub-10-nm Si QD results in stable operation at room temperature, as the observable Coulomb blockade regime covers effectively the higher temperature range. Si QD-based SETs are also fully compatible with advanced CMOS technology and they can be manufactured using routine nanofabrication steps. At first, we present the principles of operation of Si SETs used for room-temperature operation. Possible flash-type ADC architectures are then investigated and the design considerations of possible Coulomb oscillation regimes are addressed. A modified design procedure is then introduced for [Formula: see text]-bit SET-based ADCs, and validated through simulation of a 3-bit ADC with a sampling frequency of 5 GS/s. The ADC core is comprised from a capacitive signal divider followed by three periodic symmetric functions (PSFs). Simulation results demonstrate the stability of output signals at the room-temperature range.

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Rujzl, Miroslav, Ladislav Polak, and Jiri Petrzela. "Hybrid Analog Computer for Modeling Nonlinear Dynamical Systems: The Complete Cookbook." Sensors 23, no. 7 (March 30, 2023): 3599. http://dx.doi.org/10.3390/s23073599.

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This paper describes a design process for a universal development kit based on an analog computer concept that can model the dynamics of an arbitrarily complex dynamical system up to the fourth order. The constructed development kit contains digital blocks and associated analog-to-digital and digital-to-analog converters (ADCs and DAC), such that multiple-segmented piecewise-linear input–output characteristics can be used for the synthesis of the prescribed mathematical model. Polynomial input–output curves can be implemented easily by four-quadrant analog multipliers. The proposed kit was verified through several experimental scenarios, starting with simple sinusoidal oscillators and ending with generators of continuous-time robust chaotic attractors. The description of each individual part of the development kit is accompanied by links to technical documentation, allowing skilled readers in the construction of electronic systems to replicate the proposed functional example. For this purpose, the electrical scheme of the hybrid analog computer and all important source codes are available online.

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ZHU, ZHANGMING, HONGBING WU, GUANGWEN YU, YANHONG LI, LIANXI LIU, and YINTANG YANG. "A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC." Journal of Circuits, Systems and Computers 22, no. 04 (April 2013): 1350018. http://dx.doi.org/10.1142/s0218126613500187.

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A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

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Alvero-Gonzalez, Leidy Mabel, Victor Medina, Vahur Kampus, Susana Paton, Luis Hernandez, and Eric Gutierrez. "Ring-Oscillator with Multiple Transconductors for Linear Analog-to-Digital Conversion." Electronics 10, no. 12 (June 11, 2021): 1408. http://dx.doi.org/10.3390/electronics10121408.

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This paper proposes a new circuit-based approach to mitigate nonlinearity in open-loop ring-oscillator-based analog-to-digital converters (ADCs). The approach consists of driving a current-controlled oscillator (CCO) with several transconductors connected in parallel with different bias conditions. The current injected into the oscillator can then be properly sized to linearize the oscillator, performing the inverse current-to-frequency function. To evaluate the approach, a circuit example has been designed in a 65-nm CMOS process, leading to a more than 3-ENOB enhancement in simulation for a high-swing differential input voltage signal of 800-mVpp, with considerable less complex design and lower power and expected area in comparison to state-of-the-art circuit based solutions. The architecture has also been checked against PVT and mismatch variations, proving to be highly robust, requiring only very simple calibration techniques. The solution is especially suitable for high-bandwidth (tens of MHz) medium-resolution applications (10–12 ENOBs), such as 5G or Internet-of-Things (IoT) devices.

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Shlezinger, Nir, and Yonina C. Eldar. "Deep Task-Based Quantization." Entropy 23, no. 1 (January 13, 2021): 104. http://dx.doi.org/10.3390/e23010104.

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Quantizers play a critical role in digital signal processing systems. Recent works have shown that the performance of acquiring multiple analog signals using scalar analog-to-digital converters (ADCs) can be significantly improved by processing the signals prior to quantization. However, the design of such hybrid quantizers is quite complex, and their implementation requires complete knowledge of the statistical model of the analog signal. In this work we design data-driven task-oriented quantization systems with scalar ADCs, which determine their analog-to-digital mapping using deep learning tools. These mappings are designed to facilitate the task of recovering underlying information from the quantized signals. By using deep learning, we circumvent the need to explicitly recover the system model and to find the proper quantization rule for it. Our main target application is multiple-input multiple-output (MIMO) communication receivers, which simultaneously acquire a set of analog signals, and are commonly subject to constraints on the number of bits. Our results indicate that, in a MIMO channel estimation setup, the proposed deep task-bask quantizer is capable of approaching the optimal performance limits dictated by indirect rate-distortion theory, achievable using vector quantizers and requiring complete knowledge of the underlying statistical model. Furthermore, for a symbol detection scenario, it is demonstrated that the proposed approach can realize reliable bit-efficient hybrid MIMO receivers capable of setting their quantization rule in light of the task.

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Murthy Dumpala, Ramana, and . "Technique to Improve SNR for Sigma Delta Adcs for Audio Signals." International Journal of Engineering & Technology 7, no. 3.6 (July 4, 2018): 91. http://dx.doi.org/10.14419/ijet.v7i3.6.14946.

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A RISR architecture for Sigma-delta analog to digital converters with modified noise transfer function to obtain a better performance in terms of SNR is proposed. Cascading of two modified second order modulators are done to achieve 4th order modulator. Behavioral simulations are done to study the performance of feed-forward and the modified cascaded architecture. They are designed to operate at 1.28MHz clock frequency for audio applications (OSR of 32). It is noted that SNR of 115dB is achieved by cascading of two Modified second order RISR architectures which is 8dB more than the normal RISR architecture.

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Correia, Ana, Vítor Grade Tavares, Pedro Barquinha, and João Goes. "All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications." Journal of Low Power Electronics and Applications 12, no. 4 (December 7, 2022): 64. http://dx.doi.org/10.3390/jlpea12040064.

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In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-ΔM with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated FoMWalden is close to 16.2 fJ/conv.-step.

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RAMAMOORTHY, SARAVANAN, and HAIBO WANG. "ADDRESSING MEMORY EFFECT FOR RAIL-TO-RAIL COMPARATOR WITH NEAR-THRESHOLD SUPPLY VOLTAGE." Journal of Circuits, Systems and Computers 22, no. 06 (July 2013): 1350048. http://dx.doi.org/10.1142/s0218126613500485.

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Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impacts of the proposed design modification on comparator speed, offset voltage and power consumptions are discussed. Based on a 0.13 μm CMOS technology and with a 0.5 V power supply, the proposed comparator is compared with the original comparator in terms of memory effect, speed, power consumption and input offset voltage. The integral and differential nonlinearity (INL and DNL) of 10-bit SAR ADCs with using the proposed and original comparators are also compared.

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ElGabry, Mohammed A., Ali H. Hassan, Hassan Mostafa, and Ahmed M. Soliman. "A new design methodology for voltage-to-frequency converters (VFCs) circuits suitable for time-based analog-to-digital converters (T-ADCs)." Analog Integrated Circuits and Signal Processing 94, no. 2 (December 7, 2017): 277–87. http://dx.doi.org/10.1007/s10470-017-1092-2.

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Lyu, Fangxing, Zekang Xiong, Fei Li, and Xin Fang. "A Photonic Time-Interleaved ADC Architecture Based on Optical Clock Distribution and Elector-Optical Modulation Technology." Journal of Nanoelectronics and Optoelectronics 18, no. 4 (April 1, 2023): 435–40. http://dx.doi.org/10.1166/jno.2023.3409.

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A photonic time-interleaved analog-to-digital conversion (PTIADC) scheme by exploring optical clock distribution technology and elector-optical modulation technology is presented in this work. In the proposed PTIADC system, the interleaved sampling clocks for several channel analog-to-digital converters (ADCs) are implemented by optical clocks. A proof-of-concept experiment with a four-channel 400 MS/s PTIADC system has been achieved, and the performance has been experimentally demonstrated. Experimental results show that the proposed method can offer four-channel clock signals with low-timing jitters. The effective number of bits (ENOB) of the constructed PTIADC is ∼6 bits. Additionally, timing mismatch calibration via conveniently adjusting the length of optical delay lines produces a 26 dB spur suppression.

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Journal articles on the topic 'Analog-to-digital converters (ADCs)'

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