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Relevant bibliographies by topics / Analog-to-digital converters for imaging applications / Dissertations / Theses

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Dissertations / Theses on the topic 'Analog-to-digital converters for imaging applications'

Author: Grafiati

Published: 4 June 2021

Last updated: 11 February 2022

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1

Mahsereci, Yigit Uygar. "A Successive Approximation Register Analog-to-digital Converter For Low Cost Microbolometers." Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12614031/index.pdf.

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Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achiev

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2

Zhang, Dai. "Ultra-Low-Power Analog-to-Digital Converters for Medical Applications." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-110387.

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Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultralow- power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent ADC architectures, the successiveapproximation-register (SAR) ADC exhibits significantly high energy eff

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3

Gustafsson, E. Martin I. "Reconfigurable Analog to Digital Converters for Low Power Wireless Applications." Doctoral thesis, Kista : KTH School of Information and Communication Technology, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4774.

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4

Serrano, Guillermo J. "Floating-gate digital to analog converter for retinal implant applications." Thesis, Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/13312.

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5

Tao, Sha. "Power-Efficient Continuous-Time Incremental Sigma-Delta Analog-to-Digital Converters." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-164282.

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Over the past decade, there has been a growing interest in the devel- opment of integrated circuits (ICs) for wearable or implantable biosensors, aiming at providing personalized healthcare services and reducing the health-care expenses. In biosensor ICs, the analog-to-digital converter (ADC) is a key building block that acts as a bridge between analog signals and digital processors. Since most of the biosensors are attached to or implanted in hu- man bodies and powered by either portable batteries or harvested energy, ultra-low-power operation is often required. The stringent power budget im-

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6

Soell, Sven. "Theory and applications of delta-sigma analogue-to-digital converters without negative feedback." Thesis, Connect to e-thesis, 2008. http://theses.gla.ac.uk/369/.

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Thesis (Ph.D.) - University of Glasgow, 2008.<br>Ph.D. thesis submitted to the Department of Electronics and Electrical Engineering, Faculty of Engineering, University of Glasgow, 2008. Includes bibliographical references. Print version also available.

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7

Sutula, Stepan. "Low-power high-resolution cmos switched-capacitor delta-sigma analog-to-digital converters for sensor applications." Doctoral thesis, Universitat Autònoma de Barcelona, 2015. http://hdl.handle.net/10803/667348.

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Aquesta tesi doctoral explora mètodes per augmentar tant l'eficiència energètica com la resolució de convertidors analògic-digital (ADCs) Delta-Sigma de condensadors commutats mitjançant innovadors circuits CMOS de baix consum. En aquest sentit, s'ha prioritzat un alt rendiment, fiabilitat i baixos costos de fabricació dels circuits, així com un flux de disseny simple per ser reutilitzat per la comunitat científica. S'ha escollit l'arquitectura Delta-Sigma per la seva simplicitat i la tolerància a les imperfeccions dels seus blocs bàsics. La recerca de circuits presentada utilitza tècniques

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8

Marble, William J. "Design and analysis of charge-transfer amplifiers for low-power analog-to-digital converter applications /." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd418.pdf.

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9

Lee, Sang Min. "A CMOS analog pulse compressor with a low-power analog-to-digital converter for MIMO radar applications." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/42875.

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Multiple-input multiple-output (MIMO) radars, which utilize multiple transmitters and receivers to send and receive independent waveforms, have been actively investigated as a next generation radar technology inspired by MIMO techniques in communication theory. Complementary metal-oxide-semiconductor (CMOS) technology offers an opportunity for dramatic cost and size reduction for a MIMO array. However, the resulting formidable signal processing burden has not been addressed properly and remains a challenge. On the other hand, from a block-level point of view, an analog-to-digital converter (AD

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10

Jalali, Farahani Bahar. "Adaptive digital calibration techniques for high speed, high resolution SIGMA DELTA ADCs for broadband wireless applications." Columbus, Ohio : Ohio State University, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1133192371.

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11

Ismail, Ayman. "High-Speed Analog-to-Digital Converters for Broadband Applications." Thesis, 2007. http://hdl.handle.net/10012/3477.

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Flash Analog-to-Digital Converters (ADCs), targeting optical communication standards, have been reported in SiGe BiCMOS technology. CMOS implementation of such designs faces two challenges. The first is to achieve a high sampling speed, given the lower gain-bandwidth (lower ft) of CMOS technology. The second challenge is to handle the wide bandwidth of the input signal with a certain accuracy. Although the first problem can be relaxed by using the time-interleaved architecture, the second problem remains as a main obstacle to CMOS implementation. As a result, the feasibility of the CMOS implem

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12

Lin, Sue-Hwa, and 林淑華. "Design of high-speed analog to digital converters for digital video applications." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/44c8a8.

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碩士<br>國立清華大學<br>工程與系統科學系<br>92<br>The paper presents a pipeline analog to digital converter (ADC) used for video applications. The 10-bit ADC has an input signal range of ±0.5 V with the resolution near 1 mV. Sampling rate is 100 MHz. To reach the high speed, low power conversion, ADC implemented with pipeline architecture. How to implement a high speed, high gain Opamp is the bottleneck of ADC design. The Opamp used gain boost and two-stage techniques. Gain boost circuit strengthen the DC gain of Opamp without reducing bandwidth. Two-stage can get wide input common mode range and wide output

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13

Wu, Yen-Ting, and 吳彥霆. "Design of Low Power SAR Analog-to-Digital Converters for Biomedical System Applications." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/q3z3fz.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>105<br>This thesis presents two analog and mixed-signal circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the experimental prototypes, the presented techniques are verified. The first technique is hybrid unit capacitors. Comparing to last work [1], the resolution bit has been enhanced by adding extra capacitor arrays with an additional smaller unit capacitor. This relevant prototype SAR ADC consumes 10.55μW at 1-V supply, and the effective number of bit (ENOB) is 10.827

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14

Jhou, Cheng-Yi, and 周承毅. "Design of Low Power SAR Analog-to-Digital Converters for Biomedical System Applications." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/79187123663232007564.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>104<br>This thesis presents two analog and mixed-signal circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the experimental prototypes, the presented techniques are verified. The first technique is the layout schemes of a unit capacitor. Compared to last work [1], the surroundings of a unit capacitor is identical to each unit capacitor, which does not take process variation into consideration. This relevant prototype SAR ADC consumes 6.2μW at 1-V supply, and the effectiv

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15

Singh, Ritu. "Luminescence Contact Imaging Microsystems." Thesis, 2009. http://hdl.handle.net/1807/17445.

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This thesis presents two hybrid luminescence-based biochemical photosensory microsystems: a CMOS/microfluidic chemiluminescence contact imager, and a CMOS/thin-film fluorescence contact imager. A compact, low-power analog-to-digital converter (ADC) architecture for use in such sensory microsystems is also proposed. Both microsystems are prototyped in a standard 0.35um CMOS technology. The CMOS/microfluidic microsystem integrates a 64x128-pixel CMOS imager and a soft polymer microfluidic network. Circuit techniques are employed to reduce the dark current and circuit noise for low-level light

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16

Ren-LiChen and 陳仁禮. "Design of Low-Power Current-Steering Digital-to-Analog Converters for Wireless Communication Applications." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/94146635807191250180.

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博士<br>國立成功大學<br>電機工程學系碩博士班<br>101<br>This dissertation proposes several circuit design techniques for current-steering digital-to-analog converters (DACs) on wireless communication applications to lower the power consumption. Moreover, a compound current cell is also proposed to make current-steering DACs in a system-on-a-chip (SoC) have more functionality for reducing the integration challenges and cost. Hence, three proof-of-concept prototypes are presented to demonstrate these techniques. According to the measurement results of the prototypes, the proposed techniques have good power efficie

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17

Yu, Chia-Wei, and 余家緯. "Design of 90nm Analog-to-Digital Converters for Low-Power and High-Speed Applications." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/11433305567541299785.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>102<br>Pipelined analog-to-digital converters (ADCs) and Successive-approximation register (SAR) analog-to-digital converters have been widely utilized in high speed communication system for mid to high resolution. This thesis proposes two circuit design techniques for analog-to-digital converters (ADCs), including pipelined ADC with hybrid calibration and successive-approximation register (SAR) ADC. According to the simulation and measurement results of the proof-of-concept prototypes, the proposed techniques are able to improve the operating speed. The proposed te

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18

Sajjadian, Farnad. "A 10MHz flash analog-to-digital converter system for digital oscilloscope and signal processing applications." 1985. http://hdl.handle.net/2097/27577.

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19

Yang, Yuqing Ph D. "System oriented delta sigma analog-to-digital modulator design for ultra high precisoin data acquisition applications." 2008. http://hdl.handle.net/2152/18176.

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As high precision data acquisition systems continue to improve their performance and power efficiency to migrate into portable devices, increasing demands are placed on the performance and power efficiency of the analog-to-digital conversion modulator. On the other hand, analog-to-digital modulator performance is largely limited by several major noise sources including thermal noise, flicker noise, quantization noise leakage and internal analog and digital coupling noise. Large power consumption and die area are normally required to suppress the above noise energies, which are the major challe

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20

Javed, Gaggatur Syed. "Integrated Interfaces for Sensing Applications." Thesis, 2016. http://hdl.handle.net/2005/2914.

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Sensor interfaces are needed to communicate the measured real-world analog values to the base¬band digital processor. They are dominated by the presence of high accuracy, high resolution analog to digital converters (ADC) in the backend. On most occasions, sensing is limited to small range measurements and low-modulation sensors where the complete dynamic range of ADC is not utilized. Designing a subsystem that integrates the sensor and the interface circuit and that works with a low resolution ADC requiring a small die-area is a challenge. In this work, we present a CMOS based area eﬃcient, i

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