Dissertations / Theses on the topic 'Analog-to-digital converters for imaging applications'

Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achieve the lowest power, yet the highest performance. The successive approximation architecture is chosen, due to its low-power, small-area nature, high resolution potential, and the achievable speed, as the ADC needs to support a 160x120 imager at a frame rate of 25 frames/sec (fps). The resolution of the ADC is 14 bit at a sampling rate of 700 Ksample/sec (Ksps). The noise level is at the order of 1.3 LSBs. The true resolution of the ADC is set to be higher than the need of the current low-cost microbolometers, so that it is not the limiting factor for the overall noise specifications. The design is made using a 0.18&micro<br>m CMOS process, for easy porting of design to the next generation low-cost microbolometers. An optional dual buffer approach is used for improved linearity, a modified, resistive digital-to-analog converter (DAC) is used for enhanced digital correction, and a highly configurable digital controller is designed for on-silicon modification of the device. Also, a secondary 16-bit high performance ADC with the same topology is designed in this thesis. The target of the high resolution ADC is low speed sensors, such as temperature sensors or very small array sizes of infrared sensors. Both of the SAR ADCs are designed without switched capacitor circuits, the operation speed can be minimized as low as DC if an extremely low power operation is required. A compact test setup is designed and implemented for the ADC. It consists of a custom designed proximity card, an FPGA card, and a PC. The proximity card is designed for high resolution ADC testing and includes all analog utilities such as voltage references, voltage regulators, digital buffers, high resolution DACs for reference generation, voltage buffers, and a very high resolution &Delta<br>-&Sigma<br>DAC for input voltage generation. The proximity card is fabricated and supports automated tests, because many components surrounding the ADC are digitally controllable. The FPGA card is selected as a commercially available card with USB control. The full chip functionalities and performances of both ADCs are simulated. The complete layouts of both versions are finished and submitted to the foundry. The ADC prototypes consist of more than 7500 transistors including the digital circuitry. The power dissipation of the 16-bit ADC is around 10mW, where the 14-bit device consumes 30mW. Each of the dies is 1mm x 5mm, whereas the active circuits occupy around 0.5mm x 1.5mm silicon area. These chips are the first steps in METU for the realization of the digital-in digital-out low cost microbolometers and low cost sensors.

Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultralow- power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent ADC architectures, the successiveapproximation-register (SAR) ADC exhibits significantly high energy efficiency due to its good trade-offs among power consumption, conversion accuracy, and design complexity. This thesis examines the physical limitations and investigates the design methodologies and circuit techniques for low-speed and ultra-low-power SAR ADCs. The power consumption of SAR ADC is analyzed and its lower bounds are formulated. At low resolution, power is bounded by minimum feature sizes; while at medium to high resolution, power is bounded by thermal noise and capacitor mismatch. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity for high resolution, a bottom-up weight calibration technique is further proposed. It utilizes redundancy generated by a non-binary-weighted capacitive network, and measures the actual weights of more significant capacitors using less significant capacitors. Three SAR ADCs have been implemented. The first ADC, fabricated in a 0.13μm CMOS process, achieves 9.1ENOB with 53-nW power consumption at 1kS/s. The main key to achieve the ultra-low-power operation turns out to be the maximal simplicity in the ADC architecture and low transistor count. In addition, a dual-supply voltage scheme allows the SAR digital logic to operate at 0.4V, reducing the overall power consumption of the ADC by 15% without any loss in performance. Based on the understanding from the first ADC and motivated by the predicted power bounds, the second ADC, a single-supply 9.1-ENOB SAR ADC in 65nm CMOS process has been further fabricated. It achieves a substantial (94%) improvement in power consumption with 3-nW total power at 1kS/s and 0.7V. Following the same concept of imposing maximal simplicity in the ADC architecture and taking advantage of the smaller feature size, the ultra-low-power consumption is achieved by a matched splitarray capacitive DAC, a bottom-plate full-range input-sampling scheme, a latch-based SAR control logic, and a multi-VT design approach. The third ADC fabricated in 65nm CMOS process targets at a higher resolution of 14b and a wider bandwidth of 5KHz. It achieves 12.5ENOB  with 1.98-μW power consumption at 0.8V and 10kS/s. To achieve the high resolution, the ADC implements a uniform-geometry non-binary-weighted capacitive DAC and employs a secondary-bit approach to dynamically shift decision levels for error correction. Moreover, a comparator with bias control utilizes the redundancy to reduce the power consumption.

Over the past decade, there has been a growing interest in the devel- opment of integrated circuits (ICs) for wearable or implantable biosensors, aiming at providing personalized healthcare services and reducing the health-care expenses. In biosensor ICs, the analog-to-digital converter (ADC) is a key building block that acts as a bridge between analog signals and digital processors. Since most of the biosensors are attached to or implanted in hu- man bodies and powered by either portable batteries or harvested energy, ultra-low-power operation is often required. The stringent power budget im- poses challenges in designing power-efficient ADCs, especially when targeting high-resolution. Among different ADC architectures, the Sigma-Delta (Σ∆) ADC has emerged as the most suitable for low-power, high-resolution appli- cations. This thesis aims to enhance the power efficiency of continuous-time (CT) incremental Σ∆ (IΣ∆) ADCs by exploring design techniques at both architectural and circuit levels. The impact of feedback DACs in CT IΣ∆ ADCs is investigated, so as to provide power-efficient feedback DAC solutions, suitable for biosensor ap- plications. Different DAC schemes are examined analytically considering the trade-off between timing error sensitivity and power consumption. The an- alytical results are verified through behavioral simulations covering both the conventional and incremental Σ∆ modes. Additionally, by considering a typi- cal biosensor application, different feedback DACs are further compared, aim- ing to offer a reference for selecting a power-efficient DAC scheme. A two-step CT IΣ∆ ADC is proposed, analyzed, implemented and tested, with the objective of offering flexible and power-efficient A/D conversion in neural recording systems. By pipelining two CT IΣ∆ ADCs, the pro- posed ADC can achieve high-resolution without sacrificing the conversion rate. Power-efficient circuits are proposed to implement the active blocks of the proposed ADC. The feasibility and power efficiency of the two-step CT IΣ∆ ADC are validated by measurement results. Furthermore, enhancement techniques from both the architecture and circuit perspectives are discussed and implemented, which are validated by post-layout simulations. A comparative study of several CT IΣ∆ ADC architectures is presented, aiming to boost the power efficiency by reducing the number of cycles per con- version while benefiting from the advantage of CT implementation. Five CT IΣ∆ ADC architectures are analyzed and simulated to evaluate their effective- ness under ideal conditions. Based on the theoretical results, a second-order CT IΣ∆ ADC and an extended-range CT IΣ∆ ADC are selected as implemen- tation case studies together with the proposed two-step CT IΣ∆ ADC. The impact of critical circuit non-idealities is investigated. The three ADCs are then implemented and fabricated on a single chip. Experimental results reveal that the three prototype ADCs improve considerably the power efficiency of existing CT IΣ∆ ADCs while being very competitive when compared to all types of the state-of-the-art IΣ∆ ADCs.<br><p>QC 20150422</p>

Thesis (Ph.D.) - University of Glasgow, 2008.<br>Ph.D. thesis submitted to the Department of Electronics and Electrical Engineering, Faculty of Engineering, University of Glasgow, 2008. Includes bibliographical references. Print version also available.

Aquesta tesi doctoral explora mètodes per augmentar tant l'eficiència energètica com la resolució de convertidors analògic-digital (ADCs) Delta-Sigma de condensadors commutats mitjançant innovadors circuits CMOS de baix consum. En aquest sentit, s'ha prioritzat un alt rendiment, fiabilitat i baixos costos de fabricació dels circuits, així com un flux de disseny simple per ser reutilitzat per la comunitat científica. S'ha escollit l'arquitectura Delta-Sigma per la seva simplicitat i la tolerància a les imperfeccions dels seus blocs bàsics. La recerca de circuits presentada utilitza tècniques de condensadors commutats per aconseguir un aparellament adequat entre els dispositius i per tenir dependència només de la fluctuació del rellotge extern. Les tècniques de disseny de circuits analògics de baix corrent desenvolupades tenen com a objectiu l'eficiència energètica, aprofitant les regions d'inversió feble i moderada d'operació del transistor MOS. També s'investiguen nous amplificadors operacionals Classe AB com a elements actius, tractant d'utilitzar energia només durant les transicions dinàmiques, el que redueix el consum de potència a nivell de circuit. Els circuits no utilitzats durant un determinat període de temps es desactiven, reduint així el consum de potència a nivell de sistema i minimitzant el nombre de dispositius de commutació en el camí de senyal. S'ha millorat la fiabilitat dels circuits proposats evitant els elevadors de tensió o altres tècniques que poden incrementar els voltatges d'operació més enllà del d'alimentació nominal de la tecnologia CMOS utilitzada. A més, per incrementar el rendiment de producció dels ADCs resultants, s'ha enfocat la recerca de disseny sobre noves topologies de circuits amb una baixa sensibilitat a les variacions tant del procés de fabricació com de la temperatura. Un modulador Delta-Sigma de 96.6 dB de SNDR, 50 kHz d'ample de banda, 1.8 V i 7.9 mW per a ADCs s'ha implementat en una tecnologia estàndard CMOS de 0.18 µm basat en les novetats proposades. Els resultats de les mesures indiquen la millora de l'estat de l'art d'ADCs d'alta resolució sense elevadors de tensió del senyal de rellotge, calibratge o compensació digital, fet que beneficia una àmplia gamma d'aplicacions de sensors intel·ligents. Una altra contribució en el marc d'aquest treball de recerca és la millora dels amplificadors operacionals de Classe AB d'una sola etapa exclusivament MOS. Els amplificadors commutats de mirall variable desenvolupats, amb la seva remarcable eficiència de corrent i compensació intrínseca de freqüència juntament amb un fons d'escala i un guany de llaç obert grans, són adequats per a un ample ventall d'aplicacions de baix consum i d'alta precisió més enllà de l'àmbit<br>This PhD thesis explores methods to increase both the power efficiency and the resolution of switched-capacitor Delta-Sigma analog-to-digital converters (ADCs) by employing novel CMOS low-power circuits. A high circuit performance, reliability, low manufacturing costs and a simple design flow to be reused by the scientific community are prioritized. The Delta-Sigma architecture is chosen because of its simplicity and tolerance for its basic block imperfections. The presented circuit research makes use of switched-capacitor techniques to achieve an appropriate matching between the devices and to be dependent only on the external clock jitter. The developed low-current analog circuit techniques target power efficiency, taking advantage of the weak- and moderate-inversion regions of the MOS transistor operation. Novel Class-AB operational amplifiers are also investigated as active elements, trying to use energy only for dynamic transitions, thus reducing power consumption at the circuit level. The circuits unused during a certain period of time are switched off, thus reducing power consumption at the system level and minimizing the number of signal-path switching devices. The circuit reliability is improved by avoiding bootstrapping or other techniques which may increase the operation voltages beyond the nominal supply of the target CMOS technology. Furthermore, the design research also focuses on new circuit topologies with a low sensitivity to both process and temperature deviations in order to increase the yield of the resulting ADCs. A 96.6-dB-SNDR 50-kHz-BW 1.8-V 7.9-mW Delta-Sigma modulator for ADCs is implemented in a standard 0.18-µm CMOS technology based on the proposed novelties. The measurement results indicate the improvement of the state of the art of high-resolution ADCs without clock bootstrapping, calibration or digital compensation, benefiting a wide range of smart sensing applications. Another contribution made in the scope of this research work is the improvement of MOS-only single-stage Class-AB operational amplifiers. The developed switched variable-mirror amplifiers, with their remarkable current efficiency and intrinsic frequency compensation together with high full-scale value and open-loop gain, are suitable for low-power high-precision applications extending beyond the specific area of ADCs, such as digital-to-analog converters (DACs), filters or generators.

Multiple-input multiple-output (MIMO) radars, which utilize multiple transmitters and receivers to send and receive independent waveforms, have been actively investigated as a next generation radar technology inspired by MIMO techniques in communication theory. Complementary metal-oxide-semiconductor (CMOS) technology offers an opportunity for dramatic cost and size reduction for a MIMO array. However, the resulting formidable signal processing burden has not been addressed properly and remains a challenge. On the other hand, from a block-level point of view, an analog-to-digital converter (ADC) is required for mixed-signal processing to convert analog signals to digital signals, but an ADC occupies a significant portion of a system's budget. Therefore, improvement of an ADC will greatly enhance various trade-offs. This research presents an alternative and viable approach for a MIMO array from a system architecture point of view, and also develops circuit level improvement techniques for an ADC. This dissertation presents a fully-integrated analog pulse compressor (APC) based on an analog matched filter in a mixed signal domain as a key block for the waveform diversity MIMO radar. The performance gain of the proposed system is mathematically presented, and the proposed system is successfully implemented and demonstrated from the block level to the system level using various waveforms. Various figures of merit are proposed to aid system evaluations. This dissertation also presents a low-power ADC based on an asynchronous sample-and-hold multiplying SAR (ASHMSAR) with an enhanced input range dynamic comparator as a key element of a future system. Overall, with the new ADC, a high level of system performance without severe penalty on power consumption is expected. The research in this dissertation provides low-cost and low-power MIMO solutions for a future system by addressing both system issues and circuit issues comprehensively.

Flash Analog-to-Digital Converters (ADCs), targeting optical communication standards, have been reported in SiGe BiCMOS technology. CMOS implementation of such designs faces two challenges. The first is to achieve a high sampling speed, given the lower gain-bandwidth (lower ft) of CMOS technology. The second challenge is to handle the wide bandwidth of the input signal with a certain accuracy. Although the first problem can be relaxed by using the time-interleaved architecture, the second problem remains as a main obstacle to CMOS implementation. As a result, the feasibility of the CMOS implementation of ADCs for such applications, or other wide band applications, depends primarily on achieving a very small input capacitance (large bandwidth) at the desired accuracy. In the flash architecture, the input capacitance is traded off for the achievable accuracy. This tradeoff becomes tighter with technology scaling. An effective way to ease this tradeoff is to use resistive offset averaging. This permits the use of smaller area transistors, leading to a reduction in the ADC input capacitance. In addition, interpolation can be used to decrease the input capacitance of flash ADCs. In an interpolating architecture, the number of ADC input preamplifiers is reduced significantly, and a resistor network interpolates the missing zero-crossings needed for an N-bit conversion. The resistive network also averages out the preamplifiers offsets. Consequently, an interpolating network works also as an averaging network. The resistor network used for averaging or interpolation causes a systematic non-linearity at the ADC transfer characteristics edges. The common solution to this problem is to extend the preamplifiers array beyond the input signal voltage range by using dummy preamplifiers. However, this demands a corresponding extension of the flash ADC reference-voltage resistor ladder. Since the voltage headroom of the reference ladder is considered to be a main bottleneck in the implementation of flash ADCs in deep-submicron technologies with reduced supply voltage, extending the reference voltage beyond the input voltage range is highly undesirable. The principal objective of this thesis is to develop a new circuit technique to enhance the bandwidth-accuracy product of flash ADCs. Thus, first, a rigorous analysis of flash ADC architectures accuracy-bandwidth tradeoff is presented. It is demonstrated that the interpolating architecture achieves a superior accuracy compared to that of a full flash architecture for the same input capacitance, and hence would lead to a higher bandwidth-accuracy product, especially in deep-submicron technologies that use low power supplies. Also, the gain obtained, when interpolation is employed, is quantified. In addition, the limitations of a previous claim, which suggests that an interpolating architecture is equivalent to an averaging full flash architecture that trades off accuracy for the input capacitance, is presented. Secondly, a termination technique for the averaging/interpolation network of flash ADC preamplifiers is devised. The proposed technique maintains the linearity of the ADC at the transfer characteristics edges and cancels out the over-range voltage, consumed by the dummy preamplifiers. This makes flash ADCs more amenable for integration in deep-submicron CMOS technologies. In addition, the elimination of this over-range voltage allows a larger least-significant bit. As a result, a higher input referred offset is tolerated, and a significant reductions in the ADC input capacitance and power dissipation are achieved at the same accuracy. Unlike a previous solution, the proposed technique does not introduce negative transconductance at flash ADC preamplifiers array edges. As a result, the offset averaging technique can be used efficiently. To prove the resulting saving in the ADC input capacitance and power dissipation that is attained by the proposed termination technique, a 6-bit 1.6-GS/s flash ADC test chip is designed and implemented in 0.13-$\mu$m CMOS technology. The ADC consumes 180 mW from a 1.5-V supply and achieves a Signal-to-Noise-plus-Distortion Ratio (SNDR) of 34.5 dB and 30 dB at 50-MHz and 1450-MHz input signal frequency, respectively. The measured peak Integral-Non-Linearity (INL) and Differential-Non-Linearity (DNL) are 0.42 LSB and 0.49 LSB, respectively.

碩士<br>國立清華大學<br>工程與系統科學系<br>92<br>The paper presents a pipeline analog to digital converter (ADC) used for video applications. The 10-bit ADC has an input signal range of ±0.5 V with the resolution near 1 mV. Sampling rate is 100 MHz. To reach the high speed, low power conversion, ADC implemented with pipeline architecture. How to implement a high speed, high gain Opamp is the bottleneck of ADC design. The Opamp used gain boost and two-stage techniques. Gain boost circuit strengthen the DC gain of Opamp without reducing bandwidth. Two-stage can get wide input common mode range and wide output swing. Pipeline ADC can use this advantage to amplify the full-scale signal stage-by-stage and lower down the precision need stage-by-stage. This will help to save power consumption of pipeline ADC. With the aid of spice and matlab, the simulation DC performance of ADC claims no missing code, DNL within ±0.2 LSB, INL within ±0.5 LSB. The simulation AC performance of ADC claims SNDR are 60.6 dB@5 MHz and 50.2 dB@40 MHz. The total power dissipation of ADC is about 722 mW. The power reduction can be done using error tolerance of pipeline structure. It is predicted to reduce about 25% of power dissipation.

碩士<br>國立臺灣大學<br>電子工程學研究所<br>105<br>This thesis presents two analog and mixed-signal circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the experimental prototypes, the presented techniques are verified. The first technique is hybrid unit capacitors. Comparing to last work [1], the resolution bit has been enhanced by adding extra capacitor arrays with an additional smaller unit capacitor. This relevant prototype SAR ADC consumes 10.55μW at 1-V supply, and the effective number of bit (ENOB) is 10.827 bits. The resultant figure of merit (FoM) is 29.0 fJ/conversion-step by measurement results. The second technique is applying a sub-ranged SAR ADC. By adding a 5-bit sub-ranged SAR ADC to make a pre-decision of the first 5 bits, the switching power of system could be reduced by half. This relevant prototype SAR ADC consumes 3.683μW at 1-V supply, and the ENOB is 11.818 bits. The resultant FoM is 5.099 fJ/conversion-step by simulation results. Both of the prototypes are implemented in the 0.18μm 1P6M CMOS technology.

碩士<br>國立臺灣大學<br>電子工程學研究所<br>104<br>This thesis presents two analog and mixed-signal circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the experimental prototypes, the presented techniques are verified. The first technique is the layout schemes of a unit capacitor. Compared to last work [1], the surroundings of a unit capacitor is identical to each unit capacitor, which does not take process variation into consideration. This relevant prototype SAR ADC consumes 6.2μW at 1-V supply, and the effective number of bit (ENOB) is 9.47 bits. The resultant figure of merit (FoM) is 43.7 fJ/conversion-step. The second technique is a hybrid capacitor switching procedure. In order to suppress the effect of dynamic offset in the comparator, a capacitor switching procedure is proposed. This relevant prototype SAR ADC consumes 6.0μW at 1-V supply, and the ENOB is 9.51 bits. The resultant FoM is 41.1 fJ/conversion-step. Both of the prototypes are implemented in a 0.18μm 1P6M CMOS technology.

This thesis presents two hybrid luminescence-based biochemical photosensory microsystems: a CMOS/microfluidic chemiluminescence contact imager, and a CMOS/thin-film fluorescence contact imager. A compact, low-power analog-to-digital converter (ADC) architecture for use in such sensory microsystems is also proposed. Both microsystems are prototyped in a standard 0.35um CMOS technology. The CMOS/microfluidic microsystem integrates a 64x128-pixel CMOS imager and a soft polymer microfluidic network. Circuit techniques are employed to reduce the dark current and circuit noise for low-level light sensitivity. Experimental validation is performed by detecting luminol chemiluminescence and electrochemiluminescence. The CMOS/thin-film microsystem integrates an existing 128x128-pixel CMOS imager and a prefabricated, high-performance optical filter. Experimental validation is performed by detecting human DNA labeled with Cyanine-3 fluorescent dye. The proposed ADC architecture employs a novel digital-to-analog converter with a flexible trade-off between the integration area and the conversion speed. The area savings and good linearity of the DAC are verified by simulations.

博士<br>國立成功大學<br>電機工程學系碩博士班<br>101<br>This dissertation proposes several circuit design techniques for current-steering digital-to-analog converters (DACs) on wireless communication applications to lower the power consumption. Moreover, a compound current cell is also proposed to make current-steering DACs in a system-on-a-chip (SoC) have more functionality for reducing the integration challenges and cost. Hence, three proof-of-concept prototypes are presented to demonstrate these techniques. According to the measurement results of the prototypes, the proposed techniques have good power efficiency and the prototypes can meet wireless communication applications, especially on ultra-wideband (UWB) applications. The prototypes and chip measurement results are depicted as follows: The first one uses a “3 (thermometer)  2 (binary)” segmented structure for reaching a compromise between the circuit complexity and the differential nonlinearity (DNL) error. In addition, we employ bipolar current source cells in this prototype to cut the power consumption while maintaining the same output voltage swing. Moreover, a de-glitch latch is presented to reduce the clock feedthrough from the pass transistors. This prototype was implemented in a standard 0.18-m 1P6M CMOS technology with the active area of 0.19 mm2. The measured integral nonlinearity (INL) and DNL are less than 0.04 and 0.05 least significant bit (LSB), respectively. The measured spurious-free dynamic range (SFDR) is above 30 dB over the complete Nyquist band at the sampling frequency of 1.35 GHz. The power consumption of this DAC is 9.7 mW. The second prototype is a 6-bit 2.7-GS/s DAC. In this prototype, a “2 (thermometer)  4 (binary)” segmented architecture is chosen to make a compromise between the current source cell’s area and the operating speed of the thermometer decoder. In addition, the proposed pseudo-thermometer structure improves the DAC’s dynamic performance. The bipolar current source cell and latch clock delay technique are employed to reduce the power consumption in analog and digital parts, respectively. Moreover, the compact de-glitch latch simplifies the conventional latch design and layout. This DAC was implemented in a standard 0.13-m 1P8M CMOS technology with the active area of 0.0585 mm2. The measured DNL and INL are less than 0.09 and 0.11 LSB, respectively. The measured SFDR is more than 36 dB over the Nyquist frequency at the sampling frequency of 2.7 GHz. The DAC consumes 5.4 mW for a near-Nyquist sinusoidal output at 2.7 GS/s, resulting in a better figure of merit of 31 fJ/conversion-step. In the third one, a compound current cell, with the properties of N-type, P-type, and bipolar ones, is proposed and utilized in a current-steering DAC to satisfy the application of rail-to-rail voltage sources. Additionally, a DAC with the cells also has a high speed fashion. Therefore, the presented DAC with the cells meets both communication and rail-to-rail voltage-source applications. Moreover, the effective output voltage step size is improved by appropriately switching these cells and connecting one of gain control resisters, resulting in a about 6.4-mV step size in a 1.2-V supply. Furthermore, this DAC was implemented in a standard low-power 90-nm 1P9M CMOS technology with the active area of 0.045 mm2. The measured SFDR is more than 36 dB over the Nyquist frequency at 3 GS/s, and the DAC consumes 8.32 mW for a near-Nyquist sinusoidal output at the sampling rate of 3 GS/s.

碩士<br>國立臺灣大學<br>電子工程學研究所<br>102<br>Pipelined analog-to-digital converters (ADCs) and Successive-approximation register (SAR) analog-to-digital converters have been widely utilized in high speed communication system for mid to high resolution. This thesis proposes two circuit design techniques for analog-to-digital converters (ADCs), including pipelined ADC with hybrid calibration and successive-approximation register (SAR) ADC. According to the simulation and measurement results of the proof-of-concept prototypes, the proposed techniques are able to improve the operating speed. The proposed techniques and chip measurement results are sketched as follows: The first technique is a pipelined ADC with hybrid calibration, a high speed and low power 10-bit pipelined ADC with 200MS/s sampling clock. This technique can reduce 50% of original calibration time and cost less hardware in high order calibration without changing communication system to accomplish high resolution, low power, and high speed ADC. Moreover, 1.5-bit architecture is applied to achieve high speed and low power application. Besides, the calibration not only increases the resolution, but also lowers the op-amps requirements of the gain and bandwidth. A 10-bit, 200-MS/s pipelined ADC with the proposed calibration is implemented in a 90-nm 1P9M CMOS technology. According to the measuring results, with 1MHz input frequency, the ENOB and SFDR achieve 8.17 and 64.5dB at 10MS/s. The ENOB and SFDR are reduced to 7.46 and 46.7dB at 100MS/s with 1MHz input frequency. The ENOB and SFDR are reduced to 6.85 and 57.3dB at 100MS/s with 1MHz input frequency. The power consumption is 20.4mW at 200MS/s conversion rate. The second design of SAR ADC utilizes the two-bit per step architecture technique operating at 100MS/s in 90nm to make this design a high speed, low power, and small area ADC(without using excessive power.). As we know, the comparator only outputs high and low voltage, so we prepare these two voltages to choose beforehand. Therefore, we are able to decide two bit in one cycle but not one bit in conventional. Compared to converters that use the conventional architecture, the operating speed is increase by about 70%. But compared to time-interleaved SAR ADC, the total sampling capacitor could be reduced by 25%. A 9-bit, 100-MS/s SAR ADC with the proposed two-bit per step switching procedure is implemented in a 90-nm 1P9M CMOS technology. According to the measuring results with 20MHz input frequency, the ENOB and SFDR achieve 6.77 and 44.71dB at 50MS/s. The ENOB and SFDR are reduced to 6.05 and 45.86dB at 100MS/s with 10MHz input frequency. The power consumption is 2.4mW at 100MS/s conversion rate.

As high precision data acquisition systems continue to improve their performance and power efficiency to migrate into portable devices, increasing demands are placed on the performance and power efficiency of the analog-to-digital conversion modulator. On the other hand, analog-to-digital modulator performance is largely limited by several major noise sources including thermal noise, flicker noise, quantization noise leakage and internal analog and digital coupling noise. Large power consumption and die area are normally required to suppress the above noise energies, which are the major challenges to achieve power efficiency and cost targets for modern day high precision converter design. The main goal of this work is to study various approaches and then propose and validate the most suitable topology to achieve the desired performance and power efficiency specifications, up to 100 kHz bandwidth with 16-21 bits of resolution. This work will first study various analog-to-digital conversion architectures ranging from Nyquist converters such as flash, pipeline, to the delta sigma architecture. Advantages and limitations of each approach will be compared to develop the criteria for the optimal modulator architecture. Second, this work will study analog sub-circuit blocks such as opamp, comparator and reference voltage generator, to compare the advantages and limitations of various design approaches to develop the criteria for the optimal analog sub circuit design. Third, this work will study noise contributions from various sources such as thermal noise, flicker noise and coupling noise, to explore alternative power and die area efficient approaches to suppress the noise. Finally, a new topology will be proposed to meet all above criteria and adopt the new noise suppression concepts, and will be demonstrated to be the optimal approach. The main difference between this work from previous ones is that current work places emphasis on the integration of the modulator architecture design and analog sub-circuit block research efforts. A high performance stereo analog-to-digital modulator is designed based on the new approach and manufactured in silicon. The chip is measured in the lab and the measurement results reported in the dissertation.<br>text

Sensor interfaces are needed to communicate the measured real-world analog values to the base¬band digital processor. They are dominated by the presence of high accuracy, high resolution analog to digital converters (ADC) in the backend. On most occasions, sensing is limited to small range measurements and low-modulation sensors where the complete dynamic range of ADC is not utilized. Designing a subsystem that integrates the sensor and the interface circuit and that works with a low resolution ADC requiring a small die-area is a challenge. In this work, we present a CMOS based area efficient, integrated sensor interface for applications like capacitance, temperature and dielectric-constant measurement. In addition, potential applica-tions for this work are in Cognitive Radios, Software Defined Radios, Capacitance Sensors, and location monitoring. The key contributions in the thesis are: 1 High Sensitivity Frequency-domain CMOS Capacitance Interface: A frequency domain capacitance interface system is proposed for a femto-farad capacitance measurement. In this technique, a ring oscillator circuit is used to generate a change in time period, due to a change in the sensor capacitance. The time-period difference of two such oscillators is compared and is read-out using a phase frequency detector and a charge pump. The output voltage of the system, is proportional to the change in the input sensor capacitance. It exhibits a maximum sensitivity of 8.1 mV/fF across a 300 fF capacitance range. 2 Sensitivity Enhancement for capacitance sensor: The sensitivity of an oscillator-based differential capacitance sensor has been improved by proposing a novel frequency domain capacitance-to-voltage (FDC) measurement technique. The capacitance sensor interface system is fabricated in a 130-nm CMOS technology with an active area of 0.17mm2 . It exhibits a maximum sensitivity of 244.8 mV/fF and a measurement resolution of 13 aF in a 10-100 fF measurement range, with a 10 pF nominal sensor capacitance and an 8-bit ADC. 3 Frequency to Digital Converter for Time/Distance measurement: A new architecture for a Vernier-based frequency-to-digital converter (VFDC) for location monitoring is pre¬sented, in which, a time interval measurement is performed with a frequency domain approach. Location monitoring is a common problem for many mobile robotic applica¬tions covering various domains, such as industrial automation, manipulation in difficult areas, rescue operations, environment exploration and monitoring, smart environments and buildings, robotic home appliances, space exploration and probing. The proposed architecture employs a new injection-locked ring oscillator (ILR) as the clock source. The proposed ILR oscillator does not need complex calibration procedures, usually required by Phase Locked Loop (PLL) based oscillators in Vernier-based time-to-digital convert¬ers. It consumes 14.4 µW and 1.15 mW from 0.4 V and 1.2 V supplies, respectively. The proposed VFDC thus achieves a large detectable range, fine time resolution, small die size and low power consumption simultaneously. The measured time-difference error is less than 50 ps at 1.2 V, enabling a resolution of 3 mm/kHz frequency shift. 4 A bio-sensor array for dielectric constant measurement: A CMOS on-chip sensor is presented to measure the dielectric constant of organic chemicals. The dielectric constant of these chemicals is measured using the oscillation frequency shift of a current controlled os¬cillator (CCO) upon the change of the sensor capacitance when exposed to the liquid. The CCO is embedded in an open-loop frequency synthesizer to convert the frequency change into voltage, which can be digitized using an off-chip analog-to-digital converter. The dielectric constant is then estimated using a detection procedure including the calibration of the sensor. 5 Integrated Temperature Sensor for thermal management: An integrated analog temper¬ature sensor which operates with simple, low-cost one-point calibration is proposed. A frequency domain technique to measure the on-chip silicon surface temperature, was used to measure the effects of temperature on the stability of a frequency synthesizer. The temperature to voltage conversion is achieved in two steps i.e. temperature to frequency, followed by frequency to voltage conversion. The output voltage can be used to com¬pensate the temperature dependent errors in the high frequency circuits, thereby reduc¬ing the performance degradation due to thermal gradient. Furthermore, a temperature measurement-based on-chip self test technique to measure the 3 dB bandwidth and the central frequency of common radio frequency circuits, was developed. This technique shows promise in performing online monitoring and temperature compensation of RF circuits.