Relevant bibliographies by topics / Analog-to-digital converters – Testing

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Analog-to-digital converters – Testing'

Author: Grafiati
Published: 4 June 2021
Last updated: 4 February 2022

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Journal articles on the topic "Analog-to-digital converters – Testing"

1

Brandolini, A., and A. Gandelli. "Testing methodologies for analog-to-digital converters." IEEE Transactions on Instrumentation and Measurement 41, no. 5 (1992): 595–603. http://dx.doi.org/10.1109/19.177328.

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Geurkov, Vadim, and Lev Kirischian. "Concurrent Testing of Analog-to-Digital Converters." i-manager's Journal on Electronics Engineering 1, no. 1 (November 15, 2010): 8–14. http://dx.doi.org/10.26634/jele.1.1.1193.

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Boser, B. E., K. P. Karmann, H. Martin, and B. A. Wooley. "Simulating and testing oversampled analog-to-digital converters." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, no. 6 (June 1988): 668–74. http://dx.doi.org/10.1109/43.3206.

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Vargha, B., J. Schoukens, and Y. Rolain. "Static nonlinearity testing of digital-to-analog converters." IEEE Transactions on Instrumentation and Measurement 50, no. 5 (2001): 1283–88. http://dx.doi.org/10.1109/19.963198.

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Suresh Babu, B. N., and H. B. Wollman. "Transient and overvoltage recovery testing of analog-to-digital converters." IEEE Transactions on Instrumentation and Measurement 44, no. 1 (1995): 53–60. http://dx.doi.org/10.1109/19.368103.

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Michaeli, Linus, and Ján Šaliga. "Error Models of the Analog to Digital Converters." Measurement Science Review 14, no. 2 (April 1, 2014): 62–77. http://dx.doi.org/10.2478/msr-2014-0010.

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Abstract Error models of the Analog to Digital Converters describe metrological properties of the signal conversion from analog to digital domain in a concise form using few dominant error parameters. Knowledge of the error models allows the end user to provide fast testing in the crucial points of the full input signal range and to use identified error models for post correction in the digital domain. The imperfections of the internal ADC structure determine the error characteristics represented by the nonlinearities as a function of the output code. Progress in the microelectronics and missing information about circuital details together with the lack of knowledge about interfering effects caused by ADC installation prefers another modeling approach based on the input-output behavioral characterization by the input-output error box. Internal links in the ADC structure cause that the input-output error function could be described in a concise form by suitable function. Modeled functional parameters allow determining the integral error parameters of ADC. Paper is a survey of error models starting from the structural models for the most common architectures and their linkage with the behavioral models represented by the simple look up table or the functional description of nonlinear errors for the output codes.
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Lewis, S. H., R. Ramachandran, and W. M. Snelgrove. "Indirect testing of digital-correction circuits in analog-to-digital converters with redundancy." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 42, no. 7 (July 1995): 437–45. http://dx.doi.org/10.1109/82.401166.

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Awada, Emad A. "Hilbert Based Testing of ADC Differential Non-linearity Using Wavelet Transform Algorithms." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (December 1, 2018): 5071. http://dx.doi.org/10.11591/ijece.v8i6.pp5071-5079.

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In testing Mixed Signal Devices such as Analog to Digital and Digital to Analog Converters, some dynamic parameters, such as Differential Non-Linearity and Integral Non-linearity, are very critical to evaluating devises performance. However, such analysis has been notorious for complexity and massive compiling process. Therefore, this research will focus on testing dynamic parameters such as Differential Non-Linearity by simulating numerous numbers of bits Analog to Digital Converters and test the output signals base on new testing algorithms of Wavelet transform based on Hilbert process. Such a new testing algorithm should enhance the testing process by using less compiling data samples and prompt testing results. In addition, new testing results will be compared with the conventional testing process of Histogram algorithms for accuracy and enactment.
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Cherubal, S., and A. Chatterjee. "Optimal linearity testing of analog-to-digital converters using a linear model." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 50, no. 3 (March 2003): 317–27. http://dx.doi.org/10.1109/tcsi.2003.809775.

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Skup, Konrad, Paweł Grudziński, and Piotr Orleański. "Application of Digital Control Techniques for Satellite Medium Power DC-DC Converters." International Journal of Electronics and Telecommunications 57, no. 1 (March 1, 2011): 77–83. http://dx.doi.org/10.2478/v10177-011-0011-1.

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Application of Digital Control Techniques for Satellite Medium Power DC-DC Converters The objective of this paper is to present a work concerning a digital control loop system for satellite medium power DC-DC converters that is done in Space Research Centre. The whole control process of a described power converter is based on a high speed digital signal processing. The paper presents a development of a FPGA digital controller for voltage and current mode stabilization that was implemented using VHDL. The described controllers are based on a classical digital PID controller. The converter used for testing is a 200 kHz, 750W buck converter with 50V/15A output. A high resolution digital PWM approach is presented. Additionally a simple and effective solution of filtering of an analog-to-digital converter output is presented.
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Dissertations / Theses on the topic "Analog-to-digital converters – Testing"

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Kook, Se Hun. "Low-cost testing of high-precision analog-to-digital converters." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/41170.

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The advent of deep submicron technology has resulted in a new generation of highly integrated mixed-signal system-on-chips (SoCs) and system-on-packages (SoPs). As a result, the cost of electrical products has sharply declined, and their performance has greatly improved. However, a testing throughput still remains one of the major contribution factors to final cost of the electrical products. In addition, highly precise and robust test methods and equipment are needed to promise non-defective products to customers. Hence, the testing is a critical part of the manufacturing process in the semiconductor industry. Testing such highly integrated systems and devices requires high-performance and high-cost equipment. Analog-to-digital converters (A/D converters) are the largest volume mixed-signal circuits, and they play a key role in communication between the analog and digital domains in many mixed-signal systems. Due to the increasing complexity of the mixed-signal systems and the availability of the new generations of highly integrated systems, reliable and robust data conversion schemes are necessary for many mixed-signal designs. Many applications such as telecommunications, instrumentation, sensing, and data acquisition have demanded data converters that support ultra high-speed, wide-bandwidths, and high-precision with excellent dynamic performance and low-noise. However, as resolutions and speeds in the A/D converters increase, testing becomes much harder and more expensive. In this research work, low-cost test strategies to reduce overall test cost for high-precision A/D converters are developed. The testing of data converters can be classified as dynamic (or alternating current (AC)) performance test and static (or direct current (DC)) performance test [1]. In the dynamic specification test, a low-cost test stimulus is generated using an optimization algorithm to stimulate high-precision sigma-delta A/D converters under test. Dynamic specifications are accurately predicted in two different ways using concepts of an alternate-based test and a signature-based test. For this test purpose, the output pulse stream of a sigma-delta modulator is made observable and useful. This technique does not require spectrally pure input signals, so the test cost can be reduced compared to a conventional test method. In addition, two low-cost test strategies for static specification testing of high-resolution A/D converters are developed using a polynomial-fitting method. The cost of testing can be significantly reduced as a result of the measurement of fewer samples than a conventional histogram test. While one test strategy needs no expensive high-precision stimulus generator, which can reduce the test cost, the other test strategy finds the optimal set of test-measurement points for the maximum fault coverage, which can use minimum-code measurement as a production test solution. The theoretical concepts of the proposed test strategies are developed in software simulation and validated by hardware experiments using a commercially available A/D converter and designed converters on printed circuit board (PCB). This thesis provides low-cost test solutions for the high-resolution A/D converters.
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Merz, Paul V. "Development and testing of the digital control system for the Archytas Unmanned Air Vehicle." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1992. http://handle.dtic.mil/100.2/ADA261656.

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Harbour, Kenton Dean. "A data acquisition system with switched capacitor sample-and-hold." Thesis, Kansas State University, 1986. http://hdl.handle.net/2097/15269.

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Imam, Neena. "Analysis, design, and testing of semiconductor intersubband devices." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15664.

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Cox, Corry. "IMPLEMENTING A TACTICAL TELEMETRY STYSTEM FOR MULTIPLE LAUNCH ROCKET SYSTEM (MLRS) STOCKPILE RELIABILITY TESTING." International Foundation for Telemetering, 2004. http://hdl.handle.net/10150/604935.

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International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California
The Precision Fires Rocket and Missile Systems (PFRMS) Program Office continually undertakes Stockpile Reliability Testing (SRP) to ensure the validity of the accumulated weapons and increase the she lf life of these weapon systems. MLRS is a legacy weapon system that has been undergoing SRP testing for over 20 years. The PFRMS Program Office has a need for a miniature Tactical Telemetry System that will monitor the fuze performance of the MLRS Rocket during SRP testing. This paper will address a technical approach of how a small Tactical Telemetry System could be built to meet this requirement. The Tactical Telemetry system proposed in this paper will monitor fuze functions, operate across the wide environmental spectrum of the SRP tests, and physically fit in the nose area without altering the overall tactical rocket appearance or operation.
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Doerfler, Douglas Wayne. "Techniques for testing a 15-bit data acquisition system." 1985. http://hdl.handle.net/2097/27427.

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Sinha, Alok Kumar. "Some Novel Ideas For Static And Dynamic Testing Of High-Speed High Resolution ADCs." Thesis, 2005. http://etd.iisc.ernet.in/handle/2005/1561.

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Yoo, Jae Ki. "A background calibration technique and self testing method for the pipeline analog to digital converter." Thesis, 2004. http://hdl.handle.net/2152/1440.

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Wang, Bo 1970. "High-accuracy circuits for on-chip capacitor ratio testing and sensor readout." Thesis, 1998. http://hdl.handle.net/1957/33343.

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The precise measurement of a capacitance difference or ratio in a digital form is very important for capacitive sensors, for CMOS process characterization as well as for the realization of precise switched-capacitor data converters, amplifiers and other circuits utilizing ratioed capacitors. This thesis introduces design techniques for on-chip capacitor ratio testing and sensor readout that utilize sigma-delta modulation and integrate the sensor capacitors into the modulator. Several single-ended circuits are introduced, and the correlated-double-sampling (CDS) technique is used in the circuits to reduce the non-ideal effects of opamps. Several simple calibration schemes for clock-feedthrough cancellation are also introduced and discussed. A fully-differential implementation is also described and various common-mode feedback schemes are discussed and analyzed. Simulation and experimental results show that these circuits can provide extremely accurate results even in the presence of non-ideal circuit effects such as finite opamp gain, opamp input offset and noise, and clock-feedthrough effect from the switches. To verify the effectiveness of the circuits and simulations, two prototype chips containing a single-ended realization and a fully-differential one were designed and fabricated in a 1.2 ��m CMOS technology. Two off-chip mica capacitors were used in the test circuits, and the measured results show that very accurate results can be obtained using these circuit techniques even with off-chip noise coupling and large parasitic capacitances.
Graduation date: 1999
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Wei-ChunWang and 王瑋竣. "Automatic Testing System for Analog to Digital Converter." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/35386932772830055402.

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碩士
國立成功大學
電機工程學系專班
100
In this thesis, we developed an automated testing system for analog-to-digital converters (ADCs) by creating a program based on the ADC theory and the signal processing theory. This system can be used to automatically test the dynamic and static characteristics of the ADCs. The LabVIEWTM software is used as the develop environment and a logic analyzer to acquire the converted digital signals. The signals were then further calculated by using the signal processing functions in LabVIEWTM to provide the converter’s dynamic values such as signal-to-noise ratio (SNR), signal-to-noise and distortion ratio (SNDR), and effective number of bits (ENOB); and static values such as the differential non-linearity (DNL) and integral non-linearity (INL). The frequency distribution can also be obtained. A configuration file was used to feed test parameters such as operational frequency, dc offset, signal amplitude, and voltage of the converter to the program for sequential execution. The results were automatically saved as an ExcelTM report. Users can monitor the tests from a remote computer from internet by using the network control function. Automated testing can reduce manual testing times and limit possible operational errors to enhance test accuracy and report reliability.
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Books on the topic "Analog-to-digital converters – Testing"

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Merz, Paul V. Development and testing of the digital control system for the Archytas Unmanned Air Vehicle. Monterey, Calif: Naval Postgraduate School, 1992.

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Dufort, Benoit. Analog test signal generation using periodic [sigma delta]-encoded data streams. New York: Springer Science+Business Media, 2000.

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1959-, Roberts Gordon W., ed. Analog test signal generation using periodic [sigma delta]-encoded data streams. Boston: Kluwer Academic, 2000.

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(Editor), Dominique Dallet, and José Machado da Silva (Editor), eds. Dynamic Characterisation of Analogue-to-Digital Converters (The International Series in Engineering and Computer Science). Springer, 2005.

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IEEE Instrumentation and Measurement Society. Waveform Measurement and Analysis Technical Committee., Institute of Electrical and Electronics Engineers., IEEE Standards Board, and IEEE Standards Association, eds. IEEE standard for terminology and test methods for analog-to-digital converters. New York: Institute of Electrical and Electronics Engineers, 2001.

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Wang, Bo. High-accuracy circuits for on-chip capacitor ratio testing and sensor readout. 1998.

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Wang, Bo. High-accuracy circuits for on-chip capacitor ratio testing and sensor readout. 1998.

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S, Gerber Scott, and NASA Glenn Research Center, eds. Low temperature testing of a radiation hardened CMOS 8-bit flash analog-to-digital (A/D) converter. [Cleveland, Ohio]: National Aeronautics and Space Administration, Glenn Research Center, 2001.

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Roberts, G. W., and Benoit Dufort. Analog Test Signal Generation Using Periodic S-Encoded Data Streams (The Kluwer International Series in Engineering and Computer Science Volume 591) (The ... Series in Engineering and Computer Science). Springer, 2000.

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Book chapters on the topic "Analog-to-digital converters – Testing"

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Plassche, Rudy. "Testing of D/A and A/D converters." In Integrated Analog-To-Digital and Digital-To-Analog Converters, 79–106. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2748-0_3.

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Plassche, Rudy. "Testing of D/A and A/D converters." In CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 523–50. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3768-4_13.

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Zjajo, Amir, and José Pineda de Gyvez. "Multi-Step Analog to Digital Converter Testing." In Low-Power High-Resolution Analog to Digital Converters, 103–82. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9725-5_4.

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Balasubramanian, Sidharth, Vipul J. Patel, and Waleed Khalil. "Current and Emerging Trends in the Design of Digital-to-Analog Converters." In Design, Modeling and Testing of Data Converters, 83–118. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-39655-7_3.

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Kościelnik, Dariusz, and Marek Miśkowicz. "Event-Driven Successive Charge Redistribution Schemes for Clockless Analog-to-Digital Conversion." In Design, Modeling and Testing of Data Converters, 161–209. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-39655-7_6.

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Petri, Dario, Daniel Belega, and Dominique Dallet. "Dynamic Testing of Analog-to-Digital Converters by Means of the Sine-Fitting Algorithms." In Design, Modeling and Testing of Data Converters, 309–40. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-39655-7_10.

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Liu, Chaotao, and Shirong Yin. "Offset Modify in Histogram Testing of Analog-to-Digital Converter Based on Sine Wave." In Emerging Technologies for Information Systems, Computing, and Management, 497–504. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-7010-6_56.

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BAKER, MARK. "TESTING DIGITAL-TO-ANALOG CONVERTERS." In Demystifying Mixed Signal Test Methods, 177–206. Elsevier, 2003. http://dx.doi.org/10.1016/b978-075067616-8/50007-8.

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BAKER, MARK. "TESTING ANALOG-TO-DIGITAL CONVERTERS." In Demystifying Mixed Signal Test Methods, 207–37. Elsevier, 2003. http://dx.doi.org/10.1016/b978-075067616-8/50008-x.

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Onabajo, Marvin, Yong-Bin Kim, Yongsuk Choi, Hari Chauhan, Chun-hsiang Chang, and In-Seok Jung. "Digitally Assisted Performance Tuning of Analog/RF Circuits with an On-Chip FFT Engine." In Advances in Computer and Electrical Engineering, 236–67. IGI Global, 2015. http://dx.doi.org/10.4018/978-1-4666-6627-6.ch010.

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A serious drawback associated with systems-on-a-chip integration and CMOS technology scaling trends is the increasing susceptibility to manufacturing process variations and aging effects. Consequently, it is critical to improve on-chip measurement and self-calibration capabilities as well as the testability of single-chip systems. This chapter describes a robust design methodology for enhanced reliability of analog front-end circuits in mixed-signal chips. The system under development is comprised of small blocks close to high-frequency analog circuits under test to down-convert signals to low frequencies such that they can be routed to an on-chip analog-to-digital converter architecture for built-in testing applications. An efficient Fast Fourier Transform (FFT) engine is used to calculate the frequency spectrum of the signal with significantly less chip area compared to existing FFT engines. The self-contained system provides the measurement results in digital form to support digital calibration approaches, particularly those that involve digitally assisted analog blocks.
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Conference papers on the topic "Analog-to-digital converters – Testing"

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Geurkov, Vadim, and Lev Kirischian. "A Concurrent Testing Technique for Analog-to-Digital Converters." In 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW 2011). IEEE, 2011. http://dx.doi.org/10.1109/ims3tw.2011.20.

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Vasan, Bharath K., Degang J. Chen, and Randall L. Geiger. "Linearity testing of Analog-to-Digital Converters using imprecise sinusoidal excitations." In NAECON 2010 - IEEE National Aerospace and Electronics Conference. IEEE, 2010. http://dx.doi.org/10.1109/naecon.2010.5712973.

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Xu, Fang. "Signal Cancellation Technique for Testing High-end Digital-to-Analog Converters." In 2007 IEEE Instrumentation & Measurement Technology Conference IMTC 2007. IEEE, 2007. http://dx.doi.org/10.1109/imtc.2007.379447.

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Karakozov, A. B., P. V. Nekraso, D. V. Bobrovsky, G. S. Sorokoumov, and V. A. Telets. "Single Event Effects And Total Dose Testing Of Digital To Analog Converters." In 2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS). IEEE, 2017. http://dx.doi.org/10.1109/radecs.2017.8696263.

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Abbas, Mohamed, Yasuo Furukawa, Satoshi Komatsu, and Kunihiro Asada. "Signature-based testing for adaptive digitally-calibrated pipelined analog-to-digital converters." In 2009 IEEE 8th International Conference on ASIC (ASICON). IEEE, 2009. http://dx.doi.org/10.1109/asicon.2009.5351356.

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Xu, Li, and Degang Chen. "Accurate spectral testing of analog-to-digital converters with frequency drift using phase correction and averaging." In 2015 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2015. http://dx.doi.org/10.1109/iscas.2015.7169134.

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Howell, Max, and Bill Hartshorn. "Rapid Design, Integration and Test of Improved Digital Fuel Control for the LM2500 Gas Turbine Engine." In ASME 1995 International Gas Turbine and Aeroengine Congress and Exposition. American Society of Mechanical Engineers, 1995. http://dx.doi.org/10.1115/95-gt-353.

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This paper describes how Martin Marietta performed rapid design, integration, and test of a Digital Fuel Control (DFC) system for control of shipboard GE LM2500 Gas Turbine Engines. This phase was performed in Orlando, Florida and included real time hardware in the loop (HWTL) testing of the DFC with a simulated engine and test cell. With this approach, all of the DFC hardware and software could be validated before performing control of a real engine. Therefore risk was minimized and the schedule did not depend on availability of an LM2500 engine. The engine and test cell were simulated using the Integrated Systems, Inc. (ISI) AC100 Real Time Controller, which is easily transportable from site to site. The next phase will involve testing the DFC and AC100 with a real LM2500 engine and test cell. The AC100 incorporates parallel digital signal processing and various input/output (I/O) options such as analog to digital (A/D) converters, digital to analog (D/A) converters, logical inputs and outputs, resolver to digital converters, pulse width modulation output, etc. Programs and I/O connections are made using extensive software on a workstation which produces code which is downloaded to the AC100 via Ethernet The programs are developed using a user-friendly, menu-driven graphical language called System Build. An autocode generator converts the system model to C or Ada, which is compiled and downloaded to the AC100 for real time execution.
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Malandruccolo, V., M. Ciappa, W. Fichtner, and H. Rothleitner. "Novel built-in methodology for defect testing of capacitor oxide in SAR analog to digital converters for critical automotive applications." In 2010 15th IEEE European Test Symposium (ETS). IEEE, 2010. http://dx.doi.org/10.1109/etsym.2010.5512762.

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Hamed, S. M., A. H. Khalil, M. B. Abdelhalim, H. H. Amer, and A. H. Madian. "N-stage pipelined Digital to Analog converter testing." In 2012 13th Biennial Baltic Electronics Conference (BEC2012). IEEE, 2012. http://dx.doi.org/10.1109/bec.2012.6376827.

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Hamed, Sahar M., Ahmed H. Khalil, Hassanein H. Amer, M. B. Abdelhalim, and Ahmed H. Madian. "Testing of one stage Pipelined Analog to Digital Converter." In Systems (ICCES). IEEE, 2011. http://dx.doi.org/10.1109/icces.2011.6141040.

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