Dissertations / Theses on the topic 'Analog-to-digital converters – Testing'

The advent of deep submicron technology has resulted in a new generation of highly integrated mixed-signal system-on-chips (SoCs) and system-on-packages (SoPs). As a result, the cost of electrical products has sharply declined, and their performance has greatly improved. However, a testing throughput still remains one of the major contribution factors to final cost of the electrical products. In addition, highly precise and robust test methods and equipment are needed to promise non-defective products to customers. Hence, the testing is a critical part of the manufacturing process in the semiconductor industry. Testing such highly integrated systems and devices requires high-performance and high-cost equipment. Analog-to-digital converters (A/D converters) are the largest volume mixed-signal circuits, and they play a key role in communication between the analog and digital domains in many mixed-signal systems. Due to the increasing complexity of the mixed-signal systems and the availability of the new generations of highly integrated systems, reliable and robust data conversion schemes are necessary for many mixed-signal designs. Many applications such as telecommunications, instrumentation, sensing, and data acquisition have demanded data converters that support ultra high-speed, wide-bandwidths, and high-precision with excellent dynamic performance and low-noise. However, as resolutions and speeds in the A/D converters increase, testing becomes much harder and more expensive. In this research work, low-cost test strategies to reduce overall test cost for high-precision A/D converters are developed. The testing of data converters can be classified as dynamic (or alternating current (AC)) performance test and static (or direct current (DC)) performance test [1]. In the dynamic specification test, a low-cost test stimulus is generated using an optimization algorithm to stimulate high-precision sigma-delta A/D converters under test. Dynamic specifications are accurately predicted in two different ways using concepts of an alternate-based test and a signature-based test. For this test purpose, the output pulse stream of a sigma-delta modulator is made observable and useful. This technique does not require spectrally pure input signals, so the test cost can be reduced compared to a conventional test method. In addition, two low-cost test strategies for static specification testing of high-resolution A/D converters are developed using a polynomial-fitting method. The cost of testing can be significantly reduced as a result of the measurement of fewer samples than a conventional histogram test. While one test strategy needs no expensive high-precision stimulus generator, which can reduce the test cost, the other test strategy finds the optimal set of test-measurement points for the maximum fault coverage, which can use minimum-code measurement as a production test solution. The theoretical concepts of the proposed test strategies are developed in software simulation and validated by hardware experiments using a commercially available A/D converter and designed converters on printed circuit board (PCB). This thesis provides low-cost test solutions for the high-resolution A/D converters.

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California
The Precision Fires Rocket and Missile Systems (PFRMS) Program Office continually undertakes Stockpile Reliability Testing (SRP) to ensure the validity of the accumulated weapons and increase the she lf life of these weapon systems. MLRS is a legacy weapon system that has been undergoing SRP testing for over 20 years. The PFRMS Program Office has a need for a miniature Tactical Telemetry System that will monitor the fuze performance of the MLRS Rocket during SRP testing. This paper will address a technical approach of how a small Tactical Telemetry System could be built to meet this requirement. The Tactical Telemetry system proposed in this paper will monitor fuze functions, operate across the wide environmental spectrum of the SRP tests, and physically fit in the nose area without altering the overall tactical rocket appearance or operation.

The precise measurement of a capacitance difference or ratio in a digital form is very important for capacitive sensors, for CMOS process characterization as well as for the realization of precise switched-capacitor data converters, amplifiers and other circuits utilizing ratioed capacitors. This thesis introduces design techniques for on-chip capacitor ratio testing and sensor readout that utilize sigma-delta modulation and integrate the sensor capacitors into the modulator. Several single-ended circuits are introduced, and the correlated-double-sampling (CDS) technique is used in the circuits to reduce the non-ideal effects of opamps. Several simple calibration schemes for clock-feedthrough cancellation are also introduced and discussed. A fully-differential implementation is also described and various common-mode feedback schemes are discussed and analyzed. Simulation and experimental results show that these circuits can provide extremely accurate results even in the presence of non-ideal circuit effects such as finite opamp gain, opamp input offset and noise, and clock-feedthrough effect from the switches. To verify the effectiveness of the circuits and simulations, two prototype chips containing a single-ended realization and a fully-differential one were designed and fabricated in a 1.2 ��m CMOS technology. Two off-chip mica capacitors were used in the test circuits, and the measured results show that very accurate results can be obtained using these circuit techniques even with off-chip noise coupling and large parasitic capacitances.
Graduation date: 1999

碩士
國立成功大學
電機工程學系專班
100
In this thesis, we developed an automated testing system for analog-to-digital converters (ADCs) by creating a program based on the ADC theory and the signal processing theory. This system can be used to automatically test the dynamic and static characteristics of the ADCs. The LabVIEWTM software is used as the develop environment and a logic analyzer to acquire the converted digital signals. The signals were then further calculated by using the signal processing functions in LabVIEWTM to provide the converter’s dynamic values such as signal-to-noise ratio (SNR), signal-to-noise and distortion ratio (SNDR), and effective number of bits (ENOB); and static values such as the differential non-linearity (DNL) and integral non-linearity (INL). The frequency distribution can also be obtained. A configuration file was used to feed test parameters such as operational frequency, dc offset, signal amplitude, and voltage of the converter to the program for sequential execution. The results were automatically saved as an ExcelTM report. Users can monitor the tests from a remote computer from internet by using the network control function. Automated testing can reduce manual testing times and limit possible operational errors to enhance test accuracy and report reliability.

碩士
國立暨南國際大學
電機工程學系
92
In this thesis, a DAC testing scheme and a 12-bit calibrated DAC are proposed. The DNL and INL of the CUT (Circuit under Test) can be obtained by fewer test patterns in the proposed DAC testing scheme. An experimental 8-bit Dual resistor ladder DAC implemented in a 0.35-mm CMOS technology demonstrates that the maximum DNL and INL are 0.07LSB and 0.48LSB, respectively, for whole test patterns, and are 0.07LSB and 0.46LSB, respectively, for 31 test patterns. The experimental results verify the proposed scheme. The proposed 12-bit DAC is not calibrated every cycle as the conventional circuits but calibrated before the normal operation. This will improve the operation speed. The simulated results show that the proposed 12-bit DAC can operate under 50MHz.

碩士
國立臺灣大學
電子工程學研究所
95
The digital to analog converter (DAC) is a key component in signal processing and telecommunication applications. One major design challenge is to achieve high static and dynamic linearity in the existence of inevitable process variations, e.g., the systematic Vth gradient across the wafer or the random device mismatch. Various layout techniques have been developed to enhance the achievable resolution by canceling out the process variation gradient. However, both the required large current source array and the complex routing introduce parasitic capacitance that poses negative impact on the dynamic performance. Furthermore, the final resolution is not predictable during the design phase and could just try-and-error to tune-up the resolution to meet the specification. Calibration techniques that intend to enhance the DAC resolution have been reported. Some works require an extra built-in high resolution converter (DAC or ADC) as the embedded tester and thus may not be suitable for some applications. Trimming technique use an operation amplifier (OpAmp) and a reference current source used to continuously charge a capacitor that stores the bias voltage of each current source in background. However, the differences between the OpAmp offset voltages may result in large current mismatch. Fuse array is utilized to adjust the DAC INL during the final test. While guaranteeing the final resolution, it requires large area overhead for the fuse array and an accurate external tester, which raises the test cost. The proposed DAC self-testing and self-calibration technique aims at reducing the induced area overhead and the required design efforts. In our technique, the lower significant bits are duplicated. Together with an analog comparator, this duplicated sub-DAC supports both self-testing and self-calibration. A prototype 14-bit DAC has been designed and fabricated in TSMC 0.35 µm technology. The results show that the proposed technique is able to greatly improve the DAC’s static and dynamic performance with low area overhead and shortened design routine.

碩士
國立交通大學
電子研究所
81
The thesis deals with the design with the design and testing of the CMOS over-sampling Digital-to-Analog converter. For the audio applications, a new fourth-order sigma-delta modulator with simulated result of 95 dB SNR is proposed. The new high- order one-bit modulator removing the real-time feedback loops relaxes the speed requirement of the adders and the multipliers. Two experimental approaches of the reconstruction filter is described. One approach is the con- ventional switched-capacitor filter with chopper stabilized op-amps, the other is the current-mode semi-digital FIR filter. A digital tester especially for the testing of the oversampling converters has been developed successfully. The tester contains two blocks of 256K words memory and can achieve the 20 MHz clock rate, which meets the requirement of the testing of the oversampling converters.

碩士
國立高雄應用科技大學
電子工程系碩士班
103
This thesis reports a nonlinearity testing technique for a top plane sampling successive-approximation analog-to-digital converter, and verify this nonlinearity testing technique with a 10-bit 1-MS/s successive-approximation analog-to-digital converter. In this design, we proposed two architecture.One is offset error cancellation technique based-on the cost of the hardware and considered the correction of the cancellation to cancel the offset error,another is capacitance-ratio quantification technique to measure the nonlinearity error for the capacitor mismatch, the nonlinearity error are differential nonlinearity and Integral nonlinearity, respectively.