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Journal articles on the topic 'Analog-to-digital convertors'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Yoshimura, Atushi. "New differential linearity compensation method for successive approximation analog-to-digital convertors." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 274, no. 3 (January 1989): 536–40. http://dx.doi.org/10.1016/0168-9002(89)90187-3.

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2

Yang, Bin, Yan Chang Wang, Pei Hong Li, and Ji Lin Liu. "HDR CCD Image Sensor System through Double-A/D Convertors." Applied Mechanics and Materials 66-68 (July 2011): 2241–47. http://dx.doi.org/10.4028/www.scientific.net/amm.66-68.2241.

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In this paper we present a CCD image sensor system with high dynamic range. This feature is achieved through double analog-to-digital convertors’(ADC) architecture and field programmable gate arrays(FPGA). By doing so, the system outputs high dynamic range images in real time. The proposed scheme is a low-cost solution in the sense that it can be built on top of any traditional sensor system with minor modifications on the system-level analog-to-digital module. Through the post-layout sensor system we show the experimental images to demonstrate the effectiveness.

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3

Miralaie, Mostafa, and Ali Mir. "Evaluation of Room-Temperature Performance of Ultra-Small Single-Electron Transistor-Based Analog-to-Digital Convertors." Journal of Circuits, Systems and Computers 27, no. 14 (August 23, 2018): 1850217. http://dx.doi.org/10.1142/s0218126618502171.

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In this paper, in order to analyze the performance of single-electron transistor (SET)-based analog-to-digital converter (ADC) circuits at room temperature, first, the quantum Coulomb blockade regime is explained and based on it we calculate and discuss the inherent Coulomb oscillation characteristics of room-temperature-operating SETs (or, in other words, ultra-small SETs). Then, to explain the performance of SET-based ADC structures, we explore the sensitivity of converter section of these structures to the inherent periodic oscillation characteristics. By simulating two different temperatures of 100[Formula: see text]K and 300[Formula: see text]K, we demonstrate that for proper performance of converter section of the SET-based ADCs, SETs must have inherent Coulomb oscillations with the same and high peak-to-valley current ratio (PVCR) and equal Coulomb peak spacing (i.e., equal [Formula: see text]. The Coulomb oscillation characteristics of the room-temperature-operating silicon SET show the Coulomb oscillations with unequal PVCRs and unequal Coulomb peak spacings (i.e., unequal [Formula: see text]. As a result, it can be seen that the room-temperature-operating SET-based ADCs never have a suitable output.

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4

Aminzadeh, Hamed, Mohammad Ali Dashti, and Mohammad Miralaei. "Nano-Scale Silicon Quantum Dot-Based Single-Electron Transistors and Their Application to Design of Analog-to-Digital Convertors at Room Temperature." Journal of Circuits, Systems and Computers 26, no. 12 (August 2017): 1750201. http://dx.doi.org/10.1142/s0218126617502012.

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Room-temperature analog-to-digital converters (ADCs) based on nanoscale silicon (Si) quantum dot (QD)-based single-electron transistors (SETs) can be very attractive for high-speed processors embedded in future generation nanosystems. This paper focuses on the design and modeling of advanced single-electron converters suited for operation at room temperature. In contrast to conventional SETs with metallic QD, the use of sub-10-nm Si QD results in stable operation at room temperature, as the observable Coulomb blockade regime covers effectively the higher temperature range. Si QD-based SETs are also fully compatible with advanced CMOS technology and they can be manufactured using routine nanofabrication steps. At first, we present the principles of operation of Si SETs used for room-temperature operation. Possible flash-type ADC architectures are then investigated and the design considerations of possible Coulomb oscillation regimes are addressed. A modified design procedure is then introduced for [Formula: see text]-bit SET-based ADCs, and validated through simulation of a 3-bit ADC with a sampling frequency of 5 GS/s. The ADC core is comprised from a capacitive signal divider followed by three periodic symmetric functions (PSFs). Simulation results demonstrate the stability of output signals at the room-temperature range.

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5

Volodin, A. D., A. L. Efimenko, A. V. Gorlin, and D. A. Kuzmin. "Signal Synchronization, Collection and Transmission for Multichannel Distribution Seismic Antenna." Journal of the Russian Universities. Radioelectronics, no. 1 (April 17, 2018): 25–31. http://dx.doi.org/10.32603/1993-8985-2018-21-1-25-31.

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Creation of seismic antennas involves production of a system capable to provide synchronous analog-to- digital data signal conversion of all channels and to broadcast digitized signals to the central computing complex (CCC). The article considers a structure of data transmission system from a big number of sources for application in seismic antennas. Moreover, it provides possible ways of preprocessing equipment (PE) unit arrangement in separate hermetic blocks to facilitate their replacement. Besides, the options for PE unit structural and functional schemes are offered. Application of specific chips is explained. The review of the most widespread types of digital convertors is given and the optimal one is chosen for application in hydro acoustic complexes. The option of synchronization with the use of phase-locked loop PLL units is offered. Configuration of data transmission system with the use of Ethernet switchboard setting optimal data transmission protocol is considered.

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6

Yang Wang, Yang Wang, Hongming Zhang Hongming Zhang, Yujie Dou Yujie Dou, and Minyu Yao Minyu Yao. "Experimental evaluation of resolution enhancement of a phase-shifted all optical analog-to-digital converter using an electrical analog-to-digital converter array." Chinese Optics Letters 11, no. 8 (2013): 082301–82303. http://dx.doi.org/10.3788/col201311.082301.

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7

Pandya, Priyesh, and Vikas Gupta. "Enhancing Analog to Digital Converter Resolution Using Oversampling Technique." International Journal of Engineering Research 3, no. 4 (April 1, 2014): 245–48. http://dx.doi.org/10.17950/ijer/v3s4/413.

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8

Melikyan, V. Sh, V. D. Hovhannisyan, M. T. Grigoryan, A. A. Avetisyan, and H. T. Grigoryan. "Real Number Modeling Flow of Digital to Analog Converter." Proceedings of Universities. Electronics 26, no. 2 (April 2021): 144–53. http://dx.doi.org/10.24151/1561-5405-2021-26-2-144-153.

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This work introduces a flow of digital to analog (DAC) implementation in digital environment of SystemVerilog. Unlike the classical Verilog models, this digital to analog converter behavioral model is analog. Such type of model creation in general is called real number modeling. The DAC model is verified by the HSPICE and SystemVerilog Co-simulations which show its applicability in different register transfer level verification environments. The digital environment with real number modeled DAC runs around 8 times faster than the same environment with SPICE model. At the same time, the output signal’s voltage difference between RNM and SPICE models is less than 2 mV.

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9

Delouis, J. M., L. Pagano, S. Mottet, J. L. Puget, and L. Vibert. "SRoll2: an improved mapmaking approach to reduce large-scale systematic effects in the Planck High Frequency Instrument legacy maps." Astronomy & Astrophysics 629 (September 2019): A38. http://dx.doi.org/10.1051/0004-6361/201834882.

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This paper describes an improved map making approach with respect to the one used for the Planck High Frequency Instrument 2018 Legacy release. The algorithm SRoll2 better corrects the known instrumental effects that still affected mostly the polarized large-angular-scale data by distorting the signal, and/or leaving residuals observable in null tests. The main systematic effect is the nonlinear response of the onboard analog-to-digital convertors that was cleaned in the Planck HFI Legacy release as an empirical time-varying linear detector chain response which is the first-order effect. The SRoll2 method fits the model parameters for higher-order effects and corrects the full distortion of the signal. The model parameters are fitted using the redundancies in the data by iteratively comparing the data and a model. The polarization efficiency uncertainties and associated errors have also been corrected based on the redundancies in the data and their residual levels characterized with simulations. This paper demonstrates the effectiveness of the method using end-to-end simulations, and provides a measure of the systematic effect residuals that now fall well below the detector noise level. Finally, this paper describes and characterizes the resulting SRoll2 frequency maps using the associated simulations that are released to the community.

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10

Li, Jiamin, Qian Lv, Jing Yang, Pengcheng Zhu, and Xiaohu You. "Spectral and Energy Efficiency of Distributed Massive MIMO with Low-Resolution ADC." Electronics 7, no. 12 (December 4, 2018): 391. http://dx.doi.org/10.3390/electronics7120391.

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In this paper, considering a more realistic case where the low-resolution analog-to-digital convertors (ADCs) are employed at receiver antennas, we investigate the spectral and energy efficiency in multi-cell multi-user distributed massive multi-input multi-output (MIMO) systems with two linear receivers. An additive quantization noise model is provided first to study the effects of quantization noise. Using the model provided, the closed-form expressions for the uplink achievable rates with a zero-forcing (ZF) receiver and a maximum ratio combination (MRC) receiver under quantization noise and pilot contamination are derived. Furthermore, the asymptotic achievable rates are also given when the number of quantization bits, the per user transmit power, and the number of antennas per remote antenna unit (RAU) go to infinity, respectively. Numerical results prove that the theoretical analysis is accurate and show that quantization noise degrades the performance in spectral efficiency, but the growth in the number of antennas can compensate for the degradation. Furthermore, low-resolution ADCs with 3 or 4 bits outperform perfect ADCs in energy efficiency. Numerical results imply that it is preferable to use low-resolution ADCs in distributed massive MIMO systems.

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11

Hayashi, Satoshi, Ryo Suzuki, Takamoto Watanabe, Shigenori Yamauchi, Nobuyuki Taguchi, Sumio Masuda, and Takehiko Adachi. "Proposal of a Method to Improve Linearity of Time Analog to Digital Converter." IEEJ Transactions on Electronics, Information and Systems 135, no. 1 (2015): 35–36. http://dx.doi.org/10.1541/ieejeiss.135.35.

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12

Guang Yang, Guang Yang, Weiwen Zou Weiwen Zou, Ye Yuan Ye Yuan, and Jianping Chen Jianping Chen. "Wideband signal detection based on high-speed photonic analog-to-digital converter." Chinese Optics Letters 16, no. 3 (2018): 030601. http://dx.doi.org/10.3788/col201816.030601.

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13

Wang, Yanyi, Kaihui Wang, Wen Zhou, and Jianjun Yu. "Photonic aided vector millimeter-wave signal generation without digital-to-analog converter." Chinese Optics Letters 19, no. 1 (2021): 011101. http://dx.doi.org/10.3788/col202119.011101.

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14

Suszynski, R., and K. Wawryn. "Rapid prototyping of algorithmic A/D converters based on FPAA devices." Bulletin of the Polish Academy of Sciences: Technical Sciences 61, no. 3 (September 1, 2013): 691–96. http://dx.doi.org/10.2478/bpasts-2013-0073.

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Abstract A rapid prototyping method for designing mixed signal systems has been presented in the paper. The method is based on implementation of the field programmable analog array (FPAA) to configure and reconfigure mixed signal systems. A serial algorithmic analog digital converter has been used as an example. Three converter architectures have been selected and implemented FPAA device. To verify and illustrate converters operation and prototyping capabilities, implemented converters have been excited by a sinusoidal signal. Analog sinusoidal excitations, digital responses and sinusoidal waveforms after reconstruction are presented.

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15

Yang Wang, Yang Wang, Yujie Dou Yujie Dou, and Hongming Zhang Hongming Zhang. "Experimental demonstration of 5-bit phase-shifted all-optical analog-to-digital converter." Chinese Optics Letters 11, no. 4 (2013): 042301–42302. http://dx.doi.org/10.3788/col201311.042301.

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16

Bin Le, T. W. Rondeau, J. H. Reed, and C. W. Bostian. "Analog-to-digital converters." IEEE Signal Processing Magazine 22, no. 6 (November 2005): 69–77. http://dx.doi.org/10.1109/msp.2005.1550190.

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17

Harris, M. S. "Integrated analog-to-digital and digital-to-analog converters." Microelectronics Journal 25, no. 5 (August 1994): 405–6. http://dx.doi.org/10.1016/0026-2692(94)90096-5.

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18

Grechishnikov, V. M., and E. G. Komarov. "Increasing the information capacity of a fiber-optic multi-sensor converter of binary mechanical signals into electrical signals." Izmeritel`naya Tekhnika, no. 9 (2020): 15–23. http://dx.doi.org/10.32446/0368-1025it.2020-9-15-23.

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The design and operation principle of a multi-sensor Converter of binary mechanical signals into electrical signals based on a partitioned fiber-optic digital-to-analog Converter with a parallel structure is considered. The digital-to-analog Converter is made from a set of simple and technological (three to five digit) fiber-optic digital-to-analog sections. The advantages of the optical scheme of the proposed. Converter in terms of metrological and energy characteristics in comparison with single multi-bit converters are justified. It is shown that by increasing the number of digital-analog sections, it is possible to repeatedly increase the information capacity of a multi-sensor Converter without tightening the requirements for its manufacturing technology and element base. A mathematical model of the proposed Converter is developed that reflects the features of its operation in the mode of sequential time conversion of the input code vectors of individual fiber-optic sections into electrical analogues and the formation of the resulting output code vector.

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19

Lukić, Jelena, and Dragan Denić. "A Novel Design Of An NTC Thermistor Linearization Circuit." Metrology and Measurement Systems 22, no. 3 (September 1, 2015): 351–62. http://dx.doi.org/10.1515/mms-2015-0035.

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Abstract A novel design of a circuit used for NTC thermistor linearization is proposed. The novelty of the proposed design consists in a specific combination of two linearization circuits, a serial-parallel resistive voltage divider and a two-stage piecewise linear analog-to-digital converter. At the output of the first linearization circuit the quasi-linear voltage is obtained. To remove the residual voltage nonlinearity, the second linearization circuit, i.e., a two-stage piecewise linear analog-to-digital converter is employed. This circuit is composed of two flash analog-to-digital converters. The first analog-to-digital converter is piecewise linear and it is actually performing the linearization, while the second analog-to-digital converter is linear and it is performing the reduction of the quantization error introduced by the first converter. After the linearization is performed, the maximal absolute value of a difference between the measured and real temperatures is 0.014°C for the temperature range between −25 and 75°C, and 0.001°C for the temperature range between 10 and 40°C.

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20

Quenzer-Hohmuth, Samuel, Thoralf Rosahl, Steffen Ritzmann, and Bernhard Wicht. "Challenges and implementation aspects of switched-mode power supplies with digital control for automotive applications." Advances in Radio Science 14 (September 28, 2016): 85–90. http://dx.doi.org/10.5194/ars-14-85-2016.

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Abstract. Switched-mode power supplies (SMPS) convert an input DC-voltage into a higher or lower output voltage. In automotive, analog control is mostly used in order to keep the required output voltages constant and resistant to disturbances. The design of robust analog control for SMPS faces parameter variations of integrated and external passive components. Using digital control, parameter variations can be eliminated and the required area for the integrated circuit can be reduced at the same time. Digital control design bears challenges like the prevention of limit cycle oscillations and controller-wind-up. This paper reviews how to prevent these effects. Digital control loops introduce new sources for dead times in the control loop, for example the latency of the analog-to-digital-converter (ADC). Dead times have negative influence on the stability of the control loop, because they lead to phase delays. Consequently, low latency is one of the key requirements for analog-to-digital-converters in digitally controlled SMPS. Exploiting the example of a 500 kHz-buck converter with a crossover frequency of 70 kHz, this paper shows that the 5 µs-latency of a ΔΣ-analog-to-digital-converter leads to a reduction in phase margin of 126°. The latency is less critical for boost converters because of their inherent lower crossover frequencies. Finally, the paper shows a comparison between analog and digital control of SMPS with regard to chip area and test costs.

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21

Fan Yang, Fan Yang, Weiwen Zou Weiwen Zou, Lei Yu Lei Yu, Shaofu Xu Shaofu Xu, and Jianping Chen Jianping Chen. "Impact of optical–electrical conversion responsivity in sub-sampled photonic analog-to-digital converter." Chinese Optics Letters 17, no. 4 (2019): 040602. http://dx.doi.org/10.3788/col201917.040602.

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22

Skup, Konrad, Paweł Grudziński, and Piotr Orleański. "Application of Digital Control Techniques for Satellite Medium Power DC-DC Converters." International Journal of Electronics and Telecommunications 57, no. 1 (March 1, 2011): 77–83. http://dx.doi.org/10.2478/v10177-011-0011-1.

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Application of Digital Control Techniques for Satellite Medium Power DC-DC Converters The objective of this paper is to present a work concerning a digital control loop system for satellite medium power DC-DC converters that is done in Space Research Centre. The whole control process of a described power converter is based on a high speed digital signal processing. The paper presents a development of a FPGA digital controller for voltage and current mode stabilization that was implemented using VHDL. The described controllers are based on a classical digital PID controller. The converter used for testing is a 200 kHz, 750W buck converter with 50V/15A output. A high resolution digital PWM approach is presented. Additionally a simple and effective solution of filtering of an analog-to-digital converter output is presented.

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23

Kelly, Brandon M., Alexander T. DiLello, and David W. Graham. "Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion." Journal of Low Power Electronics and Applications 9, no. 3 (August 12, 2019): 25. http://dx.doi.org/10.3390/jlpea9030025.

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Wearable medical devices, wireless sensor networks, and other energy-constrained sensing devices are often concerned with finding specific data within more-complex signals while maintaining low power consumption. Traditional analog-to-digital converters (ADCs) can capture the sensor information at a high resolution to enable a subsequent digital system to process for the desired data. However, traditional ADCs can be inefficient for applications that only require specific points of data. This work offers an alternative path to lower the energy expenditure in the quantization stage—asynchronous content-dependent sampling. This asynchronous sampling scheme is achieved by pairing a flexible analog front-end with an asynchronous successive-approximation ADC and a time-to-digital converter. The versatility and reprogrammability of this system allows a multitude of event-driven, asynchronous, or even purely data-driven quantization methods to be implemented for a variety of different applications. The system, fabricated in standard 0.5 μ m and 0.35 μ m processes, is demonstrated along with example applications with voice, EMG, and ECG signals.

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24

Bojja Venkatakrishnan, Satheesh, Elias A. Alwan, and John L. Volakis. "Challenges in Clock Synchronization for On-Site Coding Digital Beamformer." International Journal of Reconfigurable Computing 2017 (2017): 1–8. http://dx.doi.org/10.1155/2017/7802735.

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Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.

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25

Valley, George C. "Photonic analog-to-digital converters." Optics Express 15, no. 5 (2007): 1955. http://dx.doi.org/10.1364/oe.15.001955.

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26

Mukhanov, O. A., D. Gupta, A. M. Kadin, and V. K. Semenov. "Superconductor analog-to-digital converters." Proceedings of the IEEE 92, no. 10 (October 2004): 1564–84. http://dx.doi.org/10.1109/jproc.2004.833660.

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27

Kroics, Kaspars. "Digital Control of Variable Frequency Interleaved DC-DC Converter." Environment. Technology. Resources. Proceedings of the International Scientific and Practical Conference 2 (August 8, 2015): 124. http://dx.doi.org/10.17770/etr2013vol2.854.

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This paper represents a design and implementation of a digital control of variable frequency interleaved DC-DC converter using a digital signal processor (DSP). The digital PWM generation, current and voltage sensing, user interface and the new period and pulse width value calculation with DSP STM32F407VGT6 are considered. Typically, the multiphase interleaved DC - DC converters require a current control loop in each phase to avoid imbalanced current between phases. This increases system costs and control complexity. In this paper the converter which operates in discontinuous conduction mode is designed in order to reduce costs and remove the current control loop in each phase. High current ripples associated with this mode operation are then alleviated by interleaving. Pulse width modulation (PWM) is one of the most conventional modulation techniques for switching DC - DC converters. It compares the error signal with the sawtooth wave to generate the control pulse. This paper shows how six PWM signals phase-shifted by 60 degrees can be generated from calculated values. To ensure that the measured values do not contain disturbances and in order to improve the system stability the digital signal is filtered. The analog to digital converter's (ADC) sampling time must not coincide with the power transistor's switching time, therefore the sampling time must be calculated correctly as well. Digital control of the DC-DC converter makes it easy and quickly to configure. It is possible for this device to communicate with other devices in a simple way, to realize data input by using buttons and keyboard, and to display information on LED, LCD displays, etc.

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28

Jovanović, Jelena, and Dragan Denić. "A Cost-effective Method for Resolution Increase of the Twostage Piecewise Linear ADC Used for Sensor Linearization." Measurement Science Review 16, no. 1 (February 1, 2016): 28–34. http://dx.doi.org/10.1515/msr-2016-0005.

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Abstract A cost-effective method for resolution increase of a two-stage piecewise linear analog-to-digital converter used for sensor linearization is proposed in this paper. In both conversion stages flash analog-to-digital converters are employed. Resolution increase by one bit per conversion stage is performed by introducing one additional comparator in front of each of two flash analog-to-digital converters, while the converters’ resolutions remain the same. As a result, the number of employed comparators, as well as the circuit complexity and the power consumption originating from employed comparators are for almost 50 % lower in comparison to the same parameters referring to the linearization circuit of the conventional design and of the same resolution. Since the number of employed comparators is significantly reduced according to the proposed method, special modifications of the linearization circuit are needed in order to properly adjust reference voltages of employed comparators.

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29

Gogna, Pawan, Murali Lingalugari, John Chandy, Evan Heller, and Faquir Jain. "Fast Digital to Analog Convertor using Spatial Wave Switched FETs." International Journal of High Speed Electronics and Systems 23, no. 01n02 (March 2014): 1450002. http://dx.doi.org/10.1142/s0129156414500025.

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In this paper, we are presenting fast digital to analog convertor designs using Spatial Waveform Switched FETs (SWSFET). SWSFET was introduced by Jain et.al. These FETs have multiple channels stacked vertically. The Carrier wavefunction switches from one channel to another with the application of different gate voltages. Designs of multi-bit SRAM, logic and sequential cells using SWSFETs have been demonstrated. Here we are introducing the use of SWSFET in mixed signal architectures. Single cycle architectures for two-bit, four-bit and eight-bit analog to digital converters are presented. Four bit architecture has been simulated and results are discussed. SWSFET presents the opportunity with its multiple stacked channel features to extend the Moors law using next generation of devices.

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30

Shih, C., and P. R. Gray. "Reference refreshing cyclic analog-to-digital and digital-to-analog converters." IEEE Journal of Solid-State Circuits 21, no. 4 (August 1986): 544–54. http://dx.doi.org/10.1109/jssc.1986.1052570.

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31

Gaude, Disha, Bathini Poornima, Sudharshan K. M., and Prashant V. Joshi. "Design and Simulation of 4-Bit Flash Analog to Digital Converter (ADC) for High Speed Applications." Indian Journal of Science and Technology 12, no. 36 (September 20, 2019): 1–7. http://dx.doi.org/10.17485/ijst/2019/v12i36/148021.

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32

Lei Yu, Lei Yu, Weiwen Zou Weiwen Zou, Guang Yang Guang Yang, Xinwan Li Xinwan Li, and Jianping Chen Jianping Chen. "Switching response of dual-output Mach–Zehnder modulator in channel-interleaved photonic analog-to-digital converter." Chinese Optics Letters 16, no. 12 (2018): 120602. http://dx.doi.org/10.3788/col201816.120602.

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33

Hae-Seung Lee and C. G. Sodini. "Analog-to-Digital Converters: Digitizing the Analog World." Proceedings of the IEEE 96, no. 2 (February 2008): 323–34. http://dx.doi.org/10.1109/jproc.2007.911069.

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34

Brown, D. R., and D. C. Randall. "Microprocessor-based analysis of sympathetic nerve traffic." American Journal of Physiology-Regulatory, Integrative and Comparative Physiology 257, no. 4 (October 1, 1989): R958—R963. http://dx.doi.org/10.1152/ajpregu.1989.257.4.r958.

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Two systems based on microcomputers with analog-to-digital (A/D) converters were developed to measure sympathetic nerve activity. The first utilized a relatively inexpensive computer and A/D converter and an analog technique to count nerve traffic "spikes" above a reference voltage. The second system, which required a more expensive microcomputer and A/D converter, used digital methods exclusively to count spikes and integrate nerve activity. These systems produced accurate and reliable indexes of nerve traffic. The digital system could also be used to store the nerve signal to magnetic disk, thereby allowing the later use of more complex analytical procedures and the possibility of comparing the results of different analyses performed upon a single data set.

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35

Pratte, Jean-François, Frédéric Nolet, Samuel Parent, Frédéric Vachon, Nicolas Roy, Tommy Rossignol, Keven Deslandes, Henri Dautet, Réjean Fontaine, and Serge A. Charlebois. "3D Photon-To-Digital Converter for Radiation Instrumentation: Motivation and Future Works." Sensors 21, no. 2 (January 16, 2021): 598. http://dx.doi.org/10.3390/s21020598.

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Analog and digital SiPMs have revolutionized the field of radiation instrumentation by replacing both avalanche photodiodes and photomultiplier tubes in many applications. However, multiple applications require greater performance than the current SiPMs are capable of, for example timing resolution for time-of-flight positron emission tomography and time-of-flight computed tomography, and mitigation of the large output capacitance of SiPM array for large-scale time projection chambers for liquid argon and liquid xenon experiments. In this contribution, the case will be made that 3D photon-to-digital converters, also known as 3D digital SiPMs, have a potentially superior performance over analog and 2D digital SiPMs. A review of 3D photon-to-digital converters is presented along with various applications where they can make a difference, such as time-of-flight medical imaging systems and low-background experiments in noble liquids. Finally, a review of the key design choices that must be made to obtain an optimized 3D photon-to-digital converter for radiation instrumentation, more specifically the single-photon avalanche diode array, the CMOS technology, the quenching circuit, the time-to-digital converter, the digital signal processing and the system level integration, are discussed in detail.

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36

Watson, Jeff, and Maithil Pachchigar. "A Low Power, Precision SAR Analog to Digital Converter for High Temperature Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000053–57. http://dx.doi.org/10.4071/hitec-ta26.

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A growing number of industries are calling for low power electronics that operate reliably at temperatures of 175°C and higher. Many of these applications require a precision data acquisition signal chain in order to digitize analog data so that it can be collected and processed. Designing circuits that meet these needs can be very challenging, requiring a data converter that can deliver high performance and reliability in these harsh environments. There are currently a very limited number of integrated circuits commercially available that are specified for operation at these temperatures, and no low power precision data converters with sample rates greater than 100kSPS. This paper presents a new 210°C rated precision analog to digital converter capable of sample rates up to 600 kSPS with 16 bit resolution while maintaining low power consumption and packaged in a small form factor. We will explore the converter architecture of this ADC, present initial test results, and show how high reliability is achieved through qualification and advanced packaging techniques.

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37

Borisyuk, L. A., and S. U. Klimovich. "Logarithmic analog-to-digital converter." Measurement Techniques 32, no. 5 (May 1989): 398–401. http://dx.doi.org/10.1007/bf00866209.

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38

Groshev, V. Ya. "Functional analog-to-digital converter." Measurement Techniques 31, no. 6 (June 1988): 533–36. http://dx.doi.org/10.1007/bf00867520.

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39

Elgreatly, Ahmed, Ahmed Dessouki, Hassan Mostafa, Rania Abdalla, and El-sayed El-Rabaie. "A Novel Highly Linear Voltage-To-Time Converter (VTC) Circuit for Time-Based Analog-To-Digital Converters (ADC) Using Body Biasing." Electronics 9, no. 12 (December 1, 2020): 2033. http://dx.doi.org/10.3390/electronics9122033.

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Time-based analog-to-digital converter is considered a crucial part in the design of software-defined radio receivers for its higher performance than other analog-to-digital converters in terms of operation speed, input dynamic range and power consumption. In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These novel converters exhibit better linearity, which is analytically proven in this paper. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800 mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology. These novel designs consist of only a single inverter stage, which results in reducing the layout area and the power consumption. The overall power consumption is 18 μW for the first proposed circuit and 15 μW for the second proposed circuit. The novel converter circuits have a resolution of 5 bits and operate at a maximum clock frequency of 500 MHz.

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40

GHARBIYA, AHMED, TREVOR C. CALDWELL, and D. A. JOHNS. "HIGH-SPEED OVERSAMPLING ANALOG-TO-DIGITAL CONVERTERS." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 297–317. http://dx.doi.org/10.1142/s0129156405003211.

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This paper is mainly tutorial in nature and discusses architectures for oversampling converters with a particular emphasis on those which are well suited for high frequency input signal bandwidths. The first part of the paper looks at various architectures for discrete-time modulators and looks at their performance when attempting high speed operation. The second part of this paper presents some recent advancements in time-interleaved oversampling converters. The next section describes the design and challenges in continuous-time modulators. Finally, conclusions are made and a brief summary of the recent state of the art of high-speed converters is presented.

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41

Juodawlkis, P. W., J. C. Twichell, G. E. Betts, J. J. Hargreaves, R. D. Younger, J. L. Wasserman, F. J. O'Donnell, K. G. Ray, and R. C. Williamson. "Optically sampled analog-to-digital converters." IEEE Transactions on Microwave Theory and Techniques 49, no. 10 (2001): 1840–53. http://dx.doi.org/10.1109/22.954797.

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42

Dent, A. C., and C. F. N. Cowan. "Linearization of analog-to-digital converters." IEEE Transactions on Circuits and Systems 37, no. 6 (June 1990): 729–37. http://dx.doi.org/10.1109/31.55031.

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Zhu, Donglin, Maliang Liu, and Zhangming Zhu. "A High Energy Efficiency and Low Common-Mode Voltage Variation Switching Scheme for SAR ADCs." Journal of Circuits, Systems and Computers 27, no. 01 (August 23, 2017): 1850010. http://dx.doi.org/10.1142/s021812661850010x.

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In this paper, a high energy saving digital-to-analog converter (DAC) switching scheme with common-mode voltage variation in 1LSB is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). Based on the third reference ([Formula: see text]), split-capacitor technique and complementary switching method, the proposed switching scheme achieves a 99.6% switching energy reduction and a 75% area reduction compared to the conventional architecture, furthermore, the common-mode voltage varies only 1LSB during a conversion cycle.

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Zheng, Kangjia, Weiwen Zou, Lei Yu, Na Qian, and Jianping Chen. "Stability optimization of channel-interleaved photonic analog-to-digital converter by extracting of dual-output photonic demultiplexing." Chinese Optics Letters 18, no. 1 (2020): 012502. http://dx.doi.org/10.3788/col202018.012502.

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45

Bialek, J., A. Wickmann, F. Ohnhaeuser, G. Fischer, R. Weigel, and T. Ussmueller. "Implementation of a digital trim scheme for SAR ADCs." Advances in Radio Science 11 (July 4, 2013): 227–30. http://dx.doi.org/10.5194/ars-11-227-2013.

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Abstract. Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.

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Polunin, M. N., and A. V. Bykova. "Review of analog-to-information converters." Issues of radio electronics, no. 8 (August 7, 2019): 6–12. http://dx.doi.org/10.21778/2218-5453-2019-8-6-12.

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The implementation of high‑throughput systems with the traditional approach to the discretization of the analog signal according to the Kotelnikov theorem is faced with the problems of high power consumption and the need to store and transfer large amounts of data. An alternative approach to sampling and processing information is based on advances in the compressed sampling theory. The paper provides a brief overview of the main provisions of this theory and considers examples of its use in practice for the implementation of information reading systems – analog‑to‑information converters. The purpose of these devices is to reduce the pressure on conventional analog‑to‑digital converters, to reduce the sampling rate and the amount of output data. The main architectures of analog‑information converters are considered: non‑uniform sampling, random filter, random demodulator, modulated wideband converter, compressive multiplexer, random modulator pre‑integrator, spread spectrum random modulator pre‑integrator.

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Ramakrishna, P., and K. Hari Kishore. "Design of low power 10GS/s 6-Bit DAC using CMOS technology." International Journal of Engineering & Technology 7, no. 1.5 (December 31, 2017): 226. http://dx.doi.org/10.14419/ijet.v7i1.5.9151.

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A Low power 6-bit R-2R ladder Digital to Analog Converter is presented in this paper. Here the R-2 R network designed using resistors with only two values-R and 2xRand the switch is designed by using both NMOS and PMOS Transistors. This Digital to Analog Converters operated with low voltage, by applying dynamic threshold MOSFET (DTMOS) logic. This design achieved less INL and DNL which is 0.3 and 0.06 respectively. Power supply required to operate this device is only 1V with10GHzconversion rate. This design is implemented by using 0.18μm CMOS technology.

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Wang, Bao Sheng, Chen Yao Liu, and Kuo Bin Liu. "The Fully Digital Controlled Corrector Magnet Power Converter with a Shunt as a Current Sensing Component." Applied Mechanics and Materials 548-549 (April 2014): 730–35. http://dx.doi.org/10.4028/www.scientific.net/amm.548-549.730.

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In Taiwan light source (TLS), Bira’s MCOR30 power converter modules are adopted as the corrector magnet power converters, the output is regulated by analog PWM IC that caused nonlinear behavior at zero cross and the adjustment of compensator for different kind of magnet load is inconvenient. To fulfill digital regulation control, the analog regulation IC of Bira’s MCOR30 is replaced by a fully digital regulation control circuit. With plugging the homemade fully digital regulation control card into MCOR30 that the current sensing component is a shunt that save cost of the power converter, the switching losses and output current ripple were reduced and stability of output current is improved. With the fully digital regulation control circuit, the parameters of the compensator for different magnet load are very easy to adjust. In addition, the feasibility and validity of MOSFET switching algorism is simulated with MATLAB Simulink and the performance of this power converter is verified, the output current ripple of this power converter could be within 10ppm, which is beyond the requirement of current TLS corrector power converter and qualified to be used in the future TPS facility.

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Huajie Zhang, Huajie Zhang, Weiwen Zou Weiwen Zou, Guang Yang Guang Yang, and and Jianping Chen and Jianping Chen. "Dual-output modulation in time-wavelength interleaved photonic analog-to-digital converter based on actively mode-locked laser." Chinese Optics Letters 14, no. 3 (2016): 030602–30606. http://dx.doi.org/10.3788/col201614.030602.

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Yadav, Nandakishor, Youngbae Kim, Mahmoud Alashi, and Kyuwon Ken Choi. "Sensitive, Linear, Robust Current-To-Time Converter Circuit for Vehicle Automation Application." Electronics 9, no. 3 (March 16, 2020): 490. http://dx.doi.org/10.3390/electronics9030490.

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Voltage-to-time and current-to-time converters have been used in many recent works as a voltage-to-digital converter for artificial intelligence applications. In general, most of the previous designs use the current-starved technique or a capacitor-based delay unit, which is non-linear, expensive, and requires a large area. In this paper, we propose a highly linear current-to-digital converter. An optimization method is also proposed to generate the optimal converter design containing the smallest number of PMOS and sensitive circuits such as a differential amplifier. This enabled our design to be more stable and robust toward negative bias temperature instability (NBTI) and process variation. The proposed converter circuit implements the point-wise conversion from current-to-time, and it can be used directly for a variety of applications, such as analog-to-digital converters (ADC), used in built-in computational random access (C-RAM) memory. The conversion gain of the proposed circuit is 3.86 ms/A, which is 52 times greater than the conversion gains of state-of-the-art designs. Further, various time-to-digital converter (TDC) circuits are reviewed for the proposed current-to-time converter, and we recommend one circuit for a complete ADC design.

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