Academic literature on the topic 'Analogue electronics'

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Journal articles on the topic "Analogue electronics"

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Brown, O. R. "Analogue electronics." Electrochimica Acta 38, no. 4 (March 1993): 626. http://dx.doi.org/10.1016/0013-4686(93)85024-s.

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Bourzac, Katherine. "Electronics: Back to analogue." Nature 483, no. 7389 (March 2012): S34—S36. http://dx.doi.org/10.1038/483s34a.

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Polyushkin, Dmitry K., Stefan Wachter, Lukas Mennel, Matthias Paur, Maksym Paliy, Giuseppe Iannaccone, Gianluca Fiori, Daniel Neumaier, Barbara Canto, and Thomas Mueller. "Analogue two-dimensional semiconductor electronics." Nature Electronics 3, no. 8 (August 2020): 486–91. http://dx.doi.org/10.1038/s41928-020-0460-6.

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Wilson, Brett. "Book Review: Introduction to Analogue Electronics." International Journal of Electrical Engineering & Education 35, no. 1 (January 1998): 88. http://dx.doi.org/10.1177/002072099803500109.

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Heys, J. D. "Book Review: Analogue and Digital Electronics." International Journal of Electrical Engineering & Education 35, no. 3 (July 1998): 279–80. http://dx.doi.org/10.1177/002072099803500311.

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Price, T. E. "Computer Assisted Learning in An Electronics Course." International Journal of Electrical Engineering & Education 29, no. 3 (July 1992): 212–23. http://dx.doi.org/10.1177/002072099202900303.

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Computer assisted learning in an electronics course The CAD software package Electronic Workbench has been used for computer assisted learning for analogue electronics in the second year of a degree course. After a description of the package, the approach used to generate text files to describe the subject matter for transistor biasing, small signal analysis and frequency response is described. The student response is considered, as are the problems encountered in using the package for CAL.
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Simpson, Robert J. "Book Review: Analogue Electronics for Higher Studies." International Journal of Electrical Engineering & Education 33, no. 2 (April 1996): 184–85. http://dx.doi.org/10.1177/002072099603300212.

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Shaw, Brian M. "Book Review: The Essence of Analogue Electronics." International Journal of Electrical Engineering & Education 35, no. 1 (January 1998): 87. http://dx.doi.org/10.1177/002072099803500108.

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Winkler, D. "Superconducting analogue electronics for research and industry." Superconductor Science and Technology 16, no. 12 (November 13, 2003): 1583–90. http://dx.doi.org/10.1088/0953-2048/16/12/056.

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Hart, B. L. "Book Review: Analogue and Digital Electronics for Engineers." International Journal of Electrical Engineering Education 22, no. 3 (September 1985): 285. http://dx.doi.org/10.1177/002072098502200330.

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Dissertations / Theses on the topic "Analogue electronics"

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Berdan, Radu. "Applications of memristors in conventional analogue electronics." Thesis, Imperial College London, 2016. http://hdl.handle.net/10044/1/43370.

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This dissertation presents the steps employed to activate and utilise analogue memristive devices in conventional analogue circuits and beyond. TiO2 memristors are mainly utilised in this study, and their large variability in operation in between similar devices is identified. A specialised memristor characterisation instrument is designed and built to mitigate this issue and to allow access to large numbers of devices at a time. Its performance is quantified against linear resistors, crossbars of linear resistors, stand-alone memristive elements and crossbars of memristors. This platform allows for a wide range of different pulsing algorithms to be applied on individual devices, or on crossbars of memristive elements, and is used throughout this dissertation. Different ways of achieving analogue resistive switching from any device state are presented. Results of these are used to devise a state-of-art biasing parameter finder which automatically extracts pulsing parameters that induce repeatable analogue resistive switching. IV measurements taken during analogue resistive switching are then utilised to model the internal atomic structure of two devices, via fittings by the Simmons tunnelling barrier model. These reveal that voltage pulses modulate a nano-tunnelling gap along a conical shape. Further retention measurements are performed which reveal that under certain conditions, TiO2 memristors become volatile at short time scales. This volatile behaviour is then implemented into a novel SPICE volatile memristor model. These characterisation methods of solid-state devices allowed for inclusion of TiO2 memristors in practical electronic circuits. Firstly, in the context of large analogue resistive crossbars, a crosspoint reading method is analysed and improved via a 3-step technique. Its scaling performance is then quantified via SPICE simulations. Next, the observed volatile dynamics of memristors are exploited in two separate sequence detectors, with applications in neuromorphic engineering. Finally, the memristor as a programmable resistive weight is exploited to synthesise a memristive programmable gain amplifier and a practical memristive automatic gain control circuit.
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McEwan, Alistair. "Direct digital synthesis by analogue interpolation." Thesis, University of Oxford, 2004. http://ora.ox.ac.uk/objects/uuid:3def187d-5172-463c-9498-55898782f663.

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An improvement in efficiency of direct digital frequency synthesis (DDFS) systems is demanded for low power frequency synthesis in wireless communications. Concurrently a reduction in cost is important for disposable, low resolution frequency synthesis in biomedical instrumentation systems. To meet both these needs a new ROM-less architecture is presented here that uses less than half the circuit area of previous state of the art systems and improves the efficiency by operating at up to a tenth of the power consumption. The main contribution presented in this thesis is a novel, efficient method of interpolation for DDFS that uses the nonlinear response of the CMOS differential switch already present in the high speed current steering DAC. The nonlinear response provides a smooth transition between the conventional, quantised DAC output. This interpolation may be performed with the conventionally discarded phase bits leading to highly compact and efficient DDFS architectures for application in instrumentation and communications systems. DDFS systems typically consist of a large overflowing accumulator to generate the phase, a ROM lookup table to convert the phase to amplitude and a DAC to perform the digital to analogue conversion. Approximations are often used to reduce the size of the ROM, however the most efficient DDFS systems remove the ROM completely and calculate the phase to amplitude conversion directly or store the conversion in a non-linear DAC. State of the art, high speed CMOS DACs consisting of thermometer decoded arrays of current steering cells are often used to reduce non-ideal effects that cause unwanted transients leading to a degradation in spectral purity (SFDR). A novel ROM-less technique is introduced here that uses the non-linear response of a current cell consisting of an ideal current source and differential current switch to interpolate between the output levels of a non-linear DAC. Using this technique two architectures are developed. A compact architecture using only four or six current cells suitable for instrumentation applications and a thermometer decoded architecture using 64 current cells for communications applications that require better spectral purity. The compact architecture is 100% efficient as all the bias current is used to form the output. The only additional component is a small linear phase DAC. One compact system with a nonlinear DAC of four current cells achieved an SFDR of -40dBc up to output frequencies of 1MHz for dielectrophoresis consumed only 5μW/MHz and a second compact system with a six cell nonlinear DAC for electrical impedance spectroscopy, achieved an SFDR of -48dBc for output frequencies up to 1MHz and consumed only 8μW/MHz. As an extension to improve the SFDR a segmented system with 64 current cells was developed. The larger number of current cells required the use of a modified thermometer decoder that had the added benefit of improving the spectral purity by linearising the response of each cell. The total active area was 0.6mm2, less than half of state of the art ROM-less DDFS systems that include a DAC. Although measurement results of the 64 cell system were disappointing, simulations suggest that these problems may be solved in a future chip that should be able to achieve -70dBc SFDR at 100MHz. Despite the loss in performance from simulation to measurement, the measured 64 cell system still meets the spectral purity requirements of UMTS and Bluetooth, -60dBc SFDR.
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Sapargaliyev, Yerbol. "Automatic design of analogue circuits." Thesis, Brunel University, 2011. http://bura.brunel.ac.uk/handle/2438/6323.

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Evolvable Hardware (EHW) is a promising area in electronics today. Evolutionary Algorithms (EA), together with a circuit simulation tool or real hardware, automatically designs a circuit for a given problem. The circuits evolved may have unconventional designs and be less dependent on the personal knowledge of a designer. Nowadays, EA are represented by Genetic Algorithms (GA), Genetic Programming (GP) and Evolutionary Strategy (ES). While GA is definitely the most popular tool, GP has rapidly developed in recent years and is notable by its outstanding results. However, to date the use of ES for analogue circuit synthesis has been limited to a few applications. This work is devoted to exploring the potential of ES to create novel analogue designs. The narrative of the thesis starts with a framework of an ES-based system generating simple circuits, such as low pass filters. Then it continues with a step-by-step progression to increasingly sophisticated designs that require additional strength from the system. Finally, it describes the modernization of the system using novel techniques that enable the synthesis of complex multi-pin circuits that are newly evolved. It has been discovered that ES has strong power to synthesize analogue circuits. The circuits evolved in the first part of the thesis exceed similar results made previously using other techniques in a component economy, in the better functioning of the evolved circuits and in the computing power spent to reach the results. The target circuits for evolution in the second half are chosen by the author to challenge the capability of the developed system. By functioning, they do not belong to the conventional analogue domain but to applications that are usually adopted by digital circuits. To solve the design tasks, the system has been gradually developed to support the ability of evolving increasingly complex circuits. As a final result, a state-of-the-art ES-based system has been developed that possesses a novel mutation paradigm, with an ability to create, store and reuse substructures, to adapt the mutation, selection parameters and population size, utilize automatic incremental evolution and use the power of parallel computing. It has been discovered that with the ability to synthesis the most up-to-date multi-pin complex analogue circuits that have ever been automatically synthesized before, the system is capable of synthesizing circuits that are problematic for conventional design with application domains that lay beyond the conventional application domain for analogue circuits.
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Parish, Simon James. "Behavioural synthesis of analogue integrated circuits." Thesis, University of Birmingham, 2010. http://etheses.bham.ac.uk//id/eprint/549/.

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Automatic synthesis of analogue circuits remains a very manually intensive task despite huge strides in the field of Electronic Design Automation (EDA) in recent decades. Genetic Algorithms (GAs) are biologically inspired search algorithms which have previously shown some promise in this field. Their ability to form the basis of a practically useful synthesis system is investigated. A GA-based experimental synthesis system is implemented, which employs a Genetic Programming (GP) style encoding scheme based on tree structures, and a novel fitness function based on pole-zero analysis. The system is capable of synthesising circuit topologies entirely from scratch, but can also utilise user-provided circuit knowledge of arbitrary detail and complexity. The system uses a SPICE-based circuit simulator as a circuit evaluator. Experimental results reveal a number of issues that adversely impact the ability of GAs to reliably synthesise practically useful analogue circuits. These include considerable resource requirements and a tendency for synthesised circuits to contain an unnecessarily large number of components. Most serious is the sensitivity of analogue circuits to changes in topology and/or sizing. GAs are shown to be currently ill-suited to the problem domain of analogue circuit synthesis. The problem of SPICE non-convergence on the GA is also considered.
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Collins, Steven John. "A radio frequency capacitive discharge digital to analogue converter." Thesis, University of Glasgow, 2012. http://theses.gla.ac.uk/3371/.

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As the communications revolution continues there is an ever increasing demand for integrated transmitters and receivers on silicon in devices such as mobile phones and networking products. The demand to integrate complete systems onto a single die has driven a need to minimise the area of transmitters which has led to research into combining digital to analogue converters and RF mixers to minimise their area. The drive for increasing speeds and smaller transistors has resulted in higher capacitance densities and lower operating voltages, the latter making it more difficult to implement conventional transmitter circuits. Therefore there is a need for passive transmitter systems that maximise the output power to the load by minimising the voltage overhead on the output signal. This thesis proposes and demonstrates that it is possible to use a digital to analogue converter that performs RF up conversion using direct capacitive discharge to the load, which takes advantage of the large capacitance densities of a modern 40nm CMOS process. The DAC uses charge sharing in a similar manner to a charge sharing DAC without the bandwidth limitations imposed by an output amplifier. The RF frequency up conversion at the DAC data clock rate is produced using two DACs that differentially output the complement of each other on different halves of the clock cycle (one outputting while the other is charging) thereby emulating a passive switched mixer. The thesis shows that an 8 bit capacitive discharge DAC of 0.16mm2 can output 3dBm into a 50Ω load at 2.15GHz using a clock rate of 2GHz with MTPR of greater than 30dBc.
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Craven, Michael P. "Inter-chip communications in an analogue neural network utilising frequency division multiplexing." Thesis, University of Nottingham, 1994. http://eprints.nottingham.ac.uk/13085/.

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As advances have been made in semiconductor processing technology, the number of transistors on a chip has increased out of step with the number of input/output pins, which has introduced a communications ’bottle-neck’ in the design of computer architectures. This is a major issue in the hardware design of parallel structures implemented in either digital or analogue VLSI, and is particularly relevant to the design of neural networks which need to be highly interconnected. This work reviews hardware implementations of neural networks, with an emphasis on analogue implementations, and proposes a new method for overcoming connectivity constraints, by the use of Frequency Division Multiplexing (FDM) for the inter-chip communications. In this FDM scheme, multiple analogue signals are transmitted between chips on a single wire by modulating them at different frequencies. The main theoretical work examines the number of signals which can be packed into an FDM channel, depending on the quality factors of the filters used for the demultiplexing, and a fractional overlap parameter which was defined to take into account the inevitable overlapping of filter frequency responses. It is seen that by increasing the amount of permissible overlap, it is possible to communicate a larger number of signals in a given bandwidth. Alternatively, the quality factors of the filters can be reduced, which is advantageous for hardware implementation. Therefore, it was found necessary to determine the amount of overlap which might be permissible in a neural network implementation utilising FDM communications. A software simulator is described, which was designed to test the effects of overlap on Multilayer Perceptron neural networks. Results are presented for networks trained with the backpropagation algorithm, and with the alternative weight perturbation algorithm. These were carried out using both floating point and quantised weights to examine the combined effects of overlap and weight quantisation. It is shown using examples of classification problems, that the neural network learning is indeed highly tolerent to overlap, such that the effect on performance (i.e. on convergence or generalisation) is negligible for fractional overlaps of up to 30%, and some tolerence is achieved for higher overlaps, before failure eventually occurs. The results of the simulations are followed up by a closer examination of the mechanism of network failure. The last section of the thesis investigates the VLSI implementation of the FDM scheme, and proposes the use of the operational transconductance amplifier (OTA) as a building block for implementation of the FDM circuitry in analogue VLSI. A full custom VLSI design of an OTA is presented, which was designed and fabricated through Eurochip, using HSPICE/Mentor Graphics CAD tools and the Mietec 2.4µ CMOS process. A VLSI architecture for inter-chip FDM is also proposed, using adaptive tuning of the OTA-C filters and oscillators.This forms the basis for a program of further work towards the VLSI realisation of inter-chip FDM, which is outlined in the conclusions chapter.
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Feng, Hong. "Impact of atomistic device variability on analogue circuit design." Thesis, University of Glasgow, 2011. http://theses.gla.ac.uk/3074/.

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Scaling of complementary metal-oxide-semiconductor (CMOS) technology has benefited the semiconductor industry for almost half a century. For CMOS devices with a physical gate-length in the sub-100 nm range, extreme device variability is introduced and has become a major stumbling block for next generation analogue circuit design. Both opportunities and challenges have therefore confronted analogue circuit designers. Small geometry device can enable high-speed analogue circuit designs, such as data conversion interfaces that can work in the radio frequency range. These designs can be co-integrated with digital systems to achieve low cost, high-performance, single-chip solutions that could only be achieved using multi-chip solutions in the past. However, analogue circuit designs are extremely vulnerable to device mismatch, since a large number of symmetric transistor pairs and circuit cells are required. The increase in device variability from sub-100 nm processes has therefore significantly reduced the production yield of the conventional designs. Mismatch models have been developed to analytically evaluate the magnitude of random variations. Based on measurements from custom designed test structures, the statistics of process variation can be estimated using design related parameters. However, existing models can no longer accurately estimate the magnitude of mismatch for sub-100 nm “atomistic” devices, since short-channel effects have become important. In this thesis, a new mismatch model for small geometry devices will be proposed to address this problem. Based on knowledge of the matching performance obtained from the mismatch model, design solutions are desired at different design levels for a variety of circuit topologies. In this thesis, transistor level compensation solutions have been investigated and closed-loop compensation circuits have been proposed. At circuit level, a latch-based comparator has been used to develop a compensation solution because this type of comparator is extremely sensitive to the device mismatch. These comparators are also used as the fundamental building block for the analogue-to-digital converters (ADC). The proposed comparator compensation scheme is used to improve the performance of a high-speed flash ADC.
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Tanhaei, Ghazal. "A power-scalable variable-length analogue DFT processor for multi-standard wireless transceivers." Thesis, University of Birmingham, 2016. http://etheses.bham.ac.uk//id/eprint/7072/.

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In the Orthogonal Frequency-Division Multiplexing (OFDM) based transceivers, digital computation of the Discrete Fourier Transform (DFT) is a power hungry process. Reduction in the hardware cost and power consumption is possible by implementing the DFT processor with analogue circuits. This thesis presents the real-time recursive DFT processor. Previously, changing the transform length and scaling the power could only be performed by digital Fast Fourier Transform (FFT) processors. By using the real-time recursive DFT processor, the decimation filter is eliminated. Thus, further reduction in the hardware cost and power consumption of the multi-standard transceiver is achieved. The real-time recursive DFT processor was designed in 180 nm CMOS technology. Results of device mismatch analysis indicate that the 8-point recursive DFT processor has a yield of 97.5% for the BPSK modulated signal. For the QPSK modulated signal, however, yield of the 8-point recursive DFT processor is 8.9%. Moreover, doubling the transform length reduces the average dynamic range by 3dB. Accordingly, the 16-point recursive DFT processor has a yield of 43.4% for the BPSK modulated signal. Power consumption of the recursive DFT processor is about 1/6 of the power consumption of a previous analogue FFT processor.
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Heima, Mohamed Mohamed. "The design of active-R and active-RC sinusoidal oscillators." Thesis, Manchester Metropolitan University, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.337186.

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Hertel, Thorsten W. "Pulse radiation from an insulated antenna : an analogue of Cherenkov radiation from a moving charge." Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/15752.

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Books on the topic "Analogue electronics"

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Analogue electronics. London: E. Arnold, 1991.

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Analogue electronics. 2nd ed. London: Arnold, 1999.

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Hart, Bryan. Introduction to analogue electronics. London: Arnold, 1997.

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Warnes, Lionel. Analogue and Digital Electronics. London: Macmillan Education UK, 1998. http://dx.doi.org/10.1007/978-1-349-14037-4.

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Allen, B. W. Analogue Electronics for Higher Studies. London: Macmillan Education UK, 1995. http://dx.doi.org/10.1007/978-1-349-13364-2.

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An introduction to analogue electronics: With practical demonstrations. London: McGraw-Hill Pub., 1996.

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Electronics of measuring systems: Practical implementation of analogue and digital techniques. Chichester: Wiley, 1987.

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Improved nerve signal recording: Methods and analogue circuits. Konstanz: Hartung-Gorre, 2005.

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Saraga Colloquium on Digital Filters and Filtering Systems (1992 London). Electronics Division twelfth Saraga Colloquium on "Digital and analogue filters and filtering systems". London: Institution of Electrical Engineers, 1992.

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Green, D. C. Electronics IV: A textbook covering the analogue (linear) content of the Business and Technician Education Council's scheme for higher electronic and telecommunication technicians. 2nd ed. Harlow: Longman Scientific & Technical, 1989.

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Book chapters on the topic "Analogue electronics"

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Strong, J. A. "The analogue connection." In Basic Digital Electronics, 146–77. Dordrecht: Springer Netherlands, 1991. http://dx.doi.org/10.1007/978-94-011-3118-6_7.

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Waterworth, G. "Non-linear Analogue Systems." In Work Out Electronics, 159–67. London: Macmillan Education UK, 1988. http://dx.doi.org/10.1007/978-1-349-10008-8_9.

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Warnes, Lionel. "Electrical circuits." In Analogue and Digital Electronics, 1–49. London: Macmillan Education UK, 1998. http://dx.doi.org/10.1007/978-1-349-14037-4_1.

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Warnes, Lionel. "Data conversion." In Analogue and Digital Electronics, 414–36. London: Macmillan Education UK, 1998. http://dx.doi.org/10.1007/978-1-349-14037-4_11.

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Warnes, Lionel. "Computers, microprocessors and microcontrollers." In Analogue and Digital Electronics, 437–508. London: Macmillan Education UK, 1998. http://dx.doi.org/10.1007/978-1-349-14037-4_12.

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Warnes, Lionel. "Measurements, electrical transducers and EMC." In Analogue and Digital Electronics, 509–50. London: Macmillan Education UK, 1998. http://dx.doi.org/10.1007/978-1-349-14037-4_13.

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Warnes, Lionel. "Diodes." In Analogue and Digital Electronics, 49–87. London: Macmillan Education UK, 1998. http://dx.doi.org/10.1007/978-1-349-14037-4_2.

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Warnes, Lionel. "Bipolar junction transistors." In Analogue and Digital Electronics, 88–154. London: Macmillan Education UK, 1998. http://dx.doi.org/10.1007/978-1-349-14037-4_3.

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Warnes, Lionel. "Field-effect transistors." In Analogue and Digital Electronics, 155–98. London: Macmillan Education UK, 1998. http://dx.doi.org/10.1007/978-1-349-14037-4_4.

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Warnes, Lionel. "Feedback and operational amplifiers." In Analogue and Digital Electronics, 199–226. London: Macmillan Education UK, 1998. http://dx.doi.org/10.1007/978-1-349-14037-4_5.

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Conference papers on the topic "Analogue electronics"

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Chan, H. K., N. G. Wright, and A. B. Horsfall. "Live demonstration: Extreme environment analogue electronics for sensor nodes." In 2016 IEEE SENSORS. IEEE, 2016. http://dx.doi.org/10.1109/icsens.2016.7808569.

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Tsiatmas, A., V. A. Fedotov, and N. I. Zheludev. "Superconducting analogue of optical plasmonic waveguides." In 12th European Quantum Electronics Conference CLEO EUROPE/EQEC. IEEE, 2011. http://dx.doi.org/10.1109/cleoe.2011.5943613.

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Samuelsen, Dag A. H., and Olaf H. Graven. "An affordable pocket lab for a module in analogue electronics." In 2016 International Conference on Interactive Mobile Communication, Technologies and Learning (IMCL). IEEE, 2016. http://dx.doi.org/10.1109/imctl.2016.7753778.

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Fedotov, V. A., N. Papasimakis, A. Bitzer, M. Walther, and N. I. Zheludev. "Metamaterial analogue of the Mössbauer effect." In 11th European Quantum Electronics Conference (CLEO/EQEC). IEEE, 2009. http://dx.doi.org/10.1109/cleoe-eqec.2009.5191762.

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Mongellaz, B., F. Marc, C. Bestory, and Y. Danto. "A CMOS analogue function VHDL-AMS behavioral ageing model." In 2004 IEEE International Symposium on Industrial Electronics. IEEE, 2004. http://dx.doi.org/10.1109/isie.2004.1571805.

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Liu, Wei, Dragomir N. Neshev, Andrey E. Miroshnichenko, Ilya V. Shadrivov, and Yuri S. Kivshar. "Plasmonic analogue of quantum paddle balls." In 2011 International Quantum Electronics Conference (IQEC) and Conference on Lasers and Electro-Optics (CLEO) Pacific Rim. IEEE, 2011. http://dx.doi.org/10.1109/iqec-cleo.2011.6193810.

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Longhi, Stefano. "Photonic Analogue of Zitterbewegung and Klein Tunneling in Optical Superlattices." In Quantum Electronics and Laser Science Conference. Washington, D.C.: OSA, 2010. http://dx.doi.org/10.1364/qels.2010.jtud14.

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Wijekoon, Jayawan H. B., and Piotr Dudek. "Simple Analogue VLSI Circuit of a Cortical Neuron." In 2006 13th IEEE International Conference on Electronics, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/icecs.2006.379731.

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Graven, Olaf Hallan. "Setup to investigate game-based model for presenting analogue electronics learning material." In Annual International Conference on Education & e-Learning. Global Science & Technology Forum (GSTF), 2015. http://dx.doi.org/10.5176/2251-1814_eel15.27.

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Iliev, Ivo Ts, Dimiter H. Badarov, Serafim D. Tabakov, Borislav T. Ganev, and Ivan K. Kanev. "Fully Analogue ECG Front-end Applicable in Remote Patient Monitoring." In 2020 XXIX International Scientific Conference Electronics (ET). IEEE, 2020. http://dx.doi.org/10.1109/et50336.2020.9238247.

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Reports on the topic "Analogue electronics"

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Seaman, B. T., M. Kraemer, D. Z. Anderson, and M. J. Holland. Atomtronics: Ultracold Atom Analogs of Electronic Devices. Fort Belvoir, VA: Defense Technical Information Center, June 2006. http://dx.doi.org/10.21236/ada467798.

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Hardcastle, S. G., M G Grenier, and K. C. Butler. Electronic vane anemometry - finding a suitable replacement of mechanical analog devices for mine airflow assessment. Natural Resources Canada/CMSS/Information Management, 1991. http://dx.doi.org/10.4095/328606.

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Philpott, Rick A. Development of High Performance Electronics and Optical-to-Electrical Advanced Circuitry for Photonic Analog-to-Digital Converters. Fort Belvoir, VA: Defense Technical Information Center, February 2006. http://dx.doi.org/10.21236/ada444702.

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