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1
Berdan, Radu. "Applications of memristors in conventional analogue electronics." Thesis, Imperial College London, 2016. http://hdl.handle.net/10044/1/43370.
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This dissertation presents the steps employed to activate and utilise analogue memristive devices in conventional analogue circuits and beyond. TiO2 memristors are mainly utilised in this study, and their large variability in operation in between similar devices is identified. A specialised memristor characterisation instrument is designed and built to mitigate this issue and to allow access to large numbers of devices at a time. Its performance is quantified against linear resistors, crossbars of linear resistors, stand-alone memristive elements and crossbars of memristors. This platform allows for a wide range of different pulsing algorithms to be applied on individual devices, or on crossbars of memristive elements, and is used throughout this dissertation. Different ways of achieving analogue resistive switching from any device state are presented. Results of these are used to devise a state-of-art biasing parameter finder which automatically extracts pulsing parameters that induce repeatable analogue resistive switching. IV measurements taken during analogue resistive switching are then utilised to model the internal atomic structure of two devices, via fittings by the Simmons tunnelling barrier model. These reveal that voltage pulses modulate a nano-tunnelling gap along a conical shape. Further retention measurements are performed which reveal that under certain conditions, TiO2 memristors become volatile at short time scales. This volatile behaviour is then implemented into a novel SPICE volatile memristor model. These characterisation methods of solid-state devices allowed for inclusion of TiO2 memristors in practical electronic circuits. Firstly, in the context of large analogue resistive crossbars, a crosspoint reading method is analysed and improved via a 3-step technique. Its scaling performance is then quantified via SPICE simulations. Next, the observed volatile dynamics of memristors are exploited in two separate sequence detectors, with applications in neuromorphic engineering. Finally, the memristor as a programmable resistive weight is exploited to synthesise a memristive programmable gain amplifier and a practical memristive automatic gain control circuit.
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McEwan, Alistair. "Direct digital synthesis by analogue interpolation." Thesis, University of Oxford, 2004. http://ora.ox.ac.uk/objects/uuid:3def187d-5172-463c-9498-55898782f663.
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An improvement in efficiency of direct digital frequency synthesis (DDFS) systems is demanded for low power frequency synthesis in wireless communications. Concurrently a reduction in cost is important for disposable, low resolution frequency synthesis in biomedical instrumentation systems. To meet both these needs a new ROM-less architecture is presented here that uses less than half the circuit area of previous state of the art systems and improves the efficiency by operating at up to a tenth of the power consumption. The main contribution presented in this thesis is a novel, efficient method of interpolation for DDFS that uses the nonlinear response of the CMOS differential switch already present in the high speed current steering DAC. The nonlinear response provides a smooth transition between the conventional, quantised DAC output. This interpolation may be performed with the conventionally discarded phase bits leading to highly compact and efficient DDFS architectures for application in instrumentation and communications systems. DDFS systems typically consist of a large overflowing accumulator to generate the phase, a ROM lookup table to convert the phase to amplitude and a DAC to perform the digital to analogue conversion. Approximations are often used to reduce the size of the ROM, however the most efficient DDFS systems remove the ROM completely and calculate the phase to amplitude conversion directly or store the conversion in a non-linear DAC. State of the art, high speed CMOS DACs consisting of thermometer decoded arrays of current steering cells are often used to reduce non-ideal effects that cause unwanted transients leading to a degradation in spectral purity (SFDR). A novel ROM-less technique is introduced here that uses the non-linear response of a current cell consisting of an ideal current source and differential current switch to interpolate between the output levels of a non-linear DAC. Using this technique two architectures are developed. A compact architecture using only four or six current cells suitable for instrumentation applications and a thermometer decoded architecture using 64 current cells for communications applications that require better spectral purity. The compact architecture is 100% efficient as all the bias current is used to form the output. The only additional component is a small linear phase DAC. One compact system with a nonlinear DAC of four current cells achieved an SFDR of -40dBc up to output frequencies of 1MHz for dielectrophoresis consumed only 5μW/MHz and a second compact system with a six cell nonlinear DAC for electrical impedance spectroscopy, achieved an SFDR of -48dBc for output frequencies up to 1MHz and consumed only 8μW/MHz. As an extension to improve the SFDR a segmented system with 64 current cells was developed. The larger number of current cells required the use of a modified thermometer decoder that had the added benefit of improving the spectral purity by linearising the response of each cell. The total active area was 0.6mm2, less than half of state of the art ROM-less DDFS systems that include a DAC. Although measurement results of the 64 cell system were disappointing, simulations suggest that these problems may be solved in a future chip that should be able to achieve -70dBc SFDR at 100MHz. Despite the loss in performance from simulation to measurement, the measured 64 cell system still meets the spectral purity requirements of UMTS and Bluetooth, -60dBc SFDR.
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Sapargaliyev, Yerbol. "Automatic design of analogue circuits." Thesis, Brunel University, 2011. http://bura.brunel.ac.uk/handle/2438/6323.
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Evolvable Hardware (EHW) is a promising area in electronics today. Evolutionary Algorithms (EA), together with a circuit simulation tool or real hardware, automatically designs a circuit for a given problem. The circuits evolved may have unconventional designs and be less dependent on the personal knowledge of a designer. Nowadays, EA are represented by Genetic Algorithms (GA), Genetic Programming (GP) and Evolutionary Strategy (ES). While GA is definitely the most popular tool, GP has rapidly developed in recent years and is notable by its outstanding results. However, to date the use of ES for analogue circuit synthesis has been limited to a few applications. This work is devoted to exploring the potential of ES to create novel analogue designs. The narrative of the thesis starts with a framework of an ES-based system generating simple circuits, such as low pass filters. Then it continues with a step-by-step progression to increasingly sophisticated designs that require additional strength from the system. Finally, it describes the modernization of the system using novel techniques that enable the synthesis of complex multi-pin circuits that are newly evolved. It has been discovered that ES has strong power to synthesize analogue circuits. The circuits evolved in the first part of the thesis exceed similar results made previously using other techniques in a component economy, in the better functioning of the evolved circuits and in the computing power spent to reach the results. The target circuits for evolution in the second half are chosen by the author to challenge the capability of the developed system. By functioning, they do not belong to the conventional analogue domain but to applications that are usually adopted by digital circuits. To solve the design tasks, the system has been gradually developed to support the ability of evolving increasingly complex circuits. As a final result, a state-of-the-art ES-based system has been developed that possesses a novel mutation paradigm, with an ability to create, store and reuse substructures, to adapt the mutation, selection parameters and population size, utilize automatic incremental evolution and use the power of parallel computing. It has been discovered that with the ability to synthesis the most up-to-date multi-pin complex analogue circuits that have ever been automatically synthesized before, the system is capable of synthesizing circuits that are problematic for conventional design with application domains that lay beyond the conventional application domain for analogue circuits.
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Parish, Simon James. "Behavioural synthesis of analogue integrated circuits." Thesis, University of Birmingham, 2010. http://etheses.bham.ac.uk//id/eprint/549/.
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Automatic synthesis of analogue circuits remains a very manually intensive task despite huge strides in the field of Electronic Design Automation (EDA) in recent decades. Genetic Algorithms (GAs) are biologically inspired search algorithms which have previously shown some promise in this field. Their ability to form the basis of a practically useful synthesis system is investigated. A GA-based experimental synthesis system is implemented, which employs a Genetic Programming (GP) style encoding scheme based on tree structures, and a novel fitness function based on pole-zero analysis. The system is capable of synthesising circuit topologies entirely from scratch, but can also utilise user-provided circuit knowledge of arbitrary detail and complexity. The system uses a SPICE-based circuit simulator as a circuit evaluator. Experimental results reveal a number of issues that adversely impact the ability of GAs to reliably synthesise practically useful analogue circuits. These include considerable resource requirements and a tendency for synthesised circuits to contain an unnecessarily large number of components. Most serious is the sensitivity of analogue circuits to changes in topology and/or sizing. GAs are shown to be currently ill-suited to the problem domain of analogue circuit synthesis. The problem of SPICE non-convergence on the GA is also considered.
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Collins, Steven John. "A radio frequency capacitive discharge digital to analogue converter." Thesis, University of Glasgow, 2012. http://theses.gla.ac.uk/3371/.
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As the communications revolution continues there is an ever increasing demand for integrated transmitters and receivers on silicon in devices such as mobile phones and networking products. The demand to integrate complete systems onto a single die has driven a need to minimise the area of transmitters which has led to research into combining digital to analogue converters and RF mixers to minimise their area. The drive for increasing speeds and smaller transistors has resulted in higher capacitance densities and lower operating voltages, the latter making it more difficult to implement conventional transmitter circuits. Therefore there is a need for passive transmitter systems that maximise the output power to the load by minimising the voltage overhead on the output signal. This thesis proposes and demonstrates that it is possible to use a digital to analogue converter that performs RF up conversion using direct capacitive discharge to the load, which takes advantage of the large capacitance densities of a modern 40nm CMOS process. The DAC uses charge sharing in a similar manner to a charge sharing DAC without the bandwidth limitations imposed by an output amplifier. The RF frequency up conversion at the DAC data clock rate is produced using two DACs that differentially output the complement of each other on different halves of the clock cycle (one outputting while the other is charging) thereby emulating a passive switched mixer. The thesis shows that an 8 bit capacitive discharge DAC of 0.16mm2 can output 3dBm into a 50Ω load at 2.15GHz using a clock rate of 2GHz with MTPR of greater than 30dBc.
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Craven, Michael P. "Inter-chip communications in an analogue neural network utilising frequency division multiplexing." Thesis, University of Nottingham, 1994. http://eprints.nottingham.ac.uk/13085/.
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As advances have been made in semiconductor processing technology, the number of transistors on a chip has increased out of step with the number of input/output pins, which has introduced a communications ’bottle-neck’ in the design of computer architectures. This is a major issue in the hardware design of parallel structures implemented in either digital or analogue VLSI, and is particularly relevant to the design of neural networks which need to be highly interconnected. This work reviews hardware implementations of neural networks, with an emphasis on analogue implementations, and proposes a new method for overcoming connectivity constraints, by the use of Frequency Division Multiplexing (FDM) for the inter-chip communications. In this FDM scheme, multiple analogue signals are transmitted between chips on a single wire by modulating them at different frequencies. The main theoretical work examines the number of signals which can be packed into an FDM channel, depending on the quality factors of the filters used for the demultiplexing, and a fractional overlap parameter which was defined to take into account the inevitable overlapping of filter frequency responses. It is seen that by increasing the amount of permissible overlap, it is possible to communicate a larger number of signals in a given bandwidth. Alternatively, the quality factors of the filters can be reduced, which is advantageous for hardware implementation. Therefore, it was found necessary to determine the amount of overlap which might be permissible in a neural network implementation utilising FDM communications. A software simulator is described, which was designed to test the effects of overlap on Multilayer Perceptron neural networks. Results are presented for networks trained with the backpropagation algorithm, and with the alternative weight perturbation algorithm. These were carried out using both floating point and quantised weights to examine the combined effects of overlap and weight quantisation. It is shown using examples of classification problems, that the neural network learning is indeed highly tolerent to overlap, such that the effect on performance (i.e. on convergence or generalisation) is negligible for fractional overlaps of up to 30%, and some tolerence is achieved for higher overlaps, before failure eventually occurs. The results of the simulations are followed up by a closer examination of the mechanism of network failure. The last section of the thesis investigates the VLSI implementation of the FDM scheme, and proposes the use of the operational transconductance amplifier (OTA) as a building block for implementation of the FDM circuitry in analogue VLSI. A full custom VLSI design of an OTA is presented, which was designed and fabricated through Eurochip, using HSPICE/Mentor Graphics CAD tools and the Mietec 2.4µ CMOS process. A VLSI architecture for inter-chip FDM is also proposed, using adaptive tuning of the OTA-C filters and oscillators.This forms the basis for a program of further work towards the VLSI realisation of inter-chip FDM, which is outlined in the conclusions chapter.
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Feng, Hong. "Impact of atomistic device variability on analogue circuit design." Thesis, University of Glasgow, 2011. http://theses.gla.ac.uk/3074/.
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Scaling of complementary metal-oxide-semiconductor (CMOS) technology has benefited the semiconductor industry for almost half a century. For CMOS devices with a physical gate-length in the sub-100 nm range, extreme device variability is introduced and has become a major stumbling block for next generation analogue circuit design. Both opportunities and challenges have therefore confronted analogue circuit designers. Small geometry device can enable high-speed analogue circuit designs, such as data conversion interfaces that can work in the radio frequency range. These designs can be co-integrated with digital systems to achieve low cost, high-performance, single-chip solutions that could only be achieved using multi-chip solutions in the past. However, analogue circuit designs are extremely vulnerable to device mismatch, since a large number of symmetric transistor pairs and circuit cells are required. The increase in device variability from sub-100 nm processes has therefore significantly reduced the production yield of the conventional designs. Mismatch models have been developed to analytically evaluate the magnitude of random variations. Based on measurements from custom designed test structures, the statistics of process variation can be estimated using design related parameters. However, existing models can no longer accurately estimate the magnitude of mismatch for sub-100 nm “atomistic” devices, since short-channel effects have become important. In this thesis, a new mismatch model for small geometry devices will be proposed to address this problem. Based on knowledge of the matching performance obtained from the mismatch model, design solutions are desired at different design levels for a variety of circuit topologies. In this thesis, transistor level compensation solutions have been investigated and closed-loop compensation circuits have been proposed. At circuit level, a latch-based comparator has been used to develop a compensation solution because this type of comparator is extremely sensitive to the device mismatch. These comparators are also used as the fundamental building block for the analogue-to-digital converters (ADC). The proposed comparator compensation scheme is used to improve the performance of a high-speed flash ADC.
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Tanhaei, Ghazal. "A power-scalable variable-length analogue DFT processor for multi-standard wireless transceivers." Thesis, University of Birmingham, 2016. http://etheses.bham.ac.uk//id/eprint/7072/.
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In the Orthogonal Frequency-Division Multiplexing (OFDM) based transceivers, digital computation of the Discrete Fourier Transform (DFT) is a power hungry process. Reduction in the hardware cost and power consumption is possible by implementing the DFT processor with analogue circuits. This thesis presents the real-time recursive DFT processor. Previously, changing the transform length and scaling the power could only be performed by digital Fast Fourier Transform (FFT) processors. By using the real-time recursive DFT processor, the decimation filter is eliminated. Thus, further reduction in the hardware cost and power consumption of the multi-standard transceiver is achieved. The real-time recursive DFT processor was designed in 180 nm CMOS technology. Results of device mismatch analysis indicate that the 8-point recursive DFT processor has a yield of 97.5% for the BPSK modulated signal. For the QPSK modulated signal, however, yield of the 8-point recursive DFT processor is 8.9%. Moreover, doubling the transform length reduces the average dynamic range by 3dB. Accordingly, the 16-point recursive DFT processor has a yield of 43.4% for the BPSK modulated signal. Power consumption of the recursive DFT processor is about 1/6 of the power consumption of a previous analogue FFT processor.
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Heima, Mohamed Mohamed. "The design of active-R and active-RC sinusoidal oscillators." Thesis, Manchester Metropolitan University, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.337186.
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Hertel, Thorsten W. "Pulse radiation from an insulated antenna : an analogue of Cherenkov radiation from a moving charge." Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/15752.
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Rudolf, Robert. "Design methods to mitigate the effects of variation in analogue and mixed-signal circuits." Thesis, University of Southampton, 2014. https://eprints.soton.ac.uk/374300/.
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The continued scaling of CMOS process features enables ever-faster and denser circuits, which comes at the cost of increased device parameter variation. The performance of analogue and mixed-signal circuits in particular degrades in such a high variation environment, which poses an extraordinary challenge in the design and fabrication of such circuits. This thesis develops a set of tools and methodologies for a post-fabrication calibration system called the Configurable Analogue Transistor (CAT). The principle of the CAT technique is to replace certain transistors in a circuit with calibration devices, which allow adjustment of circuit performance after fabrication to compensate the effects of device parameter variation. Building on initial research on the CAT, this thesis develops a methodology to identify the most suitable calibration devices in their circuit and determine their optimal sizes. Furthermore, the applicability of CAT is extended beyond parameter variation to also include direct compensation of temperature. A complementary technique to post-fabrication calibration is robust design, where a circuit is designed to be inherently robust against variation in device parameters. In this thesis, a novel closed-loop pick-off circuit for force-balanced MEMS accelerometers is presented. It is comparable in performance to other state-of-the-art techniques, but provides vastly improved robustness against parameter variation and a more intuitive design process.
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Ng, Chuk Man 1974. "On the digital re-design of an analogue missile flight control system using PIM method." Thesis, McGill University, 1999. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=30263.
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This research examines some of the ways to design a digital control system with particular reference to the control of yaw plane dynamics of an air-to-air missile model. Specific attention is paid to compare two methods of global digital re-design of validated analogue closed loop control system. These two methods are the multi-input multi-output (MIMO) Plant Input Mapping (PIM) method and multi-loop PIM method. The thesis will first show how a specific class of closed loop MIMO feedback systems with a single-input multi-output (SIMO) plant can be re-structured as multi-loop control systems, which includes the closed loop missile control system. Some special characteristics pertaining to SIMO systems for control system design are explored. The aforementioned two methods of PIM global digital re-design are then applied to the MIMO analogue missile control system and its re-structured multi-loop counterpart. A comparison of the two methods is made on its design procedure, implementation structure and results from computer simulation.This thesis also touches upon the topic of controller order reduction, particularly in consideration of the PIM digital re-design of analogue feedback systems. (Abstract shortened by UMI.)
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Soell, Sven. "Theory and applications of delta-sigma analogue-to-digital converters without negative feedback." Thesis, Connect to e-thesis, 2008. http://theses.gla.ac.uk/369/.
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Thesis (Ph.D.) - University of Glasgow, 2008.Ph.D. thesis submitted to the Department of Electronics and Electrical Engineering, Faculty of Engineering, University of Glasgow, 2008. Includes bibliographical references. Print version also available.
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Eberhardt, Friedemann. "Symbolic tolerance and sensitivity analysis of large scale electronic circuits." Thesis, University of Bath, 1999. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301578.
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Ravi, Sanjay. "Inter-pulse interval based mixed signal representations/." Full text open access at:, 2008. http://content.ohsu.edu/u?/etd,656.
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Sheehan, Kevin Michael. "Evolving analogue electronic signal processing circuit behaviour in hardware." Thesis, Royal Holloway, University of London, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.272073.
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Choubey, Bhaskar. "On wide dynamic range logarithmic CMOS image sensors." Thesis, University of Oxford, 2006. http://ora.ox.ac.uk/objects/uuid:f2d8ea6d-6b71-45bf-80dc-7dadb1421e3b.
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Logarithmic sensors are capable of capturing the wide dynamic range of intensities available in nature with minimum number of bits and post-processing required. A simple circuit able to perform logarithmic capture is one utilising a MOS device in weak inversion. However, the output of this pixel is crippled due to fixed pattern noise. Technique proposed to reduce this noise fail to produce high quality images on account of unaccounted high gain variations in the pixel. An electronic calibration technique is proposed which is capable of reducing both multiplicative as well as additive FPN. Contrast properties matching that of human eye are reported from these sensors. With reduced FPN, the pixel performance at low intensities becomes concerning. In these regions, the high leakage current of the CMOS process affects the logarithmic pixel. To reduce this current, two different techniques using a modified circuit and another with modified layout are tested. The layout technique is observed to reduce the leakage current. In addition, this layout can be used to linearise the output of logarithmic pixel in low light regions. The unique linear response at low light and logarithmic pixel at high light is further investigated. A new model based on the device physics is derived to represent this response. The fixed pattern noise profile is also investigated. An intelligent iterative scheme is proposed and verified to extract the photocurrent flowing in the pixel and correct the fixed pattern noise utilising the new model. Future research ideas leading to better designs of logarithmic pixels and post-processing of these signals are proposed at the end of the thesis.
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Care, Charles. "From analogy-making to modelling : the history of analog computing as a modelling technology." Thesis, University of Warwick, 2008. http://wrap.warwick.ac.uk/2381/.
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Today, modern computers are based on digital technology. However, during the decades after 1940, digital computers were complemented by the separate technology of analog computing. But what was analog computing, what were its merits, and who were its users? This thesis investigates the conceptual and technological history of analog computing. As a concept, analog computing represents the entwinement of a complex pre-history of meanings, including calculation, modelling, continuity and analogy. These themes are not only landmarks of analog's etymology, but also represent the blend of practices, ways of thinking, and social ties that together comprise an `analog culture'. The first half of this thesis identifies how the history of this technology can be understood in terms of the two parallel themes of calculation and modelling. Structuring the history around these themes demonstrates that technologies associated with modelling have less representation in the historiography. Basing the investigation around modelling applications, the thesis investigates the formation of analog culture. The second half of this thesis applies the themes of modelling and information generation to understand analog use in context. Through looking at examples of analog use in academic research, oil reservoir modelling, aeronautical design, and meteorology, the thesis explores why certain communities used analog and considers the relationship between analog and digital in these contexts. This study demonstrates that analog modelling is an example of information generation rather than information processing. Rather than focusing on the categories of analog and digital, it is argued that future historical scholarship in this field should give greater prominence to the more general theme of modelling.
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Dickinson, John Andrew. "Electronic spectroscopy and conformations of aromatic systems." Thesis, University of Oxford, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.363668.
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Long, David Ian. "Behavioural simulation of mixed analogue/digital circuits." Thesis, Bournemouth University, 1996. http://eprints.bournemouth.ac.uk/278/.
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Continuing improvements in integrated circuit technology have made possible the implementation of complex electronic systems on a single chip. This often requires both analogue and digital signal processing. It is essential to simulate such IC's during the design process to detect errors at an early stage. Unfortunately, the simulators that are currently available are not well-suited to large mixed-signal circuits. This thesis describes the design and development of a new methodology for simulating analogue and digital components in a single, integrated environment. The methodology represents components as behavioural models that are more efficient than the circuit models used in conventional simulators. The signals that flow between models are all represented as piecewise-linear (PWL) waveforms. Since models representing digital and analogue components use the same format to represent their signals, they can be directly connected together. An object-oriented approach was used to create a class hierarchy to implement the component models. This supports rapid development of new models since all models are derived from a common base class and inherit the methods and attributes defined in their parentc lassesT. he signal objectsa re implementedw ith a similar class hierarchy. The development and validation of models representing various digital, analogue and mixed-signal components are described. Comparisons are made between the accuracy and performance of the proposed methodology and several commercial simulators. The development of a Windows-based demonstrations imulation tool called POISE is also described. This permitted models to be tested independently and multiple models to be connected together to form structural models of complex circuits.
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Bee, Sarah Caroline. "Radiation effects in analogue to digital converters." Thesis, University College London (University of London), 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.298887.
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Osuch, Piotr. "Synthesis and monolithic integration of analogue signal processing networks." Thesis, University of Pretoria, 2018. http://hdl.handle.net/2263/66382.
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Data traffic of future 5G telecommunication systems is projected to increase 10 000-fold compared to current rates. 5G fronthaul links are therefore expected to operate in the mm-wave spectrum with some preliminary International Telecommunication Union specifications set for the 71-76 and 81-86 GHz bands. Processing 5 GHz as a single contiguous band in real-time, using existing digital signal processing (DSP) systems, is exceedingly challenging. A similar challenge exists in radio astronomy, with the Square Kilometer Array project expecting data throughput rates of 15 Tbits/s at its completion. Speed improvements on existing state-of-the-art DSPs of 2-3 orders of magnitude are therefore required to meet future demands.
One possible mitigating approach to processing wideband data in real-time is to replace some DSP blocks with analog signal processing (ASP) equivalents, since analogue devices outperform their digital counterparts in terms of cost, power consumption and the maximum attainable bandwidth. The fundamental building block of any ASP is an all-pass network of prescribed response, which can always be synthesized by cascaded first- and second-order all-pass sections (with two cascaded first-order sections being a special case of the latter). The monolithic integration of all-pass networks in commercial CMOS and BiCMOS technology nodes is a key consideration for commercial adaptation of ASPs, since it supports mass production at reduced costs and operating power requirements, making the ASP approach feasible. However, this integration has presented a number of yet unsolved challenges.
Firstly, the state-of-the-art methods for synthesizing quasi-arbitrary group delay functions using all-pass elements lack a theoretical synthesis procedure that guarantees minimum-order networks. In this work an analytically-based solution to the synthesis problem is presented that produces an all-pass network with a response approximating the required group delay to within an arbitrary minimax error. This method is shown to work for any physical realization of second-order all-pass elements, is guaranteed to converge to a global optimum solution without any choice of seed values as an input, and allows synthesis of pre-defined networks described either analytically or numerically.
Secondly, second-order all-pass networks are currently primarily implemented in off-chip planar media, which is unsuited for high volume production. Component sensitivity, process tolerances and on-chip parasitics often make proposed on-chip designs impractical. Consequently, to date, no measured results of a dispersive on-chip second-order all-pass network suitable for ASP applications (delay Q-value (QD) larger than 1) have been presented in either CMOS or BiCMOS technology nodes. In this work, the first ever on-chip CMOS second-order all-pass network is proposed with a measured QD-value larger than 1. Measurements indicate a post-tuning bandwidth of 280 MHz, peak-to-nominal delay variation of 10 ns, QD-value of 1.15 and magnitude variation of 3.1 dB. An active on-chip mm-wave second-order all-pass network is further demonstrated in a 130 nm SiGe BiCMOS technology node with a bandwidth of 40 GHz, peak-to-nominal delay of 62 ps, QD-value of 3.6 and a magnitude ripple of 1.4 dB. This is the first time that measurement results of a mm-wave bandwidth second-order all-pass network have been reported.
This work therefore presents the first step to monolithically integrating ASP solutions to conventional DSP problems, thereby enabling ultra-wideband signal processing on-chip in commercial technology nodes.Thesis (PhD)--University of Pretoria, 2018.
Square Kilometer Array (SKA) project - postgraduate scholarship
Electrical, Electronic and Computer Engineering
PhD
Unrestricted
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Joubert, Antoine. "Neurone analogique robuste et technologies émergentes pour les architectures neuromorphiques." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00935178.
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Les récentes évolutions en microélectronique nécessitent une attention particulière lors de la conception d'un circuit. Depuis les noeuds technologiques de quelques dizaines de nanomètres, les contraintes de consommation deviennent prépondérantes. Pour répondre à ce problème, les concepteurs se penchent aujourd'hui sur l'utilisation d'architectures multi-coeurs hétérogènes incluant des accélérateurs matériels dotés d'une grande efficacité énergétique. Le maintien des spécifications d'un circuit apparait également essentiel à l'heure où sa fabrication est de plus en plus sujette à la variabilité et aux défauts. Il existe donc un réel besoin pour des accélérateurs robustes. Les architectures neuromorphiques, et notamment les réseaux de neurones à impulsions, offrent une bonne tolérance aux défauts, de part leur parallélisme massif, et une aptitude à exécuter diverses applications à faible coût énergétique. La thèse défendue se présente sous deux aspects. Le premier consiste en la conception d'un neurone analogique robuste et à son intégration dans un accélérateur matériel neuro-inspiré à des fins calculatoires. Cet opérateur mathématique à basse consommation a été dimensionné puis dessiné en technologie 65 nm. Intégré au sein de deux circuits, il a pu être caractérisé dans l'un d'entre eux et ainsi démontrer la faisabilité d'opérations mathématiques élémentaires. Le second objectif est d'estimer, à plus long terme, l'impact des nouvelles technologies sur le développement de ce type d'architecture. Ainsi, les axes de recherches suivis ont permis d'étudier un passage vers un noeud technologique très avancé, les opportunités procurées par des Through-Silicon-Vias ou encore, l'utilisation de mémoires résistives à changement de phase ou à filament conducteur.
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Stocks, Nigel Geoffrey. "Experiments in stochastic nonlinear dynamics." Thesis, Lancaster University, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.315224.
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Besnard, SteÌphane Claude Louis. "Optimising fault modelling and test development for VLSI analogue circuits." Thesis, University of Huddersfield, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.288503.
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Dida, Bashkim. "Automatiserad konstruktion av analoga förstärkare." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2944.
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The last few decades the development in the field of electronics has been huge. The components performance gets better at the same time as the manufacturing cost decreases. Many of the design moments that have to be done, are done automatically today, but it can get better. Especially for analog circuit design.
At Electronic System in Linköpings universitet, research is in progress to develop a tool that can design analog circuits in reasonable time. It means that it has to size the components (transistors, resistances, capacitances etc), so that the circuit can fulfill the performance requirements. An optimization method in conjunction with derived equations for the circuit performance is used to solve this task. The tool is created to design e.g. analog amplifiers. The goal is to decrease the design time and at the same time achieve better circuit performance.
This tool has been tested on three different circuits, a power-amplifier, a Nested Miller Compensated amplifier with an active feedback (Active Nested Miller Compensation) and a Nested Miller Compensated amplifier without an active feedback (Nested Miller Compensation). In this report the results from the designing tests are presented.
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Spinks, Stephen James. "Fault simulation for structural testing of analogue integrated circuits." Thesis, University of Hull, 1998. http://hydra.hull.ac.uk/resources/hull:8047.
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In this thesis the ANTICS analogue fault simulation software is described which provides a statistical approach to fault simulation for accurate analogue IC test evaluation. The traditional figure of fault coverage is replaced by the average probability of fault detection. This is later refined by considering the probability of fault occurrence to generate a more realistic, weighted test metric. Two techniques to reduce the fault simulation time are described, both of which show large reductions in simulation time with little loss of accuracy. The final section of the thesis presents an accurate comparison of three test techniques and an evaluation of dynamic supply current monitoring. An increase in fault detection for dynamic supply current monitoring is obtained by removing the DC component of the supply current prior to measurement.
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Nalbantis, Dimitris. "World Wide Web based layout synthesis for analogue modules." Thesis, University of Kent, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.365218.
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Mangieri, Eduardo. "An analogue approach for the processing of biomedical signals." Thesis, University of Southampton, 2012. https://eprints.soton.ac.uk/348009/.
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Constant device scaling has signifcantly boosted electronic systems design in the digital domain enabling incorporation of more functionality within small silicon area and at the same time allows high-speed computation. This trend has been exploited for developing high-performance miniaturised systems in a number of application areas like communication, sensor network, main frame computers, biomedical information processing etc. Although successful, the associated cost comes in the form of high leakage power dissipation and systems reliability. With the increase of customer demands for smarter and faster technologies and with the advent of pervasive information processing, these issues may prove to be limiting factors for application of traditional digital design techniques. Furthermore, as the limit of device scaling is nearing, performance enhancement for the conventional digital system design methodology cannot be achieved any further unless innovations in new materials and new transistor design are made. To this end, an alternative design methodology that may enable performance enhancement without depending on device scaling is much sought today. Analogue design technique is one of these alternative techniques that have recently gained considerable interests. Although it is well understood that there are several roadblocks still to be overcome for making analogue-based system design for information processing as the main-stream design technique (e.g., lack of automated design tool, noise performance, efficient passive components implementation on silicon etc.), it may offer a faster way of realising a system with very few components and therefore may have a positive implication on systems performance enhancement. The main aim of this thesis is to explore possible ways of information processing using analogue design techniques in particular in the field of biomedical systems.
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Md, Ali Sawal Hamid. "System level performance and yield optimisation for analogue integrated circuits." Thesis, University of Southampton, 2009. https://eprints.soton.ac.uk/69724/.
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Advances in silicon technology over the last decade have led to increased integration of analogue and digital functional blocks onto the same single chip. In such a mixed signal environment, the analogue circuits must use the same process technology as their digital neighbours. With reducing transistor sizes, the impact of process variations on analogue design has become prominent and can lead to circuit performance falling below specification and hence reducing the yield. This thesis explores the methodology and algorithms for an analogue integrated circuit automation tool that optimizes performance and yield. The trade-offs between performance and yield are analysed using a combination of an evolutionary algorithm and Monte Carlo simulation. Through the integration of yield parameter into the optimisation process, the trade off between the performance functions can be better treated that able to produce a higher yield. The results obtained from the performance and variation exploration are modelled behaviourally using a Verilog-A language. The model has been verified with transistor level simulation and a silicon prototype. For a large analogue system, the circuit is commonly broken down into its constituent sub-blocks, a process known as hierarchical design. The use of hierarchical-based design and optimisation simplifies the design task and accelerates the design flow by encouraging design reuse. A new approach for system level yield optimisation using a hierarchical-based design is proposed and developed. The approach combines Multi-Objective Bottom Up (MUBU) modelling technique to model the circuit performance and variation and Top Down Constraint Design (TDCD) technique for the complete system level design. The proposed method has been used to design a 7th order low pass filter and a charge pump phase locked loop system. The results have been verified with transistor level simulations and suggest that an accurate system level performance and yield prediction can be achieved with the proposed methodology.
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Langsdorf, Brandi L. "Synthesis, characterization, and electronic properties of soluble, ionically functionalized polyacetylene analogues /." view abstract or download file of text, 2001. http://wwwlib.umi.com/cr/uoregon/fullcit?p3003996.
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Thesis (Ph. D.)--University of Oregon, 2001.Typescript. Includes vita and abstract. Includes bibliographical references (leaves 163-173). Also available for download via the World Wide Web; free to University of Oregon users.
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Smith, Paul Carson. "Broadband analog opto-electronic blind source separation." Diss., Connect to online resource, 2005. http://wwwlib.umi.com/dissertations/fullcit/3178354.
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Basak, Juthika. "Adaptive electronic linearization of analog optical links." Diss., Restricted to subscribing institutions, 2006. http://proquest.umi.com/pqdweb?did=1280148041&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Fiedorow, Pawel. "Etude et optimisation de structures intégrées analogiques en vue de l'amélioration du facteur de mérite des amplificateurs opérationnels." Thesis, Lyon, INSA, 2012. http://www.theses.fr/2012ISAL0061.
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Rail à rail entrée - sortie, classe AB, faible consommation sont autant de critères que le concepteur d'amplificateur opérationnel (AOP) intègre pour réaliser une cellule analogique performante. Pour un AOP standard, l'accent n'est pas porté sur une caractéristique particulière mais sur l’ensemble de celle-ci. Dans le but d'augmenter le nombre de fonction par circuit intégré, la tension d'alimentation des AOPs ainsi que leur consommation en courant tendent à diminuer. L'objectif des circuits réalisés est de doubler le facteur de mérite des circuits déjà présents dans le portefeuille de STMicroelectronics. Le facteur de mérite est un indice qui compare des circuits équivalents. Il est défini par le rapport entre le produit capacité de charge x produit gain bande-passante et le produit courant de consommation x tension d'alimentation. L'état de l'art des structures d'AOPs a orienté l'étude vers des structures analogiques possédant au moins trois étages de gain. Un niveau de gain statique supérieur à la centaine de décibel est nécessaire pour utiliser ces amplificateurs dans des systèmes contre-réactionnés. Puisque chaque étage de gain introduit un noeud haute impédance et que chaque noeud haute impédance est à l'origine d'un pôle, l'étude de la compensation fréquentielle s'est avérée indispensable pour obtenir des structures optimisées. Pour simplifier l'étude de ces AOPs, le développement d'outils d'aide à la conception analogique a contribué à l'automatisation de plusieurs tâches.. Ces différents travaux ont été ponctués par la réalisation et la caractérisation de six circuits. Les compensations fréquentielles utilisées dans ces circuits sont la compensation nested miller , la compensation reversed nested miller et la compensation multipath nested miller . Parmi les six circuits, une moitié a été réalisée uniquement dans le but de valider des concepts de compensation fréquentielle et l'autre moitié avec toutes les contraintes d'une documentation technique propre à la famille d'AOP standardTo be in line with the standard of operational amplifier (opamp), designer integrates in his circuit several functionalities like a Rail to rail input and output, class AB output stage and low power consumption. For standard products, there is no outstanding performance but the average of all of them has to be good. In order to increase the number of functions on an integrated circuit, the power supply and current consumption are permanently decreasing. The aim of the designed circuits is to double the figure of merit (FOM) of the actual ST portfolio products. The FOM allows the comparison of similar opamps. It is defined by the ratio of the product of capacitive load x gain-bandwith product over the power consumption. The opamps’ state of the art has led this study to three stages analog cells. A DC gain higher than hundreds of decibel is required to use opamps in feedback configuration. As each stage of the structure introduces a high impedance node and as each high impedance node introduces a pole, the study of frequency compensation technics became essential for well optimized structures. To simplify the study of the opamps, three tools have been developed to help in the design of the frequency compensation network and to automate some tasks. This work has been followed by the realization of six cells. Three of them were designed to validate frequency compensation structure and the other three to satisfy a standard opamp datasheet. Nested Miller, Reversed Nested Miller and Multipath Nested Miller compensations were used in these circuits
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Carlsson, Fredrick, and David Kronqvist. "Generering av analoga signaler från XSV-300." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1769.
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Att ett grafikkort ska behandla data och sen generera en bild på en skärm är en ganska logisk funktion för ett grafikkort. Vad som har gjorts här är att alla grundläggande funktioner för grafikkortet har tagits bort, detta för att ingen behandling ska göras. Detta har gjorts för att kunna låta data passera genom kortet med så hög hastighet som möjligt. Att låta data gå genom kortet var det första steget. Efter det skulle förhoppningsvis ett stabilt system ha uppnåtts där vi kunde göra överföringen av data snabbare. Tyvärr blev det inte tillräckligt stabilt och vår slutsats är att man inte kan använda detta kort på det här sättet.
För att kunna genomföra detta programmerades FPGA:n med VHDL-kodning. Innan VHDL programmeringen så studerades manualen för kortet för att veta hur de olika registrena på kortet skulle ställas in.
För att testa programmering konstruerades en räknare som genererade en trekantsvåg på ett inkopplat oscilloskop.
Den ursprungliga uppgiften klarades av. Detta var att skicka igenom data utan den skulle behandlas.
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Cellier, Remy. "Contrôle et intégration d’amplificateurs de classe D à commande numérique pour la téléphonie mobile." Thesis, Lyon, INSA, 2011. http://www.theses.fr/2011ISAL0063/document.
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L'intégration de nombreuses fonctions complexes dans les systèmes embarqués, tels que les téléphones portables, conduit à optimiser la consommation d'énergie pour maintenir l'autonomie de fonctionnement. Concernant la chaine de reproduction sonore, la consommation a été réduite par l'utilisation d'amplificateurs de classe D analogique, mais la nature numérique de la source audio impose encore un convertisseur numérique analogique en amont. La forte consommation de ce CAN et la qualité de reproduction sonore de l'amplificateur sont actuellement les principales limitations de cette approche. Ce travail de recherche, réalisé en quatre phases, a donc pour objectifs d'apporter des améliorations et de proposer de nouvelles architectures pour réduire ces limitations. Concernant l'amplificateur de classe D analogique, une boucle d'asservissement analogique basée sur un modulateur auto-oscillant à hystérésis a été développée pour réduire la consommation et augmenter sa qualité de reproduction. Cette étude a été validée par la réalisation d'un circuit en technologie CMOS 130 nm. La possibilité de piloter l'amplificateur de classe D directement par un signal de commande numérique a ensuite été envisagée. Le train d'impulsions nécessaire à la commande de l'étage de puissance est obtenu par modulation numérique de la source audio. L'utilisation en boucle ouverte de l'étage de puissance ne permet néanmoins pas d'obtenir un signal audio de sortie insensible aux variations de l'alimentation. Un asservissement analogique local autour de l'étage de puissance est donc nécessaire. La réalisation en technologie CMOS 130 nm de cette architecture a permis la validation des études effectuées (fonctionnement, stabilité, bande passante, modélisations des éléments non linéaires,...)The integration of many complex functions in embedded systems such as mobile phones, led to optimize energy consumption to maintain operational autonomy. Concerning the chain of sound reproduction, consumption was reduced by the use of analog Class D amplifiers, but the nature of the digital audio source requires a digital to analog converter further upstream. The high consumption of the ADC and the quality of sound reproduction of the amplifier are currently the main limitations of this approach. This research, conducted in four phases, thus aims to make improvements and propose new architectures to reduce these limitations. Regarding the Class D amplifier analog control loop an analog modulator based on a self-oscillating hysteresis has been developed to reduce consumption and increase its quality of reproduction. This study was validated by the realization of a circuit in CMOS 130 nm. The ability to control the class D amplifier directly from a digital control signal was then considered. The train of pulses needed to control the power stage is obtained by digital modulation of the audio source. The use of open-loop output stage, however, does not produce an audio signal output insensitive to variations in the diet. A local analog servo around the power stage is required. Realization in CMOS 130 nm of this architecture has allowed the validation studies (operation, stability, bandwidth, modeling non-linear elements ,...). The interface between the digital modulator and the analog part is very sensitive to disturbance. A digital control overall Class D amplifier with digital control has been studied to control the interface. A prototype of this control is in progress
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Sabzavari, Abbas Mostafavi. "Fault simulation and diagnosis in analog electronic systems." Thesis, University of Exeter, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.328233.
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Wang, Haibo. "Field programmable analog array synthesis." Diss., The University of Arizona, 2002. http://hdl.handle.net/10150/289777.
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Field programmable analog arrays (FPAAs), the analog counterparts of digital field programmable gate arrays (FPGAs), are suitable for prototyping analog circuits and implementing dynamically re-configurable analog systems. Although various FPAA architectures have been recently developed, very little work has been reported in the area of design automation for field programmable analog arrays. The lack of sophisticated FPAA synthesis tools is becoming one of the key limitations toward fully exploiting the advantages of FPAAs. To address this problem, this dissertation presents a complete synthesis flow that can automatically translate abstract-level analog function descriptions into FPAA circuit implementations. The proposed synthesis flow consists of function decomposition, macro-cell synthesis, placement & routing, and post-placement simulation subroutines. The function decomposition subroutine is aimed at decomposing high-order analog functions into low-order sub-functions. This not only increases the accuracy of the realized analog functions, but also reduces the routing complexity of the synthesized circuits. The macro-cell synthesis subroutine generates circuit implementations for the decomposed sub-functions. Then, FPAA placement & routing is performed to map the synthesized analog circuits onto FPAA chips. The final stage of the synthesis flow is post-placement simulation, which is used to verify that the synthesized circuits meet performance specifications. The major contributions of this dissertation are techniques developed for implementing the FPAA synthesis flow. In the work of function decomposition, we developed theoretical proofs for two optimization criteria that were previously used to search optimal function decomposition solutions. In addition, we developed more efficient procedures to search optimal function decomposition solutions. To implement the macro-cell synthesis subroutine, we proposed a modified signal flow graph to represent FPAA circuits. Graph transformations are introduced for exploring alternative circuit structures in FPAA synthesis. Finally, in the work of FPAA placement and routing, an efficient method for estimating FPAA parasitic effects was developed. The effectiveness of the developed techniques is demonstrated by the experiments of synthesizing various FPAA circuits. The proposed synthesis methodologies will significantly simplify the use of FPAAs, and consequently make FPAAs more appealing in analog design.
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Jonsson, Per-Axel. "Simulated Annealing : implementering mot integrerade analoga kretsar." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2531.
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Today electronics becomes more and more complex and to keep low costs and power consumption, both digital and analog parts are implemented on the same chip. The degree of automization for the digital parts have increased fast and is high, but for the analog parts this has not come through. This have created a big gap between the degrees of automization for the two parts and makes the analog parts the bottleneck in electronics develop.
Research is ongoing at Electronics systems group at Linköping University target the increase of design automization for analog circuits. An optimizationbased approach for device sizing is developed and for this a good optimization method is needed which can find good solutions and meet the specification parameters.
This report contains an evaluation of the optimization method Simulated Annealing. Many test runs have been made to find out good control parameters, both for Adaptiv Simulated Annealing (ASA) and a standard Simulated Annealing method. The result is discussed and all the data is in the enclosures. A popular science and mathematical description is given for Simulated Annealing as well.
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Danzeca, Salvatore. "The new version of the Radiation Monitor system for the electronics at the CERN : electronic components radiation hardness assurance and sensors qualication." Thesis, Montpellier, 2015. http://www.theses.fr/2015MONTS196/document.
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La mesure des niveaux de rayonnement est une exigence essentielle dans le LHC et ses lignes d'injection afin de quantifier les effets des radiations sur l'électronique et de fournir une connaissance détaillée du champ de rayonnement. Le système de surveillance des rayonnements pour l'électronique au CERN, le "RadMon '', a été installé dans les zones critiques où l'équipement est ou sera placé. Les problèmes rencontrés au cours des dernières années d'utilisation du Radmon, et la nécessité d'améliorer la précision et la résolution des mesures a conduit au lancement d'une nouvelle conception du moniteur.Ce travail décrit l'architecture du nouveau RadMon (V6), sa fiabilité dans les environnements radiatifs et de la stratégie adoptée pour choisir et qualifier les capteurs utilisés pour surveiller le champ de rayonnement mixte des accélérateurs du LHC. Les directives du CERN ont été adoptées pour qualifier les composants RadMon sous rayonnement afin de développer une nouvelle architecture à la fois plus tolérante au rayonnement et plus polyvalente que celui de la version précédente. Dans ce contexte, les défis que les tests de rayonnement imposent pour mesurer les Single Event Upsets (SEUs) sur un composant complexe à signaux mixtes tels que le convertisseur analogique-numérique, ont conduit au développement d'une technique de test innovant, qui sera décrit dans cette thèse.L'environnement radiatif complexe du LHC impose un processus de qualification particulier qui sera décrit et discuté dans ce travail pour les RadFets (capteur dose ionisante) et les mémoires SRAM (capteur de fluence High Energy Hadrons).L'utilisation du RadFet dans un champ mixte de rayonnement a été étudié et analysé au moyen de sources de 60Co et de faisceaux de protons de différentes énergies.Les RadFets ont été ré-étalonné en étudiant le débit de dose, les sources de particules, la température, la guérison thermique en fonction de l'épaisseur d'oxyde. En outre, grâce à la nouvelle architecture de la RadMon, de nouvelles configurations de polarisation ont été testées pour améliorer la résolution.Deux types de mémoires SRAM avec des nœuds technologiques de 400 et 90 nm ont été testés et calibrés en suivant une méthode de qualification stricte qui comprend des tests protons,dans la plage de 30 à 400 MeV et neutrons, depuis les énergies thermiques jusqu'à des énergies intermédiaires (~ 14 MeV). La mémoire 90 nm améliore la précision et la résolution de la mesure de la fluence hadronique. En outre, l'utilisation simultanée des deux types de mémoires améliore la précision de la détection des neutrons thermiques par rapport à la version précédente, grâce à d'une procédure qui sera détaillée dans ce travail.Les efforts en vue de l'amélioration de la résolution des mesures de TID pour le nouveau RadMon conduisent à la recherche et à l'étude d'un nouveau type de dosimètre : le dosimètre a Grille Flottante (FGDOS). Le capteur intégrant une électronique complexe, une qualification complète sous rayonnement était nécessaire. Des tests en champ mixte, des tests au 60Co et des tests au protons ont été réalisés afin d'évaluer les performances et les problèmes potentiels du capteur. Dans ce contexte, un modèle analytique du capteur a été conçu pour démontrer que la structure à Grille Flottante pouvait être utilisée comme instrument de mesure du ‘charge yield' à température ambiante et sous des champs électriques faibles.La caractérisation de la tolérance au rayonnement du matériel, le processus de qualification et les étalonnages des capteurs ont considérablement amélioré la fiabilité globale et la qualité des mesures sur la nouvelle version du RadMon. Ces améliorations font du RadMon un instrument de référence pour la surveillance des rayonnements des champs mixtes complexes, tels que ceux rencontrés dans le LHC et sa chaîne d'injecteurs, mais aussi pour d'autres centres de recherche en physique des particules, comme JLAB aux États-Unis, J-PARC au JaponThe measurement of the radiation levels is an essential requirement in the LHC and its injection lines in order to quantify radiation effects on electronics and provide a detailed knowledge of the radiation field. The radiation monitoring system for the electronics at CERN, the “RadMon'', was installed in critical areas where equipment is or will be placed. Issues experienced in the last years of Radmon operation, the obsolescence of a few fundamental components of the electronic board and the necessity to improve both the accuracy and the resolution of measurements led to the launch of a new design of the monitor.This work describes the architecture of the new RadMon (V6), its reliability in radiation environments and the strategy adopted to choose and qualify the sensors, used for monitoring the mixed radiation field of the LHC accelerators. The CERN guidelines were adopted to qualify the RadMon components under radiation in order to develop a new architecture both more tolerant to radiation and more versatile than that of the previous version. In this context, the challenges that radiation tests impose for measuring Single Event Effects (SEUs) on a complex mixed-signal component such as the Analog to Digital converter, led to the development of an innovative test technique, which will be described in this thesis.The reliability of the RadMon measurements strongly depends on the calibration of its sensors. The complex radiation environment of the LHC imposes a peculiar qualification process which will be described and discussed in this work for the RadFets (Total Ionizing Dose sensor) and the SRAM memories (High Energy Hadrons fluence sensor).The use of the RadFet in a mixed field radiation environment has been studied and analyzed by means of 60Co sources as well as proton beams at different energies.The RadFets have been re-calibrated by studying the dose rate, particle sources, temperature, annealing and fading effects as a function of the oxide thickness. Furthermore, thanks to the new architecture of the RadMon, new biasing configurations have been tested to improve the resolution.Two types of SRAM memories with technology nodes of 400 and 90nm have been tested and calibrated by following a strict qualification methodology which includes tests with protons in the range 30-400 MeV, and with neutrons from thermal energies up to intermediate energies (~14 MeV). The 90nm memory improves the accuracy and resolution of the hadron fluence measurement. Moreover, the simultaneous use of both types of memories permits an improvement on the accuracy of the thermal neutron detection with respect to the previous version, as a result of a procedure which will be detailed in this work.The efforts towards the improvement of the TID measurements resolution for the new RadMon lead to the research and study of a new type of dosimeter sensor: the Floating Gate dosimeter (FGDOS). The sensor embeds complex circuitry, thus a full radiation qualification was necessary. Mixed field radiation tests, 60Co and protons tests have been carried out in order to evaluate the performance and the possible issues of the sensor. In this context, an analytical model of the sensor was developed to prove that the floating gate structure can be used as charge yield measurement instrument at room temperature and at low electric fields.The radiation tolerance characterization of the hardware, the qualification and calibration process of the sensors have significantly improved the overall reliability and quality of the measurements of the new RadMon. These improvements turned it into a reference instrument for radiation monitoring of complex mixed fields, such as the one encountered in the LHC, its injectors chain, and other particle physics research centers, such as JLAB in US, J-PARC in Japan
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Kemp, Pieter Stephanus. "The design of an analogue class-D audio amplifier using Z-domain methods." Thesis, Stellenbosch : Stellenbosch University, 2012. http://hdl.handle.net/10019.1/20084.
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Thesis (MScEng)--Stellenbosch University, 2012ENGLISH ABSTRACT: The class-D audio power amplifier has found widespread use in both the consumer and professional audio industry for one reason: efficiency. A higher efficiency leads to a smaller and cheaper design, and in the case of mobile devices, a longer battery life. Unfortunately, the basic class-D amplifier has some serious drawbacks. These include high distortion levels, a load dependent frequency response and the potential to radiate EMI. Except for EMI, the aforementioned issues can be mitigated by the proper implementation of global negative feedback. Negative feedback also has the potential to indirectly reduce EMI, since the timing requirements of the output devices can be relaxed. This thesis discusses the design of a clocked analogue controlled pulse-width modulated class-D audio amplifier with global negative feedback. The analogue control loop is converted to the z-domain by modelling the PWM comparator as a sampling operation. A method is implemented that improves clip recovery and ensures stability during over-modulation. Loop gain is shaped to provide a high gain across the audio band, and ripple compensation is implemented to minimize the negative effect of ripple feedback. Experimental results are presented.
AFRIKAANSE OPSOMMING: Die klas-D klankversterker geniet wydverspreide gebruik in beide die verbruiker en professionele oudio industrie vir een rede: benuttingsgraad. ’n Hoër benuttingsgraad lei tot ’n kleiner en goedkoper ontwerp, en in die geval van draagbare toestelle, tot langer batterylewe. Ongelukkig het die basiese klas-D klankversterker ernstige tekortkominge, naamlik hoë distorsievlakke, ’n lasafhanklike frekwensierespons en die vermoë om EMI te genereer. Behalwe vir EMI kan hierdie kwessies deur die korrekte toepassing van globale negatiewe terugvoer aangespreek word. Negatiewe terugvoer het ook die potensiaal om EMI indirek te verminder, aangesien die tydvereistes van die skakel stadium verlaag kan word. Hierdie tesis bespreek die ontwerp van ’n geklokte analoog-beheerde pulswydte-modulerende klas-D klankversterker met globale negatiewe terugvoer. Die analoogbeheerlus word omgeskakel na die z-vlak deur die PWM vlakvergelyker as ’n monster operasie te modelleer. ’n Metode word geïmplementeer wat die stabiliteit van die lus verseker tydens oormodulasie. Die lusaanwins word gevorm om ’n hoë aanwins in die oudioband te verseker en riffelkompensasie word geïmplementeer om die negatiewe effek van terugvoerriffel teen te werk. Eksperimentele resultate word voorgelê.
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Flippin, Stefanie Lee. "Synthesis of phospholipid analogs /." Electronic version (PDF), 2003. http://dl.uncw.edu/etd/2003/flippins/stefanieflippin.pdf.
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Hematy, Arman. "Digitally programmable analog log-domain filters." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=21302.
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Frequency filtering networks have numerous applications in consumer products. For high-speed and low-voltage systems, continuous-time filters are the preferred choice---these filters have become very popular with the wireless industry. Unfortunately, continuous-time filters have a high production cost since they are not geared toward mass production. This thesis proposes an analog filter structure that can be both mass produced and customized for a particular application. Such a structure is possible through the use of a state-space approach, and log-domain filtering.First, a general state-space formulation is presented; a method of obtaining the state-space coefficients from an equivalent LC ladder network is described. Such a set of coefficients results in a realization with low noise and low sensitivity properties. Next, the effects of coefficient quantization on a state-space filter's response is examined. An optimization procedure is outlined to obtain the best approximation to the desired transfer function.
In order to implement the proposed filter structure, a universal log-domain cell is presented. Such a cell can be used to produce the stages required by any filter design (input, output, and integrator stages). Using the universal log-domain cell, a systematic approach to realizing any arbitrary-order filter is described. Next, the peripheral components needed to complete the filter are presented. Included are a novel 8-bit DAC, used to implement the programmable current sources that bias the filter, and V-to-I and I-to-V converters, used to interface the current-mode filter with voltage-mode instruments.
Finally, experimental results from several prototype boards are used to verify the feasibility of the proposed filter structure. These boards make use of ICs fabricated in a 0.8 mum BiCMOS technology; included are an IC with stand-alone programmable current sources, an IC with a third-order filter, as well as one with a fifth-order filter. The results from the test boards clearly demonstrate the programmability and functionality of digitally programmable state-space filters.
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Hawrysh, Evan M. (Evan Mark). "Digital architectures for analog signal generation." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=24058.
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Analog and mixed-signal testing is far more complex than its digital equivalent. This thesis will identify the analog test requirements through an extensive analysis of integrated circuit testing, possible error sources, and the different levels of test hierarchy. The results will show that analog testing requires spectrally pure, high-quality predictable test signals. These signals are most robust when reproduced through digital techniques such as direct digital frequency synthesis. Delta-sigma ($ Delta Sigma$) modulation is perhaps the most versatile technique, as it can precisely encode arbitrary analog waveforms into a pulse-density modulated (PDM), infinite-length, single bit-wide pattern. The noise-shaping characteristics of the $ Delta Sigma$ modulator also allow for simple reconstruction of the embedded signal. Unfortunately, on-chip signal generation using this method is currently hindered by the high area overhead and limited programmability of $ Delta Sigma$ modulation oscillators. We will introduce the concept of forcing the PDM pattern to be finite in length and thus periodic. Although other periodic encoding algorithms exist, forced-periodic PDM patterns will be shown to be far superior for their precise control over signal amplitude, frequency, phase, and also for their ability to encode an arbitrary waveform. Its effectiveness will be demonstrated with several experiments of single- and multi-tone waveforms of varying degrees of complexity. By creating a fixed-length pattern, we can take advantage of many common digital built-in self-test (BIST) concepts such as scan and RAMBIST, found on most digital and mixed-signal integrated circuits, to supply the necessary hardware. We will show how analog signal generation can be integrated into digital ICs using any or all of the IEEE 1149.1-1990 standard, embedded RAMs, and scan chains. These applications will indeed prove that with very little additional hardware, on-chip, high-quality analog signal gene
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Deese, Anthony Steven Nwankpa Chika O. "Analog methods for power system analysis and load modeling /." Philadelphia, Pa. : Drexel University, 2008. http://hdl.handle.net/1860/2822.
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Martins, Tomás V. "Analog and digital control of an electronic throttle valve." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/71507.
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Thesis (S.B.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2012.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 32).
Two electronic throttler controllers were designed and implemented for an automotive throttle valve on a four-cylinder, spark-ignition gasoline engine. The first controller was designed using operational amplifiers and other analog componentry to realize a proportional-integral controller and feedback loop. The second controller utilized a programmable digital microcontroller to replace the analog componentry for signal processing. The use of analog to digital signal conversion by the microcontroller allows for the simple implementation of control logic and feedback loops through programming. Additionally, control architecture and characteristic gains implemented in the controller's code can be quickly changed and uploaded during testing. The digital controller was tested on the engine's throttle valve during motoring to demonstrate its actuation capabilities and response times. The digital controller was programmed to quickly switch between different feedback signals like throttle angle, manifold pressure, and indicated mean effective pressure for control. The controller was designed for use in experimental testing of an experimental 2.0 liter, GM EcoTec engine in the Sloan Automotive Laboratory at MIT. This study shows that rapid controller prototyping can be accomplished by using an inexpensive microcontroller for signal processing. This design concept greatly decreases implementation time and performance optimization time, increases controller flexibility and capabilities, and maintains favorable response characteristics.
by Tomás V. Martins.
S.B.
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Ishida, Yoichi. "Secret analogies mathematics, ecology, and evolution /." abstract and full text PDF (free order & download UNR users only), 2007. http://0-gateway.proquest.com.innopac.library.unr.edu/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:1442878.
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Yengui, Firas. "Contribution aux méthodologies et outils d’aide à la conception de circuits analogiques." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0098/document.
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A la différence de la conception numérique, la conception analogique souffre d’un réel retard au niveau de la solution logicielle qui permet une conception à la fois rapide et fiable. Le dimensionnement de circuits analogiques exige en effet un nombre assez élevé de simulations et de vérifications et dépend beaucoup de l’expertise du concepteur. Pour pallier à ce retard, des outils de conception automatique basés sur des algorithmes d’optimisation locale et globale sont développés. Ces outils restent encore immatures car ils n’offrent que des réponses partielles aux questions du dimensionnement, alors que l’obtention d’un dimensionnement optimal d’un circuit analogique en un temps raisonnable reste toujours un enjeu majeur. La réduction du temps de conception de circuits analogiques intégrés nécessite la mise en place de méthodologies permettant une conception systématique et automatisable sur certaines étapes. Dans le cadre de cette thèse, nous avons travaillé suivant trois approches. Il s’agit d’abord de l’approche méthodologique. A ce niveau nous préconisons une approche hiérarchique descendante « top-down ». Cette dernière consiste à partitionner le système à dimensionner en sous blocs de fonctions élémentaires dont les spécifications sont directement héritées des spécifications du niveau système. Ensuite, nous avons cherché à réduire le temps de conception à travers l’exploration de solutions optimales à l’aide des algorithmes hybrides. Nous avons cherché à profiter de la rapidité de la recherche globale et de la précision de la recherche locale. L’intérêt des algorithmes de recherche hybride réside dans le fait qu’ils permettent d’effectuer une exploration efficace de l’espace de conception du circuit sans avoir besoin d’une connaissance préalable d’un dimensionnement initial. Ce qui peut être très intéressant pour un concepteur débutant. Enfin, nous avons travaillé sur l’accélération du temps des simulations en proposant l’utilisation des méta-modèles. Ceux-ci présentent un temps de simulation beaucoup plus réduit que celui des simulations des modèles électriques. Les méta-modèles sont obtenus automatiquement depuis une extraction des résultats des simulations électriquesContrary to digital design, analog design suffers from a real delay in the software solution that enables fast and reliable design. In this PhD, three approaches are proposed. The first is the methodological approach. At this level we recommend a "top-down" hierarchical approach. It consists of partitioning the system to size into sub-blocks of elementary functions whose specifications are directly inherited from the system level specification. Next, we aimed to reduce design time through the exploration of optimal solutions using hybrid algorithms. We attempted to take advantage of the rapid global search and local search accuracy. The interest of hybrid search algorithms is that they allow to conduct effective exploration of the design space of the circuit without the need for prior knowledge of an initial design. This can be very useful for a beginner designer. Finally, we worked on the acceleration of time simulations proposing the use of meta-models which present a more reduced time than electrical simulation models. Meta-models are obtained automatically from extracting results of electrical simulations
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Minteer, Timothy Michael. "Electromagnetic modeling based on directional time-distance energy transfer analogies." Thesis, Washington State University, 2013. http://pqdtopen.proquest.com/#viewpdf?dispub=3587146.
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A new electromagnetic model is established based on an average rate of directional time-distance energy transfers. A directional time-distance energy transfer is defined as an energy carrier mediator (boson) exchange. Electromagnetic force is modeled as mean valued, continual emission and absorption of energy carrier mediators.
For an isolated, spherically symmetric static charge distribution, Maxwell's stress equation is recast using a variant of Stokes' Theorem. The recast stress equation eliminates the stress normal to the electric field and establishes a stress only aligned with the electric field. The remaining stress is identified as an external omnidirectional Poincaré stress, inwardly directed towards the charge distribution. The Poincaré stress is modeled as a mean valued, continual exchange of bosons between the charge distribution and the distant matter of the universe.
For two separated, spherically symmetric static charge distributions, Maxwell's stress equation is recast using a variant of Stokes' Theorem. The recast stress equation develops a line stress that only exists on the straight path between the two charge distributions. The line stress is identified as a Coulomb stress modeled as a mean valued, continual exchange of photons back and forth between two like-charge distributions.
For an isolated, differential current element, Maxwell's stress equation is recast using a variant of Stokes' Theorem. The recast stress equation establishes a pinch stress that is normal to the magnetic field and is directed inward toward the differential current element. Similar to the Poincaré stress, the pinch stress is omnidirectional and is modeled as a mean valued, continual exchange of bosons between the current element and the distant matter of the universe.
For two separated, static differential current elements, a Neumann stress is established by analyzing the historical current force formulas known to be compatible with Maxwell's equations for closed circuits. The term Neumann stress is assigned to the line stress that only exists at each point on the straight path between two separated, differential current elements. Similar to the Coulomb stress, the Neumann stress is modeled as a mean valued, continual exchange of photons back and forth between two differential current elements in opposite directions.
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Lu, Albert K. (Albert Keishi). "Analog signal generation using delta-sigma modulation." Thesis, McGill University, 1994. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=68040.
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This thesis introduces a method by which low-frequency analog waveforms may be generated using delta-sigma modulation. The technique centers around a delta-sigma based oscillator which, with the exception of a continuous-time low-pass filter, is entirely digital and provides precise control over the oscillation frequency, amplitude, and phase. The incorporation of a delta-sigma modulator inside the resonator loop leads to an efficient implementation requiring 4 multi-bit adders, 4 delay elements, and a 2-input multiplexer. Two additional circuits, which generate multi-tone and piece-wise linear waveforms, are presented as extensions of the original single-tone design.Prototypes of the proposed designs have been assembled using Field-Programmable Gate Array, and BiCMOS technologies. The test results have successfully verified the validity of the proposed concepts indicating dynamic ranges exceeding 80 dB and 60 dB for the single and multi-tone generators respectively.