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1
Hamid, Fazrena Azlee. "Architectural synthesis of analogue filters from behavioural VHDL-AMS descriptions." Thesis, University of Southampton, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.422985.
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Wang, Shiwei. "Biomimetic cochlea filters : from modelling, design to analogue VLSI implementation." Thesis, University of Edinburgh, 2014. http://hdl.handle.net/1842/9695.
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This thesis presents a novel biomimetic cochlea filter which closely resembles the biological cochlea behaviour. The filter is highly feasible for analogue very-large-scale integration (VLSI) circuits, which leads to a micro-watt-power and millimetre-sized hardware implementation. By virtue of such features, the presented filter contributes to a solid foundation for future biologically-inspired audio signal processors. Unlike existing works, the presented filter is developed by taking direct inspirations from the physiologically measured results of the biological cochlea. Since the biological cochlea has prominently different characteristics of frequency response from low to high frequencies, the biomimetic cochlea filter is built by cascading three sub-filters accordingly: a 2nd-order bandpass filter for the constant gentle low-frequency response, a 2nd-order tunable low-pass filter for the variable and selective centre frequency response and a 5th-order elliptic filter for the ultra-steep roll-off at stop-band. As a proof of concept, a biomimetic cochlea filter bank is built to process audio signals, which demonstrates the highly discriminative spectral decomposition and high-resolution time-frequency analysis capabilities similar to the biological cochlea. The filter has simple representation in the Laplace domain which leads to a convenient analogue circuit realisation. A floating-active-inductor circuit cell is developed to build the corresponding RLC ladder for each of the three sub-filters. The circuits are designed based on complementary metal-oxide-semiconductor (CMOS) transistors for VLSI implementation. Non-ideal factors of CMOS transistors including parasitics, noise and mismatches are extensively analysed and consciously considered in the circuit design. An analogue VLSI chip is successfully fabricated using 0.35μ m CMOS process. The chip measurements demonstrate that the centre frequency response of the filter has about 20 dB wide gain tuning range and a high quality factor reaching maximally over 19. The filter has a 20 dB/decade constant gentle low-frequency tail and an over 300 dB/decade sharp stop-band roll-off slope. The measured results agree with the filter model expectations and are comparable with the biological cochlea characteristics. Each filter channel consumes as low as 59.5 ~90μ Wpower and occupies only 0.9 mm2 area. Besides, the biomimetic cochlea filter chip is characterised from a wide range of angles and the experimental results cover not only the auditory filter specifications but also the integrated circuit design considerations. Furthermore, following the progressive development of the acoustic resonator based on microelectro- mechanical systems (MEMS) technology, a MEMS-CMOS implementation of the proposed filter becomes possible in the future. A key challenge for such implementation is the low sensing capacitance of the MEMS resonator which suffers significantly from sensitivity degradation due to the parasitic capacitance. A novel MEMS capacitive interface circuit chip is additionally developed to solve this issue. As shown in the chip results, the interface circuit is able to cancel the parasitic capacitance and increase the sensitivity of capacitive sensors by 35 dB without consuming any extra power. Besides, the chopper-stabilisation technique is employed which effectively reduces the circuit flicker noise and offsets. Due to these features, the interface circuit chip is capable of converting a 7.5 fF capacitance change of a 1-Volt-biased 0.5 pF capacitive sensor pair into a 0.745 V signal-conditioned output while consuming only 165.2μ W power.
3
Taylor, D. Cameron. "Controllable, analogue, three-dimensional mixed domain linear trajectory filters for video signals." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/mq20886.pdf.
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O'Carroll, A. P. "A study of the higher-frequency performance of operational-amplifier analogue filters : active-RC and active-R filter sections using integrated operational amplifiers are investigated up to the medium frequency communications band by consideration of." Thesis, University of Bradford, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.235719.
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Williams, Sean Barry Kelly. "Electronic music instrument practice and the mechanisms of influence between technical design, performance practice and composition." Thesis, University of Edinburgh, 2012. http://hdl.handle.net/1842/7890.
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This thesis examines the practices and techniques involved with particular electronic instruments and proposes an archaeological approach to reconsider the ways in which noise can communicate various details of instrument design and practice to the listener. I present two case studies concerning electronic music practice using repurposed devices - stepped filters - and by combining a detailed material analysis of the instruments with interviews, video and other evidence, I document the practices involved with their use. By rebuilding these instruments, and designing and building other devices, I test my hypotheses through my own practice, and by doing so I refine my results and extend my composition, performance practice and technical design skills to include valuable lessons learned through this research. The portfolio engages with the three archaeological levels (Listening Situation, Reproduction Stage, Production Environment) and the three areas of the production continuum (Composition, Performance Practice, Technical Design) and through sound installations, crafted media, recorded performances, and the documentation of devices designed for these pieces, it supports the thesis through experimentation and incorporation of results through reflective practice.
6
Shadrin, Aleksandr. "Analogové pole pro realizaci programovatelného filtru." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-221026.
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The state-variable analog filter topologies are described. Using the transfer function theory and operational configurations suitable for integration and derivation, a new universal filter topology are proposed. The circuit has been implemented in CMOS technology by using six operational amplifiers, eight analog switches and five programming resistor array. Tunable corner frequencies, quality factors and gain are realized. Using the serial peripheral interface or digital memory can be realized this real-time digitally programmable first- and second-order analog filter with the tunable parameters.
7
Hematy, Arman. "Digitally programmable analog log-domain filters." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=21302.
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Frequency filtering networks have numerous applications in consumer products. For high-speed and low-voltage systems, continuous-time filters are the preferred choice---these filters have become very popular with the wireless industry. Unfortunately, continuous-time filters have a high production cost since they are not geared toward mass production. This thesis proposes an analog filter structure that can be both mass produced and customized for a particular application. Such a structure is possible through the use of a state-space approach, and log-domain filtering.First, a general state-space formulation is presented; a method of obtaining the state-space coefficients from an equivalent LC ladder network is described. Such a set of coefficients results in a realization with low noise and low sensitivity properties. Next, the effects of coefficient quantization on a state-space filter's response is examined. An optimization procedure is outlined to obtain the best approximation to the desired transfer function.
In order to implement the proposed filter structure, a universal log-domain cell is presented. Such a cell can be used to produce the stages required by any filter design (input, output, and integrator stages). Using the universal log-domain cell, a systematic approach to realizing any arbitrary-order filter is described. Next, the peripheral components needed to complete the filter are presented. Included are a novel 8-bit DAC, used to implement the programmable current sources that bias the filter, and V-to-I and I-to-V converters, used to interface the current-mode filter with voltage-mode instruments.
Finally, experimental results from several prototype boards are used to verify the feasibility of the proposed filter structure. These boards make use of ICs fabricated in a 0.8 mum BiCMOS technology; included are an IC with stand-alone programmable current sources, an IC with a third-order filter, as well as one with a fifth-order filter. The results from the test boards clearly demonstrate the programmability and functionality of digitally programmable state-space filters.
8
Hematy, Arman. "Digitally programmable analog log-domain filters." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0024/MQ50621.pdf.
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Bragina, Tatiana. "Návrh laditelného kmitočtového filtru 2. řádu se spínanými kapacitory." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-221041.
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Thesis describes analog filters topologies with capability of tuning of the main parameters and the MOSFET-C and switched-capacitor filters are described. With focus to linearity and maximal tuning range optimal topology have been chosen. In work the issue of analog switch design is described and is solved. Design of switched-capacitor low-pass Sallen-key filter in Cadence software was made and simulation results are presented.
10
Kucic, Matthew R. "Analog programmable filters using floating-gate arrays." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13755.
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Park, Shinwoong. "Reconfigurable Discrete-time Analog FIR filters for Wideband Analog Signal Processing." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/99794.
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Demand for data communication capacity is rapidly increasing with more and more number of users and higher bandwidth services. As a result, a critical research issue is the implementation of wideband and flexible signal processing in communication and sensing applications. Although software defined radio (SDR) is a possible solution, it may not be practical due to the excessive requirements for analog-to-digital converter (ADCs) and digital filters for wideband signals. In this environment, discrete-time (DT) domain circuits are gaining attention in various architectures such as N-path filters, sampling mixers, and analog FIR/IIR/FFT filters. DT analog signal processing (DT-ASP) ahead of an ADC considerably relaxes the ADC requirements by flexible filtering, offers the potential for higher dynamic range performance, and provides robustness in the presence of digital CMOS scaling.
The primary work presented in this dissertation is the design of wideband analog finite impulse response (AFIR) filters. Analog FIR filters have been used as low pass filters for out-of-band rejection in narrow-band applications. However, this work seeks to develop AFIR filters suitable for wideband applications, extending its possible applications. To achieve these performance goals, capacitive digital to analog converters (CDACs) have been introduced for the first time as wideband analog coefficient multipliers, which has led to high linearity analog multiplication with coefficient selection at the DAC resolution. A prototype 4th order DT FIR filter has been implemented in 32nm SOI CMOS technology and has achieved low-pass, band-pass, and high-pass filter (LPF, BPF and HPF) transfer functions corresponding to the programmed coefficient sets with IIP3>11dBm linearity and less than 2 mW/tap of power consumption. The AFIR filter is also utilized to demonstrate a proof-of-concept FIR-based beamforming. The beamforming network consisting of 4 antenna element inputs followed by AFIR filters was implemented with PCB modules with the previously fabricated AFIR filter chip. Behavioral simulations are used to verify the beamforming function with given coefficient sets. Based on the developed AFIR filter modules, FIR-based beamforming was demonstrated with measurement results matching well with the simulations.
Further work presented is the design and optimization of multi-section CDAC (MS-CDAC) structures. The proposed MS-CDAC approach provides wide range of options to optimize the tradeoff between kT/C noise, linearity versus switching energy, speed and area. When the optimization approach is applied to a proof-of-concept 10-bit CDAC design, the selected MS-CDAC structure reduces total capacitance and switching energy by 97% and 98%, respectively for given linearity and noise limitations. The proposed MS-CDAC structures are applicable in both DT-ASP coefficient multiplier and SAR-ADC applications.PHD
12
Přibyl, Libor. "Digitální mixážní pult." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2018. http://www.nusl.cz/ntk/nusl-376976.
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The presented work deals with the issue of digital mixing console. The main focus is on the design of sub-circuits for the digital mixer and the construction into the 19 "rack unit. The thesis presents a detailed description of individual parts and their use. Thesis also includes complete device designs, including a power supply and additional circuits.
13
Vrba, Adam. "Analýza a realizace kmitočtového filtru přeladitelného změnou parametru aktivního prvku." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218675.
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This work analyzes tuning capabilities of different fully integrated active filter topologies. Work only deals with continuous time active filters. Topologies described in this work differ in type of active element and in method of frequency tuning. Techniques of tunning are proved on second order low pass filter. Filter topologies are compared from tunning capabilities and from point of total harmonic distortion. The main building block of all filters is integrator.
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Lesellier, Amandine. "Contribution à l'étude des architectures de récepteurs large bande multi-canaux." Thesis, Paris Est, 2013. http://www.theses.fr/2013PEST1015/document.
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Cette thèse est le fruit d'un partenariat entre la BL TVFE de NXP Semiconductors et l'ESIEE dans le cadre d'une thèse CIFRE. Le but est d'apporter une solution qui permette la réception de plusieurs canaux pour le câble. Ce sujet est lié à la problématique de numérisation large bande. Dans la première partie, nous faisons un état-de-l'art sur les convertisseurs analogiques-numériques (CAN), sur les architectures parallèles (entrelacement temporel et bancs de filtres hybrides (BFH)), et sur les méthodes d'échantillonnage (passe-bande et complexe). Puis, nous étudions une architecture composée d'un banc de filtres analogiques et un banc de CANs. Nous cherchons à réduire surtout le taux d'échantillonnage. Nous comparons notre solution à un CAN large bande performant, avec notre fonction de coût. L'un des avantages de cette architecture est que tous les composants sont faisables, même les CANs, et qu'il est possible d'éteindre des sous-bandes pour diminuer la consommation. Cette solution est intéressante pour le moment mais n'est pas compétitive en termes de consommation et de surface. Nous proposons une alternative dans la partie 3, avec les BFH. Nous étudions cette architecture, en gardant à l'esprit la faisabilité de la solution. Nous avons choisi un BFH à deux voies, avec un filtre analogique passe-bas et un passe-haut. Puis, nous proposons un algorithme d'optimisation des filtres de synthèse pour atteindre nos objectifs de distorsion et de réjection de repliement. Une identification des filtres analogiques est aussi présentée. Finalement, une réalisation physique prouve le concept et valide les limitations théoriques de cette architectureThis thesis is a partnership between the BL TVFE of NXP Semiconductors and ESIEE. Its goal is to provide a solution to multi-channel reception for cable network. This is linked to the problematic of broadband digitization. In the first part, the state-of-the art of ADCs, parallel architectures (TI and HFB) and sampling methods (bandpass sampling and complex sampling) is recalled. Then we study an architecture called RFFB with a bank of analog filters and a bank of ADCs. We try to reduce the constraints on ADCs, especially the sampling rate with the different sampling. We propose an interesting solution to broadband digitization and compare this solution to a challenging wideband ADC, using the cost function we introduce. This architecture has the major advantage that all the components are feasible, even the ADCs, and it is possible to switch-off subbands to save power. It could be a good solution at the present time but it is not competitive in terms of power consumption and surface. An alternative is proposed in Part 3, where we study Hybrid Filter Banks. It is interesting to study this architecture with realization feasibility in mind. This is why we select a 2-channel HFB with a lowpass filter and a highpass filter as analog filters. Then we propose an efficient optimization algorithm to find the best synthesis filters and reach our targets of distortion and aliasing rejection. An identification of analog filters is also suggested to cope with the issue of sensitivity to analog errors. Finally, a physical realization proves the concept of aliasing rejection and confirms the theoretical issues of this architecture
15
Velazquez, Scott Richard. "Hybrid filter banks for analog/digital conversion." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/10436.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (leaves 288-291).
by Scott Richard Velazquez.
Ph.D.
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Kumar, Ajay. "A wide dynamic range high-q high-frequency bandpass." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28126.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Allen Phillip; Committee Member: Hasler Paul; Committee Member: Keezer David; Committee Member: Kenny James; Committee Member: Pan Ronghua.
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Huang, Jingyu. "Design of analog receive filters for 1000BASE-T Gigabit Ethernet /." For electronic version search Digital dissertations database. Restricted to UC campuses. Access is free to UC campus dissertations, 2005. http://uclibs.org/PID/11984.
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Robinson, David Lyle. "Automatic Synthesis of VLSI Layout for Analog Continuous-time Filters." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4913.
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Automatic synthesis of digital VLSI layout has been available for many years. It has become a necessary part of the design industry as the window of time from conception to production shrinks with ever increasing competition. However, automatic synthesis of analog VLSI layout remains rare. With digital circuits, there is often room for signal drift. In a digital circuit, a signal can drift within a range before hitting the threshold which triggers a change in logic state. The effect of parasitic capacitances for the most part, hinders the timing margins of the signal, but not its functionality. The logic functionality is protected by the inherent noise immunity of digital circuits. With analog circuits, however, there is little room for drift. Parasitic influence directly affects signal integrity and the functionality of the circuit. The underlying problem automatic VLSI layout programs face is how to minimize this influence. This thesis describes a software tool that was written to show that the minimization of parasitic influence is possible in the case of automatic layout of continuous-time filters using transconductance-capacitor methods.
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Yoo, Seoung-Jae. "Design of analog baseband circuits for wireless communication receivers." Columbus, Ohio Ohio State University, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1073617255.
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Thesis (Ph. D.)--Ohio State University, 2004.Title from first page of PDF file. Document formatted into pages; contains xvi, 167 p.; also includes graphics (some col.). Includes abstract and vita. Advisor: Mohammed Ismail ElNaggar, Dept. of Electrical Engineering. Includes bibliographical references (p. 163-167).
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Sumesaglam, Taner. "Automatic tuning of continuous-time filters." Diss., Texas A&M University, 2004. http://hdl.handle.net/1969.1/1055.
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Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.
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Langhammer, Lukáš. "Plně diferenční kmitočtové filtry s moderními aktivními prvky." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-256565.
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Tato disertační práce se zaměřuje na výzkum v oblasti frekvenčních filtrů. Hlavním cílem je navrhnout a analyzovat plně diferenční kmitočtové filtry pracující v proudovém módu a využívající moderní aktivní prvky. Prezentované filtry jsou navrženy za použití proudových sledovačů, operačních transkonduktančních zesilovačů, plně diferenčních proudových zesilovačů a transrezistančních zesilovačů. Návrh se zaměřuje na možnost řídit některý z typických parametrů filtru pomocí řiditelných aktivních prvků, které jsou vhodně umístněny do obvodové struktury. Jednotlivé prezentované filtry jsou navrženy v nediferenční a diferenční verzi. Velký důraz je věnován srovnání plně diferenčních struktur s jejich odpovídajícími nediferenčními formami. Funkčnost jednotlivých návrhů je ověřena simulacemi a v některých případech i experimentálním měřením.
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Ramachandran, Arun. "Nonlinearity and noise modeling of operational transconductance amplifiers for continuous time analog filters." Texas A&M University, 2003. http://hdl.handle.net/1969.1/3925.
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A general framework for performance optimization of continuous-time OTA-C
(Operational Transconductance Amplifier-Capacitor) filters is proposed. Efficient
procedures for evaluating nonlinear distortion and noise valid for any filter of arbitrary
order are developed based on the matrix description of a general OTA-C filter model .
Since these procedures use OTA macromodels, they can be used to obtain the results
significantly faster than transistor-level simulation. In the case of transient analysis, the
speed-up may be as much as three orders of magnitude without almost no loss of
accuracy. This makes it possible to carry out direct numerical optimization of OTA-C
filters with respect to important characteristics such as noise performance, THD, IM3,
DR or SNR. On the other hand, the general OTA-C filter model allows us to apply
matrix transforms that manipulate (rescale) filter element values and/or change topology
without changing its transfer function. The above features are a basis to build automated
optimization procedures for OTA-C filters. In particular, a systematic optimization
procedure using equivalence transformations is proposed. The research also proposes
suitable software implementations of the optimization process. The first part of the
research proposes a general performance optimization procedure and to verify the
process two application type examples are mentioned. An application example of the
proposed approach to optimal block sequencing and gain distribution of 8th order
cascade Butterworth filter (for two variants of OTA topologies) is given. Secondly the
modeling tool is used to select the best suitable topology for a 5th order Bessel Low Pass
Filter. Theoretical results are verified by comparing to transistor-level simulation withCADENCE. For the purpose of verification, the filters have also been fabricated in
standard 0.5mm CMOS process.
The second part of the research proposes a new linearization technique to
improve the linearity of an OTA using an Active Error Feedforward technique. Most
present day applications require very high linear circuits combined with low noise and
low power consumption. An OTA based biquad filter has also been fabricated in 0.35mm
CMOS process. The measurement results for the filter and the stand alone OTA have
been discussed. The research focuses on these issues.
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Javidan, Mohammad. "Conception des modulateurs sigma-delta d'ordre élévé pour des convertisseurs analogique-numérique en parallèle." Phd thesis, Université Paris Sud - Paris XI, 2009. http://tel.archives-ouvertes.fr/tel-00469483.
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Dans ce travail intitulé « Conception de modulateurs Sigma-Delta d'ordre élevé pour convertisseurs analogique-numérique en parallèle », les travaux ont été menés dans le contexte de la radio logicielle. La voie proposée pour la réalisation du convertisseur analogique-numérique, élément clé et bloquant de la radio logicielle, est une structure composée de plusieurs modulateurs sigma-delta passe-bande à temps continu mis en parallèle. Après avoir énuméré les différentes spécifications auxquelles le modulateur doit satisfaire, une nouvelle méthodologie de design à été proposé. Un état de l'art des différentes technologies de réalisation des filtres du modulateur a été réalisé, aboutissant à l'utilisation de résonateurs à filtres à ondes d'onde de Lamb. Les caractéristiques de ce résonateur ont été présentées ainsi qu'un circuit de commande permettant la compensation des inconvénients. Après avoir défini une novelle topologie et le résonateur, une méthode pour optimiser les performances de chaque modulateur en fonction des imperfections de l'électronique utilisée pour l'implémentation en fonction de la fréquence centrale de chacun d'entre eux a été proposé. Un travail d'analyse permettant de mettre en évidence l'influence de chacun des défauts électroniques importants sur les performances globales du modulateur, que ce soit en termes de résolution ou de stabilité, a été développé. Le comportement de la fonction de transfert de signal (STF) du système optimisé ne correspond pas à un filtre sélecteur de bande. Une modification originale de la topologie du modulateur permettant l'amélioration de la réponse en fréquence de la STF sans modifier la fonction de transfert du bruit (NTF) a été proposée. Enfin, la réalisation d'un modulateur sigma-delta à temps continu du deuxième ordre au niveau layout a été effectuée. La réduction de l'ordre est justifiée par le fait que l'intégration d'un filtre à onde de Lamb n'est pas encore un processus bien maitrisé et que son utilisation dans un sixième ordre pourrait aboutir à un circuit inexploitable en termes d'analyse.
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Yoo, Seoung Jae. "Design of analog baseband circuits for wireless communication receivers." The Ohio State University, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=osu1073617255.
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Fischer, Timothy W. "An analog approach to interference suppression in ultra-wideband receivers." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5769.
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Because of the huge bandwidth of Ultra-Wideband (UWB) systems, in-band narrowband
interference may hinder receiver performance. In this dissertation, sources
of potential narrowband interference that lie within the IEEE 802.15.3a UWB bandwidth
are presented, and a solution is proposed. To combat interference in Multi-Band
OFDM (MB-OFDM) UWB systems, an analog notch filter is designed to be included
in the UWB receive chain. The architecture of the filter is based on feed-forward
subtraction of the interference, and includes a Least Means Squared (LMS) tuning
scheme to maximize attenuation. The filter uses the Fast Fourier Transform (FFT)
result for interference detection and discrete center frequency tuning of the filter. It
was fabricated in a 0.18 õm process, and experimental results are provided. This is
the first study of potential in-band interference sources for UWB. The proposed filter
offers a practical means for ensuring reliable UWB communication in the presense of
such interference.
The Operational Transconductance Amplifier (OTA) is the predominant building
block in the design of the notch filter. In many cases, OTAs must handle input
signals with large common mode swings. A new scheme for achieving rail-to-rail
input to an OTA is introduced. Constant gm is obtained by using tunable level
shifters and a single differential pair. Feedback circuitry controls the level shifters
in a manner that fixes the common mode input of the differential pair, resulting in consistent and stable operation for rail-to-rail inputs. As the new technique avoids
using complimentary input differential pairs, this method overcomes problems such
as Common Mode Rejection Ratio (CMRR) and Gain Bandwidth (GBW) product
degradation that exist in many other designs. The circuit was fabricated in a 0.5õm
process. The resulting differential pair had a constant transconductance that varied
by only ñ0.35% for rail-to-rail input common mode levels. The input common mode
range extended well past the supply levels of ñ1.5V, resulting in only ñ1% fluctuation
in gm for input common modes from -2V to 2V.
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Sadeghifar, Mohammad Reza. "On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters." Licentiate thesis, Linköpings universitet, Elektroniska Kretsar och System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-114274.
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High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element. In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work. ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement. Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line. In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.
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Lacy, Cameron. "Design of a programmable switched-capacitor analog FIR filter." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0007/MQ46200.pdf.
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Jeon, Okjune. "Analog baseband processor for CMOS 5-GHz WLAN receiver." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0013035.
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Ohlsson, Henrik. "Studies on Design and Implementation of Low-Complexity Digital Filters." Doctoral thesis, Linköping : Dept. of Electrical Engineering, Univ, 2005. http://www.ep.liu.se/diss/science_technology/09/49/index.html.
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Vadnerkar, Sarang. "An Algorithm for the design of a programmable current mode filter cell." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1261601029.
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Kwan, Hing-kit. "Design algorithms for delta-sigma modulator loop filter topologies." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B4150883X.
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Dugger, Jeffery Don. "Adaptive Analog VLSI Signal Processing and Neural Networks." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5294.
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Research presented in this thesis provides
a substantial leap from the study of interesting
device physics to fully adaptive analog networks
and lays a solid foundation for future development
of large-scale, compact, low-power adaptive parallel
analog computation systems.
The investigation described here started with
observation of this potential learning capability
and led to the first derivation and characterization of
the floating-gate pFET correlation learning rule.
Starting with two synapses sharing the same error signal,
we progressed from phase correlation experiments
through correlation experiments involving harmonically related sinusoids,
culminating in learning the Fourier series coefficients
of a square wave cite{kn:Dugger2000}.
Extending these earlier two-input node experiments to the general case
of correlated inputs required dealing with
weight decay naturally exhibited by the learning rule.
We introduced a source-follower floating-gate synapse
as an improvement over our earlier source-degenerated floating-gate synapse
in terms of relative weight decay cite{kn:Dugger2004}.
A larger network of source-follower floating-gate synapses was fabricated
and an FPGA-controlled testboard was designed and built.
This more sophisticated system provides an excellent
framework for exploring applications to multi-input, multi-node
adaptive filtering applications.
Adaptive channel equalization provided
a practical test-case illustrating the use
of these adaptive systems in solving real-world problems.
The same system could easily be applied to noise and echo cancellation
in communication systems and system identification tasks in
optimal control problems.
We envision the commercialization of these adaptive analog VLSI
systems as practical products within a couple of years.
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Gruget, Alban. "Convertisseur à bancs de filtres hybrides utilisant des filtres à échantillonnage de charge pour applications de radio cognitive." Phd thesis, Télécom ParisTech, 2011. http://pastel.archives-ouvertes.fr/pastel-00679985.
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Ce travail de thèse s'inscrit dans un pro jet inter-Carnot intitulé TEROPP (Technologies for TERminals in OPPortunistic radio applications) financé par l'ANR de 2008 à 2011. L'objectif de ce projet était de concevoir les éléments clés d'un terminal reconfigurable adapté à la radio cognitive. Les travaux ont porté depuis les antennes jusqu'à l'aspect réseaux. Les travaux décrits dans cette thèse sont focalisés sur le "frontal" RF agile en fréquences multi-voies et s'intéresse plus particulièrement à la numérisation d'un signal large-bande via une architecture multi-voies. Nous avons proposé et étudié une nouvelle architecture basée sur la technique de banc de filtres hybride (BFH). Un BFH est une architecture parallèle à sous-échantillonnage qui met en jeu de l'analogique, i.e. des filtres analogiques et des convertisseurs analogique-numériques ainsi que du traitement numérique. L'originalité de l'architecture proposée est d'utiliser des filtres à échantillonnage de charge passe-bande pour les filtres analogiques. Ces filtres ont l'avantage d'être facilement intégrables en CMOS et reconfigurables. Une telle architecture devrait permettre de convertir une bande très large, tout en limitant la complexité et la consommation et offre des possibilités de reconfigurabilité en termes de bande reçue et résolution.
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Duke, Cole Victor. "Analog Feedback Control of Broadband Fan Noise." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/3646.
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Active noise control (ANC) has been implemented using analog filters to reduce broadband noise from a small axial cooling fan. Previous work successfully attenuated narrow-band, tonal portions of the noise using a digital controller. The practical performance limits of this system were reached and it was desirable to attenuate the noise further. Additional research, therefore, sought to attenuate broadband noise from the fan using a digital controller, but performance was limited by the group delay inherent in the digital signal processor (DSP). Current research attempts to further attenuate broadband noise and improve performance of the system by combining the tonal controller with an analog feedback controller. An analog controller is implemented in parallel with the digital controller without degrading the performance of either individual controller. Broadband noise is attenuated in a certain frequency region, but at the expense of increasing noise in adjacent frequency regions. Results show that a single-input single-output (SISO) controller is preferable to a multiple-input multiple-output (MIMO) controller for this system.
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Salášek, Jan. "Analogové funkční bloky fraktálního řádu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-241141.
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Thesis describes the design of the blocks of fractional-order filters approximation using a filter of higher order integer. Active filters of third-order are use to create filter of 1+alfa -order, where alfa is between zero to one. One of the filters is practically implemented and measured.
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Kwan, Hing-kit, and 關興杰. "Design algorithms for delta-sigma modulator loop filter topologies." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B4150883X.
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Allam, Mootaz Bellah Mohamed Mahmoud. "Convertisseur analogique-numérique ΣΔ à base VCO." Thesis, Paris 6, 2015. http://www.theses.fr/2015PA066299.
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Les systèmes de communication sans fil modernes exigent haute performance analogique Convertisseurs-numériques (CAN) avec l'augmentation de la bande passante et la résolution.Aujourd'hui, il y a un besoin croissant de faible puissance et de récepteurs RF multi-fonctionnels, puisque le marché s' attend à des capacités de réception complexes avec des appareils de faible puissance qui fonctionnent sur batteries portables de puissance limitée.Pour cette raison la tendance actuelle est de diminuer la partie analogique des récepteurs, tout en augmentant les tâches effectuées par la partie numérique.Par conséquent, cela demande des CAN à large bande, haute résolution et faible consommation.Dans cette recherche, on étudie plusieurs CAN à base de VCO.On montre la conception, la réalisation dans le process CMOS 65nm et les mesures de deux types de CAN à base VCO, le premier est basé sur le principe de la conversion tension-fréquence tandis que le second utilise le principe de la conversion tension-phase.Le CAN tension fréquence est un CAN de 4-bit programmable avec une fréquence d’échantillonnage qui va de 220MHz jusqu’à 1500MHz. le rapport signal dur bruit mesuré est de 40.5dB dans une bande de 30MHz avec une consommation de 0.5mW.Le CAN tension phase est un CAN de 4-bit programmable avec une fréquence d’échantillonnage qui va de 300MHz jusqu'a 1440MHz. le rapport signal dur bruit mesuré est de 48dB dans une bande de 30MHz avec une consommation de 1mW. On présente ensuite une méthode de conception systématique de conception des CAN SigmaDelta de grand ordre avec des quantificateurs à base VCO.Pour valider la méthode de conception, un CAN SigmaDelta avec un quantificateur tension-fréquence est conçu en 65nm. Le rapport signal sur bruit mesuré est de 62dB dans une bande de 28MHz et une consommation de 30mW.On propose ensuite l'utilisation des quantificateurs à base VCO dans les modulateurs SigmaDelta en quadrature. Pour cela, une méthode de conception systématique et présentée. Un CAN sigmadelta en quadrature de 4ème ordre avec des quantificateurs tension fréquence est conçu en 65nm. Les mesures de ce circuit sont encore encours. Les simulations post-layout montrent un rappost signal sur bruit de 75dB dans une bande de 40MHz et une consommation de 60mWToday's wireless communication systems are requiring high performance Converters analog-digital (ADC) with increasing demand on bandwidth and resolution.There is a growing need for low-power and multi-functional RF receivers , since the market is expecting complex receiving capacities with low power battery operated devices.For this reason the current trend is to decrease the analogue part of the receivers, while increasing the tasks performed by the digital part.Therefore, this imposes stringent requirements on the ADC such as wideband operation, high resolution and low power consumption.In this dissertation, we studied and realized several types of VCO-based ADCs.We show the design, implementation and the measurements of two types of VCO-based ADCs in 65nm CMOS process. The first is using the voltage to frequency conversion technique while the second uses the principle of voltage to phase conversion.The voltage to frequency converter is a 4-bit ADC with a programmable sampling frequency that goes from 220MHz up to 1500MHz.The measured Signal-to-noise-and-distortion-ratio (SNDR) is of 40.5dB in a band of 30MHz with a power consumption of 0.5mW.The voltage phase converter is a 4-bit ADC with a programmable sampling frequency that goes from 300MHz up to 1440MHz.The measured SNDR is 48dB in a band of 30MHz with a consumption of 1mW.We then present a systematic design method of high order SigmaDelta ADCs with VCO-based quantizers.To validate the design method, a SigmaDelta ADC with a 4-bit voltage-frequency is designed in 65nm. The measured SNDR is 62dB in a band of 28MHz and a power consumption of 30mw.We propose the use of VCO-based quantizers in quadrature SigmaDelta modulators. A systematic design method is presented for the quadrature VCO-based Sigmadelta modulators.A 4th order quadrature sigmadelta with 4-bit voltage to frequency quantizers is designed in 65nm. The measurements of this circuit are currently in progress. In post layout simulations, the quadrature modulator achieves 75dB in a band of 40MHz and a power consumption of 60mW
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Pheng, Bobby B. "3D Electromagnetic Simulation Tool Exposure for Undergraduate Electrical Engineers: Incorporation into an Analog Filters Course." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/819.
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With the growth of wireless communications, comes the need for engineers knowledgeable in 3D electromagnetic (EM) simulation of high-frequency circuits. To give electrical engineering students a better understanding of the behavior of electromagnetic fields, experiments including the use of 3D EM simulation software were proposed. Most students get lost in differential equations, curls, and divergences; this thesis aims to remedy that by exposing them to 3D EM simulation, which may motivate them toward further study in electromagnetics. Also, experience using EMPro is very beneficial for future RF/microwave/antenna engineers, as use of 3D EM simulation is becoming a requirement for this field. 3D EM simulators solve problems where using classical analysis techniques is impractical. Classical EM solutions to simple objects such as boxes, cylinders, and spheres, are widely known; but when the object is more complex, numerical approaches are preferred for their speed.
Currently, Cal Poly does not use 3D electromagnetic simulation in any of its courses. Targeted relevant courses include EE 335/375: EM Fields & Transmission Lines, EE 402: EM Waves, EE 405/445: High-Frequency Amplifier Design, EE 425/455: Analog Filter Design, EE 502: Microwave Engineering, and EE 533: Antennas. As a starting point, EE 425/455 was targeted.
In choosing which filters to investigate, simplicity and cost were the most important factors. For simplicity, transverse electromagnetic (TEM) mode filters were chosen; also, using a trough design for these filters would allow for simple construction and access. Also, a circular waveguide filter was chosen as an alternative to the TEM filters, as the modes are either transverse electric or transverse magnetic. To lower costs, printed circuit board was used to construct the filters, along with brass tubing, semi-rigid coaxial cable, and copper plumbing caps.
From these guidelines, three electronic bandpass filter experiments were investigated: a 1 GHz half-wave coaxial resonator filter, a 2 GHz copper end cap filter, and a tunable 1 GHz quarter-wave coaxial resonator filter. Electric and magnetic field coupling was used to excite the filters. They were then simulated using finite difference time domain (FDTD) simulations in Agilent EMPro. From the simulations, tradeoffs between insertion loss and bandwidth were observed. After, the filters were built and measured using a network analyzer. The quarter-wave filter was incorporated in Cal Poly’s EE 455 course during spring 2012. Students completed an EMPro tutorial, simulated the filters, and measured them using network analyzers. Student feedback was mixed, and modifications were made for future implementations.
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Löwenborg, Per. "Asymmetric filter banks for mitigation of mismatch errors in high-speed analog-to-digital converters /." Linköping : Univ, 2002. http://www.bibl.liu.se/liupubl/disp/disp2002/tek787s.pdf.
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Velazquez, Scott Richard. "A hybrid quadrature mirror filter bank approach to analog-to-digital conversion." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/11538.
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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (leaf 168).
by Scott Richard Velazquez.
M.S.
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Pothuri, Aditya R. "Design of Pulse Output Direct Digital Synthesizer with an Analog Filter Bank." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1215482245.
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Salem, Nia Ahmad. "Contribution à l'étude théorique et expérimentale d'un filtre actif parallèle à commandes analogique et numérique temps réel." Vandoeuvre-les-Nancy, INPL, 1996. http://www.theses.fr/1996INPL098N.
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Ces dernières années, l'utilisation des convertisseurs statiques est en forte progression. Ces convertisseurs absorbent des courants non sinusoïdaux au réseau. Ils se comportent alors comme des générateurs de courants harmoniques ce qui pose quelques problèmes aux distributeurs de l'énergie électrique comme aux utilisateurs. Le développement récent des semi-conducteurs de puissance entièrement commandables, les GTO thyristors et les IGBT en particulier, a conduit à la conception de nouvelles structures, comme les filtres actifs, pour minimiser les problèmes liés aux perturbations harmoniques. Dans cette thèse, après l'analyse des perturbations harmoniques et de ses effets sur le réseau électrique, les solutions pour les réduire, notamment les filtrages passif et actif ont été présentées. Ensuite le contrôle de filtre actif à structure tension avec deux stratégies de commande pour contrôler les courants du filtre, hystérésis et MLI, est étudié. Les simulations numériques pour deux types de commande, analogique et numérique, sont effectuées et les effets des différents paramètres de la commande sur la qualité de la compensation d'harmoniques sont présentés. Une maquette triphasée de filtre actif parallèle pour dépolluer le réseau électrique basse tension aux commandes analogique et numérique a été réalisée. Les essais expérimentaux effectués sur cette maquette ont montré les bonnes performances du filtre actif en compensation d'harmoniques. Enfin, profitant de la souplesse de la commande numérique, la suppression d'un ou plusieurs harmoniques particuliers a été étudiée. Les résultats obtenus par la simulation ainsi que par l'expérimentation de l'élimination de l'harmonique 5, de l'harmonique 7 et des harmoniques 5 et 7 sont satisfaisants
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Jalali, Mazlouman Shahrzad. "A frequency-translating hybrid architecture for wideband analog-to-digital converters." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/2745.
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Many emerging applications call for wideband analog-to-digital converters and some require medium-to-high resolution. Incorporating such ADCs allows for shifting as much of the signal processing tasks as possible to the digital domain, where more flexible and programmable circuits are available. However, realizing such ADCs with the existing single stage architectures is very challenging. Therefore, parallel ADC architectures such as time-interleaved structures are used. Unfortunately, such architectures require high-speed high-precision sample-and-hold (S/H) stages that are challenging to implement.
In this thesis, a parallel ADC architecture, namely, the frequency-translating hybrid ADC (FTH-ADC) is proposed to increase the conversion speed of the ADCs, which is also suitable for applications requiring medium-to-high resolution ADCs. This architecture addresses the sampling problem by sampling on narrowband baseband subchannels, i.e., sampling is accomplished after splitting the wideband input signals into narrower subbands and frequency-translating them into baseband where identical narrowband baseband S/Hs can be used. Therefore, lower-speed, lower-precision S/Hs are required and single-chip CMOS implementation of the entire ADC is possible.
A proof of concept board-level implementation of the FTH-ADC is used to analyze the effects of major analog non-idealities and errors. Error measurement and compensation methods are presented. Using four 8-bit, 100 MHz subband ADCs, four 25 MHz Butterworth filters, two 64-tap FIR reconstruction filters, and four 10-tap FIR compensation filters, a total system with an effective sample rate of 200 MHz is implemented with an effective number of bits of at least 7 bits over the entire 100 MHz input bandwidth.
In addition, one path of an 8-GHz, 4-bit, FTH-ADC system, including a highly-linear mixer and a 5th-order, 1 GHz, Butterworth Gm-C filter, is implemented in a 90 nm CMOS technology. Followed by a 4-bit, 4-GHz subband ADC, the blocks consume a total power of 52 mW from a 1.2 V supply, and occupy an area of 0.05 mm2. The mixer-filter has a THD ≤ 5% (26 dB) over its full 1 GHz bandwidth and provides a signal with a voltage swing of 350 mVpp for the subsequent ADC stage.
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Ashraf, Pouya, Linnar Billman, and Adam Wendelin. "Teaching Signals to Students: a Tool for Visualizing Signal, Filter and DSP Concepts." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-297168.
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Students at Uppsala University have for some years been given the opportunity to take courses in subjects directly, or indirectly, related to the fields of signal processing and signal analysis. According to the directors of these courses, a considerable number of students are recurringly having difficulties grasping different concepts related to this field of study. This report covers a tool that easily allows teachers to visualize and listen to different manipulations of signals, which should help students get an intuitive understanding of the subject. Features of the system include multiple kinds of analog filters, sampling with variable settings and zero-order hold reconstruction. The finished system is flexible, tunable and modifiable to the teachers every need, making it usable for a wide variety of courses involving signal processing. The system meets its requirements even though individual components’ results de- viate slightly from ideal values.Studenter vid Uppsala Universitet har, under ett antal år, givits möjligheten att läsa kurser inom ämnen direkt, eller indirekt, relaterade till signalbehandling/signalanalys. Enligt kursansvariga för dessa kurser har en ansenlig andel av studenterna svårigheter med att förstå en del av de begrepp och fenomen som förekommer under kurserna. Denna rapport behandlar ett verktyg som ger lärare i dessa kurser möjlighet att på ett enkelt sätt visualisera och lyssna på olika manipulationer av signaler, vilket bör hjälpa studenterna bygga en intuition för ämnet. Systemets olika funktioner inkluderar flera olika typer av analoga filter, sampling med olika inställningar, och så kallad ’Zero-Order-Hold’ rekonstruktion. Det resulterande systemet är flexibelt, inställbart och modifierbart till användarens behov, vilket gör det applicerbart i flera kurser som innefattar signalbehandling/analys. Systemet möter kraven som ställs, även fast resultaten hos individuella komponenter avviker aningen från ideala värden.
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Shiraishi, Hisako. "Design of an Analog VLSI Cochlea." University of Sydney. Electrical and Information Engineering, 2003. http://hdl.handle.net/2123/556.
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The cochlea is an organ which extracts frequency information from the input sound wave. It also produces nerve signals, which are further analysed by the brain and ultimately lead to perception of the sound. An existing model of the cochlea by Fragni`ere is first analysed by simulation. This passive model is found to have the properties that the living cochlea does in terms of the frequency response. An analog VLSI circuit implementation of this cochlear model in CMOS weak inversion is proposed, using log-domain filters in current domain. It is fabricated on a chip and a measurement of a basilar membrane section is performed. The measurement shows a reasonable agreement to the model. However, the circuit is found to have a problem related to transistor mismatch, causing different behaviour in identical circuit blocks. An active cochlear model is proposed to overcome this problem. The model incorporates the effect of the outer hair cells in the living cochlea, which controls the quality factor of the basilar membrane filters. The outer hair cells are incorporated as an extra voltage source in series with the basilar membrane resonator. Its value saturates as the input signal becomes larger, making the behaviour rather closer to that of a passive model. The simulation results show this nonlinear phenomenon, which is also seen in the living cochlea. The contribution of this thesis is summarised as follows: a) the first CMOS weak inversion current domain basilar membrane resonator is designed and fabricated, and b) the first active two-dimensional cochlear model for analog VLSI implementation is developed.
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Miller, William H. "Analog Implementation of DVM and Farrow Filter Based Beamforming Algorithms for Audio Frequencies." University of Akron / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=akron1531951902410037.
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Curien, Régis. "Outils pour la preuve." Nancy 1, 1995. http://docnum.univ-lorraine.fr/public/SCD_T_1995_0007_CURIEN.pdf.
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Le but de cette thèse est de fournir des outils permettant à la déduction automatique de réutiliser les résultats déjà obtenus. En effet, la preuve par analogie consiste à construire de nouvelles preuves à partir de preuves existantes. Il faut dans un premier temps reconnaître que le problème à résoudre est semblable à un problème déjà résolu, puis, transformer la solution existante, pour obtenir une solution du nouveau problème. L'approche adoptée consiste à définir formellement des relations liant deux formules logiques du premier ordre - celle dont nous possédons une preuve est appelée référence - pour en déduire une méthode automatique de transformation de la preuve de référence en une preuve de la nouvelle formule. Le concept d'analogie est très puissant, mais aussi très intuitif. Ainsi, pour le formaliser, nous l'avons réduit à des concepts plus simples afin de les automatiser. Nous avons défini quatre relations liant les formules, que nous appelons similitudes. Ces similitudes considèrent les propriétés de la logique propositionnelle, les propriétés des quantificateurs, le renommage des fonctions et prédicats et les propriétés associatives-commutatives des connecteurs logiques. Un outil fondamental pour la reconnaissance de ces similitudes est un algorithme de filtrage du second ordre modulo AC. La complétude et la terminaison de cet algorithme montrent la décidabilité du problème de filtrage AC du second ordre. Les transformations de preuves correspondant à ces similitudes sont données pour les preuves par expansion introduites par Miller et Pfenning. Cette représentation possède des propriétés très intéressantes pour l'analogie. Pour dépasser le stade des similitudes, nous utilisons le calcul de différence, qui utilise les échecs du filtrage. Nous montrons que lorsque la différence entre les deux formules considérées est simple, nous pouvons espérer une méthode complète d'analogie. Enfin, nous montrons, dans le cas général, et à partir d'exemples, comment l'analogie peut être envisagée par l'étude de la différence.
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Minarčík, Martin. "Návrh koncepce napěťového konvejoru a jeho aplikační možnosti." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-233471.
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This doctoral thesis deals with a voltage conveyor as a new active element for an analog signal processing. Various types of the voltage conveyors have been defined as a dual active elements to current conveyors based on a duality principle. Conception of a new active element that can supply all types of the voltage conveyors have been proposed. The active element has been named an universal voltage conveyor – UVC. A voltage follower is a basic building block of the UVC. The well-known circuit realization of the voltage follower comes from four transconductance amplifiers with key parameters (voltage transfer and output resistance) derived from relative accuracy of used transconductance amplifiers has been used by UVC fabrication. A new circuit realization of the voltage follower comes from three transconductance amplifiers with key parameters also derived from relative accuracy of used transconductance amplifiers has been designed. Further the doctoral thesis deals with a frequency filter with the voltage conveyors design using signal flow graphs. Various graphs of the voltage conveyors comes from the various circuit analysis methods with non-regular active elements have been created. A basic graph of the voltage conveyor has been designed with help of a known controlled sources graphs. This graph have been used to design of multifunctional frequency filters, filters with high input and low output impedance and controlled frequency filters. A design procedure have been created so that in specific step of the frequency filter design the basic graph of the voltage conveyor could be extended to graph of any type of the voltage conveyor. Thereby a practical usage of various types of the voltage conveyors has been finding out. Further a new method of frequency filter design based on expanding of the signal flow has beenproposed.
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Song, Zhiguo. "Systèmes de numérisation hautes performances - Architectures robustes adaptées à la radio cognitive." Phd thesis, Supélec, 2010. http://tel.archives-ouvertes.fr/tel-00589826.
Full textAbstract:
Les futures applications de radio cognitive requièrent des systèmes de numérisation capables de convertir alternativement ou simultanément soit une bande très large avec une faible résolution soit une bande plus étroite avec une meilleure résolution, ceci de manière versatile (i.e. par contrôle logiciel). Pour cela, les systèmes de numérisation basés sur les Bancs de Filtres Hybrides (BFH) sont une solution attractive. Ils se composent d'un banc de filtres analogiques, un banc de convertisseurs analogique-numérique et un banc de filtres numériques. Cependant, ils sont très sensibles aux imperfections analogiques. L'objectif de cette thèse était de proposer et d'étudier une méthode de calibration qui permette de corriger les erreurs analogiques dans la partie numérique. De plus, la méthode devait être implémentable dans un système embarqué. Ce travail a abouti à une nouvelle méthode de calibration de BFH utilisant une technique d'Égalisation Adaptative Multi-Voies (EAMV) qui ajuste les coefficients des filtres numériques par rapport aux filtres analogiques réels. Cette méthode requiert d'injecter un signal de test connu à l'entrée du BFH et d'adapter la partie numérique afin de reconstruire le signal de référence correspondant. Selon le type de reconstruction souhaité (d'une large-bande, d'une sous-bande ou d'une bande étroite particulière), nous avons proposé plusieurs signaux de test et de référence. Ces signaux ont été validés en calculant les filtres numériques optimaux par la méthode de Wiener-Hopf et en évaluant leurs performances de ces derniers dans le domaine fréquentiel. Afin d'approcher les filtres numériques optimaux avec une complexité calculatoire minimum, nous avons implémenté un algorithme du gradient stochastique. La robustesse de la méthode a été évaluée en présence de bruit dans la partie analogique et de en tenant compte de la quantification dans la partie numérique. Un signal de test plus robuste au bruit analogique a été proposé. Les nombres de bits nécessaires pour coder les différentes données dans la partie numérique ont été dimensionnés pour atteindre les performances visées (à savoir 14 bits de résolution). Ce travail de thèse a permis d'avancer vers la réalisation des futurs systèmes de numérisation basés sur les BFH.
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Omid, Abedi. "Analog and Digital Approaches to UWB Narrowband Interference Cancellation." Thèse, Université d'Ottawa / University of Ottawa, 2012. http://hdl.handle.net/10393/23366.
Full textAbstract:
Ultra wide band (UWB) is an extremely promising wireless technology for researchers and industrials. One of the most interesting is its high data rate and fading robustness due to selective frequency fading. However, beside such advantages, UWB system performance is highly affected by existing narrowband interference (NBI), undesired UWB signals and tone/multi-tone noises. For this reason, research about NBI cancellation is still a challenge to improve the system performance vs. receiver complexity, power consumption, linearity, etc. In this work, the two major receiver sections, i.e., analog (radiofrequency or RF) and digital (digital signal processing or DSP), were considered and new techniques proposed to reduce circuit complexity and power consumption, while improving signal parameters. In the RF section, different multiband UWB low-noise amplifier key design parameters were investigated like circuit configuration, input matching and desired/undesired frequency band filtering, highlighting the most suitable filtering package for efficient UWB NBI cancellation. In the DSP section, due to pulse transmitter signals, different issues like modulation type and level, pulse variety, shape and color noise/tone noise assumptions, were addressed for efficient NBI cancelation. A comparison was performed in terms of bit-error rate, signal-to-interference ratio, signal-to-noise ratio, and channel capacity to highlight the most suitable parameters for efficient DSP design. The optimum number of filters that allows the filter bandwidth to be reduced by following the required low sampling rate and thus improving the system bit error rate was also investigated.