Dissertations / Theses on the topic 'Anisotropic wet etching'

Thesis (M. Eng. in Manufacturing)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2012.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 52).<br>Data recently collected from an industrial thin film manufacturer indicate that almost 8% of devices are rejected due to excess metal, or unwanted metal on the device surface. Experimentation and analysis suggest that almost half of these defects are caused by incomplete removal of nickel oxides that form on top of the conductive nickel surface throughout the heated environment of the upstream process. This study classified and identified the composition of these excess metal defects, evaluated recommended wet etch methods to remove nickel oxide, and finally proposes a wet etch process that will rapidly remove defects while continuing to maintain the desired semi-anisotropic etch profile, uncharacteristic of most wet immersion etch processes. Results attested that rapid exposure to dilute (40%) nitric acid followed by immediate immersion into a cleaning agent, proprietary nickel etchant, and titanium tungsten etchant removed all nickel oxide defects. Upon implementation, this method has the potential to reduce scrap due to excess metal by 3% and reduce overall etch process time by 25%. In addition, a process was developed to completely etch patterned substrates with high defect density mid process and rework them from raw substrates.<br>by Neha H. Dave.<br>M.Eng.in Manufacturing

Thesis (M.S.) -- University of Maryland, College Park, 2005.<br>Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

ABSTRACT DEVELOPMENT OF A MICRO-FABRICATION PROCESS SIMULATOR FOR MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) Yildirim, Alper M.S, Department of Mechanical Engineering Supervisor: Asst. Prof. Dr. Melik D&ouml<br>len December 2005, 140 pages The aim of this study is to devise a computer simulation tool, which will speed-up the design of Micro-Electro-Mechanical Systems by providing the results of the micro-fabrication processes in advance. Anisotropic etching along with isotropic etching of silicon wafers are to be simulated in this environment. Similarly, additive processes like doping and material deposition could be simulated by means of a Cellular Automata based algorithm along with the use of OpenGL library functions. Equipped with an integrated mask design editor, complex mask patterns can be created by the software and the results are displayed by the Cellular Automata cells based on their spatial location and plane. The resultant etched shapes are in agreement with the experimental results both qualitatively and quantitatively. Keywords: Wet Etching, Anisotropic Etching, Doping, Cellular Automata, Micro-fabrication simulation, Material Deposition, Isotropic Etching, Dry Etching, Deep Reactive Ion Etching

This thesis presents the development of electrochemical etch-stop techniques (ECES) to achieve high precision 3-dimensional integrated MEMS sensors with wet anisotropic etching by applying proper voltages to various regions in silicon. The anisotropic etchant is selected as tetra methyl ammonium hydroxide, TMAH, considering its high silicon etch rate, selectivity towards SiO2, and CMOS compatibility, especially during front-side etching of the chip/wafer. A number of parameters affecting the etching are investigated, including the effect of temperature, illumination, and concentration of the etchant over the etch rate of silicon, surface roughness, and biasing voltages. The biasing voltages for passivating the n-well and enhancing the etching reactions on p-substrate are determined as -0.5V and -1.6V, respectively, after a series of current-voltage characteristic experiments. The surface roughness due to TMAH etching is prevented with the addition of ammonium peroxodisulfate, AP. A proper etching process is achieved using a 10wt.% TMAH at 85&deg<br>C with 10gr/lt. AP. Different silicon etch samples are produced in METU-MET facilities to understand and optimize ECES parameters that can be used for CMOS microbolometers. The etch samples are fabricated using various processes, including thermal oxidation, boron and phosphorus diffusions, aluminum and silicon nitride layer deposition processes. Etching with the prepared samples shows the dependency of the depletion layer between p-substrate and n&amp<br>#8209<br>well, explaining the reason of the previous failures during post-CMOS etching of CMOS microbolometers from the front side. Succesfully etched CMOS microbolometers are achieved with back side etching in 6M KOH at 90 &deg<br>C, where &amp<br>#8209<br>3.5V and 1.5V are applied to the p-substrate and n-well. In summary, this study provides an extensive understanding of the ECES process for successful implementations of integrated MEMS sensors.

This thesis deals with the silicon etching technology. It Examines using of water solution of potassium hydroxide. It focuses on plasma etching of silicon using mixture of CF4 and O2 as the dry way of etching. Important parameters of etching like etching rate of silicon and masking materials, etching selectivity, surface roughness and underetching of mask are determined for both ways. Some additional processes has been examined as well, namely creating of mask of resist and silicon dioxide, lithography process and etching of resist using oxygen plasma.

The task of master’s thesis was to perform optimalization process for preparing metal etching mask by electron beam litography and subsequent selective wet ething of silicon with crystalographic orientation (100). Further characterization of etched surface and fabricated structures was performed. In particular, attention was given to the morphology demonstrated by scanning electron microscopy and study changes of the optical properties of gold plasmonic antennas due to their undercut.

碩士<br>國立臺灣大學<br>機械工程學研究所<br>88<br>Anisotropic wet etching is one of the key technologies for the microstructure fabrication in Micro Electro Mechanical Systems (MEMS). The most commonly used etchants are potassium hydroxide water solution (KOH), ethylenediamine-pyrocatechol-water (EDP), and hydrazine-water solution. EDP and hydrazine-water solution handling are dangerous because of the high toxicity and instability. Aqueous KOH solutions are the most widely used due to low toxicity and good surface roughness, but the compatibility with the CMOS processes is not good enough due to the mobile potassium ion contamination. In recent years, a special anisotropic etchant, tetramethylammonium hydroxide (TMAH, (CH3)4NOH)) has been proposed and is fulfils CMOS-compatibility requirements and non-toxic. The present study aims to investigate the etching rate varies vs. the etchant’s temperature and concentration. The effects of passivation silicon oxide and surface roughness have also received very little attention. In our work, we choose three variables: (i) TMAH solution concentration by weight (2~25%), (ii) TMAH solution temperature (70~90°C), and (iii) the silicon substrate type (n- and p-type silicon wafers) to monitor the TMAH etching rate, the selectivity of Si/SiO2, and the surface roughness. In our study, the most fast etching rate is 81 m/hr, which appears at 90°C and 8 wt.% TMAH solution. We also find the selectivity of Si/SiO2 will much higher than KOH solutions at lower temperature in our study. At lower concentration (2~5 wt.%) will result the hillocks of the surface, but these will disappear at higher concentration (15~25 wt.%). Finally, the pre-alignment is also conducted. Such pre-etching patterns allow us to determine the <100> crystal orientation within accuracy of 0.05° and can be used as valuable reference for all subsequent mask patterns.

The fabrication processes of recent MEMS devices require the use of anisotropic etching and variety of concave structures. Analysis of these structures uncovered phenomenon in the etch rates of surfaces exposed by anisotropic etchant. This phenomenon could not be explained without consideration of the composition of these surfaces on atomic level. My study raised the step-based modeling of these planes, their relative interactions, and dependence on the etching environment. Control of this environment and better understanding of the different factors that influence the etch rates of these surfaces is the main theme of my work. To help with the analysis of the studied surfaces a set of the experiments was done using a wagon-wheel pattern that provided the necessary assortment of concave structures for the purpose of this research. A mathematical model was built to help understand the processes that are responsible for anomalies in the etch rates and profiles of surfaces exposed on sidewalls of spokes in the wagon-wheel experiment. Detailed examination of the profiles of the surfaces and their relative location within the same concave structure suggested the possibility of application of these surfaces in creation of different patterns for nano-applications. The major concern is the control of etch rates of these planes in order to achieve the necessary precision for the application on such scale. Light illumination of the etched surfaces is analyzed as a possible component in providing the necessary level of control. Influence of the light intensity and different wavelengths is studied with the thought of application of the respective parameters in order to achieve a satisfactory control over the etch rates of illuminated surfaces.

碩士<br>國立交通大學<br>電子工程系<br>88<br>In order to implement the MEMS devices on the silicon wafers, it's necessary to fabricate various microstructures. In this thesis, we employed the anisotropic wet-etching process to develop the crystallographic- orientation alignment technology, the etch-stop technology, and the corner compensation technology. We used photolithography and etch processes to transfer the various designed photomask patterns onto {100} silicon wafers, which would be etched in the aqueous KOH until the desired microstructures have been achieved. In this experiment, we achieved the following structures: (1) a pre-etching pattern to determinate the crystallographic orientation with resolution 0.00625°, (2) a cantilever beam with aspect ratio 12.5 and length 1cm, (3) a 50μm thick silicon membrane using laser-controlled etch-stop technology, (4) a convex-corner structure, (5) a approximate semi-cylindrical structure.

博士<br>國立交通大學<br>光電工程所<br>90<br>Si nanostructures offering unique photonic properties are significant to the applications of photonic integrated circuits. However, the extremely high expenses of the facilities and utilities to provide nanometer scale features have blocked the development of nano photonic devices in research laboratories. Scanning probe lithography (SPL), employing a proximal probe to induce local anodic oxidation (so-called scanning probe oxidation), can provide nanometer lateral resolutions comparable to most advanced lithography and exhibit the distinction of simplicity, generality and low cost. The aim of this study is to develop a reliable, yet affordable technique for rapid prototyping of nano photonic devices in laboratories based on SPL. We demonstrated the conversion of Si3N4 to SiOx at the nanometer scale can be performed by SPL. The growth kinetics of scanning probe oxidation on Si3N4 obeys the logarithmic relationship and growth rate exponentially decays with respect to oxide height. We found scanning probe oxidation of Si3N4 has a short onset time, which accounts for its extremely high initial oxidation rate. Electrostatic force characterization indicates that charges, trapped in probe-induced oxide, are positive and linearly increase with the oxide height. We suggest that effective activation energy of oxidation increases with the amount of trapped charges, and therefore the exponential decay of growth rate can be derived. By means of Si anisotropic etching in KOH and tetra-methyl ammonium hydroxide (TMAH) etchants, we produced a variety of Si structures with the oxide patterns on either Si or Si3N4 as masks. They include structures with a pitch of 100 nm, structures of positive and negative contrast, and features height greater than 400 nm, produced on bare silicon, Si3N4-coated silicon and silicon-on-insulator (SOI) wafers. Evolution of hexagonal pits on two-dimensional grid structures is shown to depend on the pattern spacing and orientation with respect to silicon crystal directions. We conclude the process of SPL in combination with anisotropic wet etching (KOH or TMAH) is a low-cost and reliable method to produce smooth and uniform silicon nanostructures on different Si substrates. We have succeeded in the combination of SPL with traditional optical lithography as a mixed, multilevel patterning method for realizing micrometer- and nanometer-scale feature sizes, as required for photonic device designs. We believe the cooperating method of the combined lithography and anisotropic wet etching is a promising approach for rapid prototyping of functional nano photonic devices. Based on the techniques developed in this study, a process to fabricate 1-D photonic band gap on SOI is proposed.

碩士<br>國立成功大學<br>微電子工程研究所碩博士班<br>101<br>Long-period gratings (LPGs) are functioned based on the light coupling between the core guiding modes and the cladding modes at specific wavelengths (resonance wavelengths). However, the conventional FBG implemented on the optical fiber inevitably faces the geometry and material constraints associated with the fiber, which impose significant limitations on the device functionalities. To bypass the foregoing constraints, a long-period waveguide grating (LPG) employing a waveguide structure has been developed instead to provide an additional flexibility needed in designing various LPG-based devices. In general, the traditional long-period waveguide gratings were manufactured using low refractive index materials. In this thesis, high-refractive index silicon was used for the first time to explore its practicality for the long-period waveguide gratings fabrication. Specifically, the device was etched and patterned on SOI wafer via an anisotropic wet etching technique and eventually the long-period waveguide gratings were successfully fabricated with silicon ridge waveguide incorporated as an optical waveguide core layer. In addition, the cladding layer based on amorphous silicon with refractive index slightly lower than the crystalline silicon was deposited using plasma-enhanced chemical vapor deposition (PECVD) by judiciously controlling the flow rate of SiH4. With the amorphous silicon used as the cladding layer, the gratings with pitch as long as tens of micrometer could now be defined and patterned using the conventional photolithography. As mentioned previously, the wet etching was adopted to overcome the line width restriction entailed by the use of a much cheaper plastic mask; making the device feature size less than 20μm easily realizable, specifically, waveguides with a line width of 20, 18, 15, 12, 10 and 8μm had all been successfully fabricated to cut down the number of guided modes present in the core region. Additionally, a commercial software was used to design gratings with six different pitches needed, namely, Λ20=100μm, Λ18=107μm, Λ15=93μm, Λ12=95μm, Λ10=109μm and Λ8=91μm. The subsequent experimental results demonstrate that the LPWG devices appear to resonate within a wavelength range between 1563 and 1578nm, and the waveguide width of 8μm has delivered a dip contrast as high as 20 dB, while the device with the waveguide width of 10μm has its FWHM measured as narrow as 3.3nm. Then the experimental results with polarization controller inserted into the measurement setup show that the devices resonate within a wavelength range between 1563 and 1580nm, and the waveguide width of 8μm has delivered a dip contrast as high as 30 dB, while the device with the waveguide width of 12μm has its FWHM measured as narrow as 1.76nm with input light polarized as transverse electric (TE) wave. With transverse magnetic (TM) polarized wave provided as an input, the waveguide width of 10μm yields a dip contrast as high as 14.5 dB, while the device with the waveguide width of 10μm has its FWHM measured as narrow as 1.32nm.

碩士<br>國立臺灣師範大學<br>機電科技研究所<br>93<br>Anisotropic wet etching is one of the key technologys for the microstructure fabrication in Micro Electro Mechanical Systems(MEMS). In the study, for improving the roughness quality and etching rate of etched surface, high pressure and high temperature enhanced fast anisotropic etching of mono-crystalline silicon, the methods will be used to evaluate the etching properties of (100) silicon plane in KOH or TMAH solutions. The anisotropic etching parameters will be optimized adequately and employed to fabricate the high precise silicon microstructures. For the study of batch production, the silicon structures will be formed the metallic mold insert by the electroforming process, and then the molding process, including hot embossing or injection molding, will be applied to produce mass plastic microstructure, and then the low-cost MEMS applications will be realized. Four key techniques will be focused as followed: (1) To setup the apparatus of high pressure and high temperature suitable to anisotropic fast wet etching of single silicon; (2) To build up the optimized fast etching process parameters, (3) To fabricatie the silicon-microstructure and Silicon nitride membrane microstructure. The results of carrying out project will be predicted to promote the domestic silicon etching technique in MEMS , and also facilitate the international competitive power of the related companies in the market of micro-systems, which have been demonstrated as the highest valued industry in the future.

碩士<br>國立成功大學<br>機械工程學系碩博士班<br>93<br>Two main points of this study is to analyze how scanning velocity affects the height of oxide line fabricated by EC-AFM(Electrochemisty Atomic Force Microscope) oxidation. Another one is to analyze the anisotropic wet etching rate without stirring. We tries to find out the relation between oxide heights, total oxidation time and scanning velocity in EC-AFM oxidation. In this study, we derive the dynamic EC-AFM oxidation model basic on static EC-AFM oxidation which includes Cabrera-Mott oxidation theory and use it to discuss the height of oxide line under different scanning velocities from the EC-AFM oxidation behavior. We also tries to find out the relation between etchant concentration, etching temperature, total etching time and the anisotropic wet etching rate without stirring. In this study, the non-stirring etching rate model is basic on the diffusion of etchant ions and chemical reaction of etching. And use this model to discuss non-stirring etching rate under different etchant concentration, etching temperature and total etching time. Then we set up the experiments, and see how the experimental parameters affect the experimental results from the dynamic oxidation mechanism and anisotropic wet etch without stirring For the same oxidation voltage the heights and widths of oxide line decrease when raising the scanning velocity. We also find out the error least under the highest scanning velocity. For wet etching without stirring the etching rate increase when raising etchant concentration or etching temperature. But the etching rate decreases accompany the etching time increasing. Comparing the experimental and the theoretical results, it is concluded that scanning velocity does affect the size of oxide line from EC-AFM oxidation. The experimental results of non-stirring etching rate is quite fit the theory derive from diffusion.

The continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes.<br>text