Dissertations / Theses on the topic 'Antenna arrays. Integrated circuits'

Thesis (M.S. in Electrical and Computer Engineering)--Naval Postgraduate School, June 2009.
Thesis Advisor(s): Janaswamy, Ramakrishna. Second Reader: Neta, Beny. "June 1990." Description based on title screen as viewed on 19 October 2009. DTIC Identifier(s): Planar antennas, antenna arrays, millimeter waves, integrated circuits. Author(s) subject terms: Thesis, word processing, Script, GML, text processing. Includes bibliographical references (p. 124-125). Also available online.

This thesis considers integration of antennas and active electronics manufactured on the same substrate. The main topic is on-chip antennas for commercial silicon processes, but hybrid integration using printed circuit board technology is also addressed.

The possible use of micromachining techniques as a means of reducing substrate losses of antennas manufactured on low resistivity silicon wafers is investigated. Compact dipole, loop, and inverted-F antennas for the 20-40 GHz frequency range are designed, implemented, and characterized. The results show significantly improved antenna efficiency when micromachining is used as a post-processing step for on-chip antennas manufactured in silicon technology.

High resistivity wafers are used in a commercial silicon germanium technology to improve the efficiency of dipole antennas realized using the available circuit metal layers in the process. Monolithically integrated 24 GHz receivers with on-chip antennas are designed and evaluated with regard to antenna and system performance. No noticeable degradation of the receiver performance caused by cross talk between the antenna and the integrated circuit is observed.

For low frequency antenna arrays, such as base station antennas, hybrid integration of active devices within the antenna aperture is treated. A compact varactor based phase shifter for traveling wave antenna applications is proposed and evaluated. Electrically steerable traveling wave patch antenna arrays, with the phase shifters implemented in the same conductor layer as the radiating elements, are designed and manufactured in microstrip technology. It is experimentally verified that the radiation from the feed network and phase shifters in the proposed antenna configuration is small.

As integrated circuits become smaller in size, antenna design has become the size limiting factor for RF front ends. The size reduction of an antenna is limited due to tradeoffs between its size and its performance. Thus, combining antenna designs with other system components can reutilize parts of the system and significantly reduce its overall size. The biggest challenge is in minimizing the interference between the antenna and other components so that the radiation performance is not compromised. This is especially true for antenna arrays where the radiation pattern is important. Antenna size reduction is also desired for wireless sensors where the devices need to be unnoticeable to the subjects being monitored. In addition to reducing the interference between components, the environmental effect on the antenna needs to be considered based on sensors' deployment. This dissertation focuses on solving the two challenges: 1) designing compact multi-frequency arrays that maintain directive radiation across their operating bands and 2) developing integrated antennas for sensors that are protected against hazardous environmental conditions. The first part of the dissertation addresses various multi-frequency directive antennas arrays that can be used for base stations, aerospace/satellite applications. A cognitive radio base station antenna that maintains a consistent radiation pattern across the operating frequencies is introduced. This is followed by multi-frequency phased array designs that emphasize light-weight and compactness for aerospace applications. The size and weight of the antenna element is reduced by using paper-based electronics and internal cavity structures. The second part of the dissertation addresses antenna designs for sensor systems such as wireless sensor networks and RFID-based sensors. Solar cell integrated antennas for wireless sensor nodes are introduced to overcome the mechanical weakness posed by conventional monopole designs. This can significantly improve the sturdiness of the sensor from environmental hazards. The dissertation also introduces RFID-based strain sensors as a low-cost solution to massive sensor deployments. With an antenna acting as both the sensing device as well as the communication medium, the cost of an RFID sensor is dramatically reduced. Sensors' strain sensitivities are measured and theoretically derived. Their environmental sensitivities are also investigated to calibrate them for real world applications.

Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design that FPGAs have had on digital design. In my research, I investigate the areas floating-gate transistors can be used to impact FPAA design and implementation. An FPAA can be broken up into two basic components, elements of connection and elements of computation. With respect to connection, I show that a floating-gate switch can be used in a cross-bar matrix in place of a transmission gate resulting in less parasitic capacitance and a more linear resistance for the same size transistor. I illuminate the programming issues relating to injecting a floating-gate for use as a switch, including the drain selection circuitry and rogue injection due to gate induced drain leakage. With respect to computation, I explain how a Multiple-Input Translinear Element, or MITE, can be augmented to fit in an FPAA framework. I also discuss two different MITE implementations compatible with CMOS technology, a subthreshold MOS design and a BJT MITE that uses a lateral BJT. Beyond FPAA components, I present two alternative FPAA systems. The first is a general purpose reconfigurable analog system that uses standard analog design components that have been augmented with floating-gates. The second FPAA is built upon MITE circuits, and is focused on supporting direct system synthesis. I conclude with a discussion of a future large-scale MITE FPAA.

The research presented in this thesis leverages silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology to develop microwave front-end electronics for active phased-array antennas. The highly integrated electronics will reduce costs and improve the feasibility of snow measurements from airborne and space-borne platforms. Chapter 1 presents the motivation of this research, focusing on the technological needs of snow measurement missions. The fundamentals and benefits of SiGe HBTs and phased-array antennas for these missions are discussed as well. Chapter 2 discusses SiGe power amplifier design considerations for radar systems. Basic power amplifier design concepts, power limitations in SiGe HBTs, and techniques for increasing the output power of SiGe HBT PAs are reviewed. Chapter 3 presents the design and characterization of a robust medium power X-band SiGe power amplifier for integration into a SiGe transmit/receive module. The PA design process applies the concepts presented in Chapter 2. A detailed investigation into measurement-to-simulation discrepancies is outlined as well. Chapter 4 discusses the development and characterization of a single-chip X-band SiGe T/R module for integration into a very thin, lightweight active phased array antenna panel. The system-on-package antenna combines the high performance and integration potential of SiGe technologies with advanced substrates and packaging techniques to develop a high performance scalable antenna panel using relatively low-cost materials and silicon-based electronics. The antenna panel presented in this chapter will enable airborne SCLP measurements and advance the technology towards an eventual space-based SCLP measurement instrument that will satisfy a critical Earth science need. Finally, Chapter 5 provides concluding remarks and discusses future research directions.

Terahertz is the portion of the spectrum that covers a frequency range between 300 GHz - 3 THz. This frequency band has proven its potential for imaging applications thanks to the good compromise between spatial resolution and penetration; however, this push towards high frequencies contains many technological difficulties in all the subsystems involved in the signal generation, transmission and detection. The power budget restrictions and high losses that sources and receivers currently suffer at these frequencies require systems with a high level of integration among all the devices and components of the systems and subsystems. Therefore, the antennas needed for these systems require to be integrated within the same fabrication processes and technologies as the sensing and power converting devices that are used at their terminals. This doctoral thesis has focused on the development of integrated antenna arrays at Terahertz frequencies for imaging applications, for both near-field and focal-plane geometries, with a special emphasis on the technologies and the fabrication capabilities that can be potentially used and are currently available. The current imaging systems require large arrays of antennas in order to achieve the high-speed image acquisition that is required in most THz applications. This fact increases considerably the difficulty and complexity to achieve highly integrated and efficient antennas. This thesis has characterized and analyzed these difficulties and provided solutions to the development of antenna arrays at millimeter and submillimeter wave frequencies. The first part of this thesis has focused on the study of a planar antenna array, called retina, for a specific near-field imaging system based on the Modulated Scatterer Technique (MST) at millimeter and submillimeter-wave frequencies. This system has been selected for its capabilities to perform high-speed imaging and because it does not require a high frequency distribution line network. However, it is hindered by many technological difficulties: the selection of an antenna geometry that achieves high efficiency, the selection of the adequate active element and its integration with the antenna. In this thesis, these challenges have been addressed and studied in-depth, and a design methodology that integrates all the different aspects of the system has been developed. Because planar antennas at millimeter and submillimeter wave frequencies suffer from high losses due to the surface wave modes inside substrate, these losses have been analyzed and quantified for different antennas, and an antenna geometry that reduces significantly this problem has been developed. Different switching technologies currently or potentially available at these high frequencies have been considered in order to study and analyze their capabilities and their integration possibilities: PIN diodes, Schottky diodes and RF-MEMS. These technologies have been studied through the development of three retina prototypes, which have been fabricated using high precision fabrication processes such as laser micromachining and photolithographic. Different measurement set ups were fabricated and assembled to validate the different premises presented. The second part of the thesis is devoted to the study of integrated Focal Plane Arrays (FPA). The development of FPA at submillimeter wave frequencies is highly on demand due to the enormous progress in designing integrated heterodyne receivers. These receivers integrate arrays of submillimeter-wave diode-based mixers and multipliers with Monolithically Integrated Circuit (MIC) amplifiers on the same wafer stack. For this stackable multi-pixel terahertz camera technology to work, a leaky wave antenna with silicon micro-lenses has been developed, which allows wafer level integration compatible with silicon micro-fabrication techniques for bulk array manufacturing and has high directivity in order to illuminate a reflector efficiently. Detailed and thorough design guidelines for this antenna are presented. Two antenna prototypes were built in order to evaluate the two fabrication possibilities: advanced laser micro-fabrication and photolithographic fabrication. A study of the aberrations of the lens has been developed in order to evaluate the performance of the lens profile fabricated. Moreover, a set of radiation pattern measurements of the fabricated prototypes was performed in order to evaluate the performance of the antenna and its possibilities to be used as a FPA.

Thesis (M. S.)--Mechanical Engineering, Georgia Institute of Technology, 2006.
Dr. Jonathan Colton, Committee Chair ; Dr. John Muzzy, Committee Member ; Dr. Daniel Baldwin, Committee Member ; Dr. John Schultz, Committee Member.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: David V Anderson; Committee Co-Chair: Sung Kyu Lim; Committee Member: Aaron Lanterman; Committee Member: Abhijit Chatterjee; Committee Member: Daniel Foty; Committee Member: Paul Hasler. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (Ph. D.)--University of California, San Diego, 2009.
Title from first page of PDF file (viewed September 17, 2009). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 112-119).

Phased array radar systems employ multiple antennas to create a radar beam that can be steered electronically. By manipulating the relative phase values of feeding signals among different antennas, the effective radiation pattern of the array can be synthesized to enhance the main lobe in a desired direction while suppressing the undesired side lobes in other directions. Hence the radar scanning angles can be electronically controlled without employing the bulky mechanical gimbal structure, which can significantly reduce radar system size, weight and power consumption. In recent years, phased array technologies have received great attentions and are explored in developing many new applications, such as smart communication systems, military radars, vehicular radar, etc. Most of these systems are narrow band systems, where the phase delays are realized with narrow band phase shifter circuits. For the impulse ground penetrating radar however, its operating frequency spans an ultrawide bandwidth. Therefore the traditional phase shifters are not applicable due to their narrow band nature. To resolve the issue, in this study, a true time delay approach is explored which can precisely control time delays for the feeding pulse signals among different antennas in the array. In the design, an on chip programmable delay generator is being developed using Global Foundry 0.18 µm 7 HV high voltage CMOS process. The time delay control is realized by designing a programmable phase locked loop (PLL) circuit which can generate true time delays ranging from 100 ps (picoseconds) to 500 ps with the step size of 25 ps. The PLL oscillator's frequency is programmable from 100MHz to 500MHz through two reconfigurable frequency dividers in the feedback loop. As a result, the antenna beam angle can be synthesized to change from 9.59° to 56.4° with a step of 2.75°, and the 3dB beamwidth is 10°. The power consumption of the time delay circuit is very low, where the supply voltage is 1.8V and the average current is as low as 472uA.

This thesis work presents a new harmonic suppression technique for microstrip patch antennas. Harmonic suppression in active integrated antennas is known as an effective method to improve the efficiency of amplifiers in transmitter side. In the proposed design, the antenna works as the radiating element and, at the same time, as the tuning load for the amplifier circuit that is directly matched to the antenna. The proposed active antenna architecture is easy to fabricate and is symmetric, so it can be conveniently mass-produced and designed to have circular polarization, which is preferred in many applications such as satellite communications. The antenna simulations were performed using Ansoft High Frequency System Simulator (HFSS) and all amplifier design steps were simulated by Advanced Design System (ADS). The final prototypes of the linearly polarized active integrated antenna and the circularly polarized active integrated antenna were fabricated using a circuit board milling machine. The antenna radiation pattern was measured inside Utah State University's anechoic chamber and the results were satisfactory. Power measurements for the amplifiers' performance were carried out inside the chamber and calculated by using the Friis transmission equation. It is seen that a significant improvement in the efficiency is achieved compared to the reference antenna without harmonic suppression. Based on the success in the single element active antenna design, the thesis also presents a feasibility of applying the active integrated antenna in array configuration, in particular, in scanning array design to yield a low-profile, low-cost alternative to the parabolic antenna transmitter of satellite communication systems.

Phased array element RF front ends typically use single pole double throw (SPDT) switches or circulators with high isolation to prevent leakage of transmit energy into the receiver circuits. However, as phased-array designs scale to the millimeter-wave range, with high degrees of integration, the physical size and performance degradations associated with switches and circulators can present challenges in meeting system performance and size/weight/power (SWAP) requirements. This work demonstrates a loss-aware methodology for analysis and design of switchless transmit/receive (T/R) circuits. The methodology provides design insights and a practical, generally applicable approach for solving the multi-variable optimization problem of switchless power amplifier/low-noise amplifier (PALNA) matching networks, which present optimal matching impedances to both the power amplifier (PA) and the low noise amplifier (LNA) while maximizing power transfer efficiency and minimizing dissipative losses in each (transmit or receive) mode of operation. Three PALNA example designs at W-band are presented in this dissertation, each following a distinct design methodology. The first example design in 32SOI CMOS leverages PA and LNA circuits that already include 50 Ω matching networks at both input and output. The second example design in 8XP SiGe develops the PA and LNA circuits and integrates the PA output and LNA input matching networks into the PALNA matching network that connects the PA and the LNA. The third design in 32SOI CMOS leverages the loss-aware PALNA design methodology to develop a PALNA that achieves simulated maximum power added efficiency of 18 % in transmit and noise figure of 7.5 dB in receive at 94 GHz, which is beyond the published state-of-art for T/R circuits. In addition, for comparison purposes, this dissertation also presents an efficient, switch-based T/R circuit design in 32SOI CMOS technology, which achieves a simulated maximum power added efficiency of 15 % in transmit and noise figure of 6.5 dB in receive at 94 GHz, which is also beyond the published state-of-art for T/R circuits.
Doctor of Philosophy
In military and commercial applications, phased arrays are devices primarily used to achieve focusing and steering of transmitted or received electromagnetic energy. Phased arrays consist of many elements, each with an ability to both transmit and receive radio frequency (RF) signals. Each element incorporates a power amplifier (PA) for transmit and a low noise amplifier (LNA) for receive, which are typically connected using a single pole double throw (SPDT) switch or a circulator with high isolation to prevent leakage of transmit energy into the receiver circuits. However, as phased arrays exploit the latest technological advances in circuit integration and their frequencies of operation increase, physical size and performance degradations associated with switches and circulators can present challenges in meeting system performance and size/weight/power (SWAP) requirements. This dissertation provides a loss-aware methodology for analysis and design of switchless transmit/receive (T/R) circuits where the switches and circulators are replaced by carefully designed power amplifier/low-noise amplifier (PALNA) impedance matching networks. In the switchless T/R circuits, the design goals of maximum power efficiency and minimum noise in transmit and receive, respectively, are achieved through impedance matching that is optimal and low-loss in both modes of operation simultaneously. Three distinct PALNA example designs at W-band are presented in this dissertation, each following a distinct design methodology. With each new design, lessons learned are leveraged and design methodologies are enhanced. The first example design leverages already available PA and LNA circuits and connects them using 50 Ω transmission lines whose lengths are designed to guarantee optimum impedance match in receive and transmit mode of operation. The second example design develops new PA and LNA circuits and connects them using 50 Ω transmission lines whose lengths are designed to simultaneously achieve optimum impedance matching for maximum power efficiency in transmit mode of operation and lowest noise in receive mode of operation. The third design leverages a loss-aware PALNA design methodology, a multi-variable optimization procedure, to develop a PALNA that achieves simulated maximum power added efficiency of 18 % in transmit and noise figure of 7.5 dB in receive at 94 GHz, which is beyond the published state-of-art for T/R circuits. In addition, for comparison purposes with the third PALNA design, this dissertation also presents an efficient, switch-based T/R circuit design, which achieves a simulated maximum power added efficiency of 15 % in transmit and noise figure of 6.5 dB in receive at 94 GHz, which is also beyond the published state-of-art for T/R circuits.

Thesis (M.Eng.(Microelectronic Engineering))--University of Pretoria, 2009.
Includes summaries in Afrikaans and English. Includes bibliographical references (leaves [74]-78). Mode of access: World Wide Web.

The introduction of new technologies such as Field Programmable Gate Arrays (FPGAs) with high gate counts and embedded memory Applications Specific Integrated Circuits (ASICs) gives greater scope to the design of computer graphics hardware. This thesis investigates the features of the current generation of FPGAs and complex programmable logic devices (CPLD) and assesses their suitability as replacements for ASIC technologies, and as prototyping tools for their verification prior to fabrication. The traditional methodologies and techniques used for digital systems are examined for application to FPGA devices and novel design flow and implementation techniques are proposed. The new methodology and design flow uses a contemporary top down approach using hardware description languages and combines the flexibility of those methods with the efficiency of detailed low level design techniques. As an example of this methodology, a set of floating point arithmetic units consisting of a adder/subtraction, multiplication and division were designed using novel alternative algorithms that significantly outperformed algorithms designed with traditional methods in terms of both size and performance.T hese techniquesu sed were used to form a ToolKit that can accelerateth e design of systems that use floating point units for computer graphics systems. This ToolKit, in combination with a precision investigation methods can be used to generate floating point arithmetic units that have the required precision with minimum required hardware resources. Another emerging technology is that of embedded memory. Recent advancements in semiconductor fabrication processes make it feasible to integrate large amounts of DRAM, SRAM and logic on a single silicon die. This thesis will show the changes in the design flow that are require to take advantage of this new technology. A new embedded logic ToolKit was created that facilitates the exploitation of this technology. Finally, as an example to this methodology, a novel processor oriented towards 3D graphics was designedA. n architecturale xploration driven by novel trace-drivenp erformancea nalysism ethods is detailed that was used to model and tune the processor for the execution of global illumination computer graphics algorithms. The adaptation of these algorithms for execution in our processor is demonstrateda nd the performancea dvantagesth at can be extracteda re shown

Phased arrays are electromagnetic antenna systems comprised of many radiating elements and processing electronics. Radiating elements are typically positioned in an orderly grid within the antenna aperture. In the receive mode of operation, radiating elements capture some of the signal energy from incoming radiation and guide these signals to processing electronics. Signals are filtered and amplified to maintain the desired sensitivity and complexly weighted using circuits with reconfigurable amplification gain and phase delay. Finally, all signals are combined. The summation of these complexly weighted spatial samples forms a spatial filter in the same way complexly weighted temporal samples establish a temporal filter in a finite impulse response discrete-time filter. Therefore, a phased array behaves like a spatial filter that strongly favors signals arriving from a specific direction. This favored direction represents the look angle of its beam, and the shape of the beam directly relates to the complex weights applied to the signals in the array. Analogous to the flexibility offered by digital filters, phased arrays enable agile beam steering, sidelobe control, and multiple independent beams. These capabilities have revolutionized radar, radioastronomy, and communication systems. Phased arrays have increasingly employed printed circuit board (PCB) fabrication techniques and processes to maximize array channel density, achieve lower profile, and minimize component integration cost. A few applications which leverage these qualities include low-cost radar, mobile satellite communication (SATCOM), and intelligence, surveillance, and reconnaissance (ISR). Further, PCB-based arrays readily accommodate advancements in highly integrated beamforming radio frequency integrated circuits (RFICs), multi-chip modules, and RF micro-electro-mechanical system (MEMS) device technologies. On a prior effort, an integrated unit cell design was developed for a PCB-based SATCOM array application. However, the design failed to meet the requirements. The primary objective of this work is to demonstrate an improved design using systematic microwave design techniques and modern analysis tools to meet the requirements for the same application. The proposed design must improve gain, bandwidth, size, and manufacturability over the prior design. Additionally, the design must be generally extensible to phased array implementations across the SHF band (3-30 GHz). This work discusses the advantages of phased arrays over continuous apertures (e.g. reflectors), reviews phased array theory, and proposes an improved unit cell design. The proposed design is 35% smaller than a dime and consists of an orthogonally-fed, slot-coupled stacked patch antenna and dual-stage branchline coupler implemented in a multilayer PCB. Within the operating band from 10.7 to 14.5 GHz, the design achieves an average return loss of 15 dB, a uniform radiation pattern with peak realized gain of 4.8 to 7.0 dBic, cross-polarization level below -17 dB, and stable performance in a closely-spaced array. When configured in an array, the design supports X/Ku-band SATCOM in full-duplex operation, electronically rotatable polarization, and a 47.5˚ grating lobe free conical scan range. Further, a Monte Carlo analysis proves the design accommodates tolerances of material properties and manufacturing processes, overcoming a major challenge in PCB-based high frequency antenna design.

Wireless communication is a form of communication that has been around for over hundreds of years and is the fastest growing segment of the communication industry. Today, wireless communication has become an essential part of almost everyone’s daily life, and the number of users has increased exponentially over the last decade with the introduction of the internet, mobile devices and smart phones. Radio Frequency (RF) transmission is arguably the most popular method of communication and is available worldwide. With the rapid progress in technology and the increase of number of users, the limited RF spectrum is becoming more congested which led to numerous research efforts to find an alternative that can help to alleviate the pending problem. One of the proposed solutions is Visible Light Communication (VLC), which uses visible Light Emitting Diode (LED) for data transmission. In this thesis, three integrated microLED/Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits (ICs) are presented with the main aim of increasing the data rate of transmission. The first microLED/CMOS IC presented here is the Generation V microLED/CMOS driver which represents the continuation of the earlier work in the HYPIX project, which aimed to develop a microLED/CMOS driver to optically pump an organic polymer laser. A 40x10 pixelarray of Generation V microLED/CMOS driver was thus designed, primarily for optical pumping polymer lasing purposes, but has also demonstrated the ability to perform communication transmission using an On-Off Keying (OOK) modulation scheme. The driver consumes up to 330mA current and produces approximately 12mW of optical power from a single pixel, which is about 3 times higher than its predecessor. The second microLED/CMOS IC is the microLED/CMOS Current Feedback (CCFBK) driver which was designed to facilitate Orthogonal Frequency Division Multiplexing (OFDM) modulation. OFDM is one of the modulation schemes, adopted from the RF domain, that was proposed to be implemented in VLC in order to increase the data transmission rate. To the best of the author’s knowledge, the microLED/CCFBK driver is the first CMOS driver for microLED that was designed to perform analogue modulation for VLC purposes. The driver is characterised and shows the ability to produce up to 3.5mW of optical power with a data transmission rate of up to 486Mbit/s. The microLED/CMOS Optical Feedback (COFBK) driver is the third microLED/CMOS IC presented in this thesis. The driver looks to improve on the performance of the microLED/CCFBK driver. OFDM transmission requires high linearity to ensure low Bit Error Rate (BER) transmission. However, the optical power output of an LED is not, in general, linear with the input voltage signal. The microLED/COFBK driver looks to increase the linearity of the optical power output by integrating a microLED and a photodiode in a single pixel to create a feedback loop. Once again, to the best of the author’s knowledge, the microLED/COFBK driver is the first CMOS driver for microLED which integrates both optical source and sensor in a single pixel to help linearise the optical power output for communication purposes; in this case, VLC. For a similar range of optical power, the microLED/COFBK driver shows a reduction about 5.3% in the degree of non-linearity compared to the microLED/CCFBK driver and produces lower Total Harmonic Distortion (THD). The microLED/COFBK driver showed the potential to increase the data rate by a factor of four over that of microLED/CCFBK driver. The analogue modulated microLED/CMOS ICs described here are the first-generation drivers that have demonstrated the possibilities to increase the data rate using OFDM. A number of possible design improvements have been identified which will enhance future performance and integration with the standard VLC system.

This thesis addresses the problem of constructing a flawless subarray from a defective VLSI/WSI array consists of identical cells such as memory cells or processors. In contrast to the redundancy approach in which some cells are dedicated as spares, all the cells in the degradation approach are treated in a uniform way. Each cell can be either fault-free or defective and a subarray which contains no faulty cell is derived under constraints of switching and routing mechanisms. Although extensive literatures exist concerning spare allocation and reconfiguration in arrays with redundancy, little research has been published on optimal reconfiguration in a degradable array. A systematic method based on graph theoretic models is developed to deal with the problem. The complexities of reconfiguration are analyzed for schemes using different switching mechanisms. Efficient heuristic algorithms are presented to determine a target subarray from the defective host array.

Large-scale reconfigurable and programmable analog devices provide a new option for prototyping and synthesizing analog circuits for analog signal processing and beyond. Field-programmable analog arrays (FPAAs) built upon floating gate transistor technologies provide the analog reconfigurability and programmability density required for large-scale devices on a single integrated circuit (IC). A wide variety of synthesized circuits, such as OTA followers, band-pass filters, and capacitively coupled summation/difference circuits, were measured to demonstrate the flexibility of FPAAs. Three generations of devices were designed and tested to verify the viability of such floating gate based large-scale FPAAs. Various architectures and circuit topologies were also designed and tested to explore the trade-offs present in reconfigurable analog systems. In addition, large-scale FPAAs have been incorporated into class laboratory exercises, which provide students with a much broader range of circuit and IC design experiences than have been previously possible. By combining reconfigurable analog technologies with an equivalent large-scale digital device, such as a field-programmable gate array (FPGA), an extremely powerful and flexible mixed signal development system can be produced that will enable all of the benefits possible through cooperative analog/digital signal processing (CADSP).

This thesis presents various integrated antenna solutions for different types of systems and applications, e.g. wireless sensors, broadband handsets, advanced base stations, MEMS-based reconfigurable front-ends, automotive anti-collision radars, and large area electronics. For wireless sensor applications, a T-matched dipole is proposed and integrated in an electrically small body-worn sensor node. Measurement techniques are developed to characterize the port impedance and radiation properties. Possibilities and limitations of the planar inverted cone antenna (PICA) for small handsets are studied experimentally. Printed slot-type and folded PICAs are demonstrated for UWB handheld terminals. Both monolithic and hybrid integration are applied for electrically steerable array antennas. Compact phase shifters within a traveling wave array antenna architecture, on single layer substrate, is investigated for the first time. Radio frequency MEMS switches are utilized to improve the performance of reconfigurable antennas at higher frequencies. Using monolithic integration, a 20 GHz switched beam antenna based on MEMS switches is implemented and evaluated. Compared to similar work published previously, complete experimental results are here for the first time reported. Moreover, a hybrid approach is used for a 24 GHz switched beam traveling wave array antenna. A MEMS router is fabricated on silicon substrate for switching two array antennas on a LTCC chip. A concept of nano-wire based substrate integrated waveguides (SIW) is proposed for millimeter-wave applications. Antenna prototypes based on this concept are successfully demonstrated for automotive radar applications. W-band body-worn nonlinear harmonic radar reflectors are proposed as a means to improve automotive radar functionality. Passive, semi-passive and active nonlinear reflectors consisting of array antennas and nonlinear circuitry on flex foils are investigated. A new stretchable RF electronics concept for large area electronics is demonstrated. It incorporates liquid metal into microstructured elastic channels. The prototypes exhibit high stretchability, foldability, and twistability, with maintained electrical properties.
wisenet

Real-time image processing involves processing a wide spectrum of algorithms on huge data sets. Processing at the pixel data rate demands more powerful parallel machines than those developed for conventional image processing. This research takes advantage of current VLSI technology to examine a new approach for processing arbitrary algorithms at real-time data rate. It is based on embedding the algorithms, expressed by their dependency graphs, into two dimensional regularly connected processing arrays. Each node in a graph represents an operation which can be processed by an individual processor in the array. The embedding is performed such that data can be processed in a pipeline fashion as they are received. The result is a machine which exploits functional parallelism and data pipelining simultaneously. The presentation is divided into three parts: the first discusses graphical representation for general image processing algorithms, taking into account the nature of the data flow in real-time systems. The conditions for pipelining the processing of the graph are derived. Next the logical design of a class of VLSI arrays is considered. These arrays can be configured to embed arbitrary problem graphs. The discussion involves the architecture of the array, the architecture of its processing elements and an efficient programming scheme. Finally, static embedding of the dependency graphs into the proposed array is considered. Lower and upper bounds on the area needed to embed any graph are found. Three heuristic procedures to embed the graph at minimum cost are developed, implemented and tested.
Ph. D.
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The effectiveness of implementing field programmable gate arrays (FPGAs) in communication, military, space and high radiation environment applications, coupled with the increased accessibility of private individuals and researchers to launch satellites, has led to an increased interest in commercial off the shelf components. The metal oxide semiconductor (MOS) structures of FPGAs however, are sensitive to radiation effects which can lead to decreased reliability of the device. In order to successfully implement a FPGA based system in a radiation environment, such as on-board a satellite, the single event upset (SEU) and total ionizing dose (TID) characteristics of the device must first be established. This research experimentally determines a research procedure which could accurately determine the SEU cross sections and TID characteristics of various mitigation techniques as well as control circuits implemented in a ProASIC3 A3P1000 FPGA. To gain an understanding of the SEU effects of the implemented circuits, the test FPGA was irradiated by a 66MeV proton beam at the iTemba LABS facility. Through means of irradiation, the SEU cross section of various communication, motor control and mitigation schemes circuits, induced by high energy proton strikes was investigated. The implementation of a full global triple modular redundancy (TMR) and a combination of TMR and a AND-OR multiplexer filter was found to most effectively mitigate SEUs in comparison to the other techniques. When comparing the communication and motor control circuits, the high frequency I2C and SPI circuits experienced a higher number of upsets when compared to a low frequency servo motor control circuit. To gain a better understanding of the absorbed dose effects, experimental TID testing was conducted by irradiating the test FPGA with a cobalt-60 (Co-60) source. An accumulated absorbed dose resulted in the fluctuation of the device supply current and operating voltages as well as resulted in output errors. The TMR and TMR filtering combination mitigation techniques again were found to be the most effective methods of mitigation.

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Paul Hasler; Committee Member: Christopher Rozell; Committee Member: David Anderson. Part of the SMARTech Electronic Thesis and Dissertation Collection.

This thesis reports the development of low-cost uncooled microbolometer focal plane arrays (FPAs) together with their integrated readout circuitry for infrared night vision applications. Infrared microbolometer detectors are based on suspended and thermally isolated p+-active/n-well diodes fabricated using a standard 0.35 µ
m CMOS process followed by a simple post-CMOS bulk-micromachining process. The post-CMOS process does not require any critical lithography or complicated deposition steps
and therefore, the FPA cost is reduced considerably. The integrated readout circuitry is developed specially for the p+-active/n-well diode microbolometers that provides lower input referred noise voltage than the previously developed microbolometer readout circuits suitable for the diode type microbolometers. Two FPAs with 64 ×
64 and 128 ×
128 array formats have been implemented together with their low-noise integrated readout circuitry. These FPAs are first of their kinds where such large format uncooled infrared FPAs are designed and fabricated using a standard CMOS process. The fabricated detectors have a temperature coefficient of -2 mV/K, a thermal conductance value of 1.55 ×
10-7 W/K, and a thermal time constant value of 36 ms, providing a measured DC responsivity (&
#8476
) of 4970 V/W under continuous bias. The measured detector noise is 0.69 µ
V in 8 kHz bandwidth, resulting a measured detectivity (D*) of 9.7 ×
108 cm&
#8730
Hz/W. The 64 ×
64 FPA chip has 4096 pixels scanned by an integrated 16-channel parallel readout circuit composed of low-noise differential transconductance amplifiers, switched capacitor integrators, and sample-and-hold circuits. It measures 4.1 mm ×
5.4 mm, dissipates 25 mW power, and provides an estimated NETD value of 0.8 K at 30 frames/sec (fps) for an f/1 optics. The measured uncorrected voltage non-uniformity for the 64 ×
64 array after the CMOS fabrication is 0.8 %, which is reduced further down to 0.2 % for the 128 ×
128 array using an improved FPA structure that can compensate for the fixed pattern noise due to the FPA routing. The 128 ×
128 FPA chip has 16384 microbolometer pixels scanned by a 32-channel parallel readout circuitry. The 128 ×
128 FPA measures 6.6 mm ×
7.9 mm, includes a PTAT temperature sensor and a vacuum sensor, dissipates 25 mW power, and provides an estimated NETD value of 1 K at 30 fps for an f/1 optics. These NETD values can be decreased below 350 mK with further optimization of the readout circuit and post-CMOS etching steps. Hence, the proposed method is very cost-effective to fabricate large format focal plane arrays for very low-cost infrared imaging applications.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.
Kucic, Matthew, Committee Member ; Hasler, Paul, Committee Chair ; Heck, Bonnie, Committee Member ; Cressler, John, Committee Member ; Anderson, David, Committee Member. Vita. Includes bibliographical references.

A comprehensive study of the High-pass/Low-pass topology has been performed, increasing the understanding of error sources arising from bit layout issues and fabrication tolerances. This included a detailed analysis of error sources in monolithic microwave phase shifters due to device size limitations, inductor parasitics, loading effects, and non-ideal switches. Each component utilized in the implementation of a monolithic high-low pass phase shifter was analyzed, with its influence on phase behavior shown in detail. An emphasis was placed on the net impact on absolute phase variation, which is critical to the system performance of a phased array radar system. The design of the individual phase shifter filter sections, and the influence of bit ordering on overall performance was also addressed. A variety of X-band four- and five-bit phase shifters were fabricated in a 200 GHz SiGe HBT BiCMOS technology platform, and further served to validate the analysis and design methodology. The SiGe phase shifter can be successfully incorporated into a single-chip T/R module forming a system-on-a-chip (SoC). Reduction in the physical size of transmission lines was shown to be a possibility with spinel magnetic nanoparticle films. The signal transmission properties of phase lines treated with nanoparticle thin films were examined, showing the potential for significant size reduction in both delay line and High-pass/Low-pass phase topologies. Wide-band, low-loss, and near-hermetic packaging techniques for RF MEMS devices were presented. A thermal compression bonding technique compatible with standard IC fabrication techniques was shown, that uses a low temperature thermal compression bonding method that avoids plastic deformations of the MEMS membrane. Ultimately, a system-on-a-package (SoP) approach was demonstrated that utilized packaged RF MEMS switches to maintain the performance of the SiGe phase shifter with much lower loss. The extremely competitive performance of the MEMS-based High-pass/Low-pass phase shifter, despite the lack of the extensive toolkits and commercial fabrication facilities employed with the active-based SiGe phase shifters, confirms both the effectiveness of the detailed phase error analysis presented in this work and the robust nature of the High-pass/Low-pass topology.

The FPGA GPU architecture proposed in this thesis was motivated by underserved markets for graphics processing that desire flexibility, long-term device availability, scalability, certifiability, and high reliability. These markets of industrial, medical, and avionics applications often are forced to rely on the latest GPUs that were actually designed for gaming PCs or handheld consumer devices. The architecture for the GPU in this thesis was crafted specifically for an FPGA and therefore takes advantage of its capabilities while also avoiding its limitations. Previous work did not specifically exploit the FPGA's structures and instead used FPGA implementations merely as an integration platform prior to proceeding on to a final ASIC design. The target of an FPGA for this architecture is also important because its flexibility and programmability allow the GPU's performance to be scaled or supplemented to fit unique application requirements. This tailoring of the architecture to specific requirements minimizes power consumption and device cost while still satisfying performance, certification, and device availability requirements. To demonstrate the feasibility of the flexible FPGA GPU architectural concepts, the architecture is applied to an avionics application and analyzed to confirm satisfactory results. The architecture is further validated through the development of extensions to support more comprehensive graphics processing applications. In addition, the breadth of this research is illustrated through its applicability to general-purpose computations and more specifically, scientific visualizations.

[EN] The processing of radiofrequency signals using photonics means is a discipline that appeared almost at the same time as the laser and the optical fibre. Photonics offers the capability of managing broadband radiofrequency (RF) signals thanks to its low transmission attenuation, a variety of linear and non-linear phenomena and, recently, the potential to implement integrated photonic subsystems. These features open the door for the implementation of multiple functionalities including optical transportation, up and down frequency conversion, optical RF filtering, signal multiplexing, de-multiplexing, routing and switching, optical sampling, tone generation, delay control, beamforming and photonic generation of digital modulations, and even a combination of several of these functionalities. This thesis is focused on the application of vector processing in the optical domain to radiofrequency signals in two fields of application: optical beamforming, and photonic vector modulation and demodulation of digital quadrature amplitude modulations. The photonic vector control enables to adjust the amplitude and phase of the radiofrequency signals in the optical domain, which is the fundamental processing that is required in different applications such as beamforming networks for direct radiating array (DRA) antennas and multilevel quadrature modulation. The work described in this thesis include different techniques for implementing a photonic version of beamforming networks for direct radiating arrays (DRA) known as optical beamforming networks (OBFN), with the objectives of providing a precise control in terrestrial applications of broadband signals at very high frequencies above 40 GHz in communication antennas, optimizing the size and mass when compared with the electrical counterparts in space application, and presenting new photonic-based OBFN functionalities. Thus, two families of OBFNs are studied: fibre-based true time delay architectures and integrated networks. The first allow the control of broadband signals using dispersive optical fibres with wavelength division multiplexing techniques and advanced functionalities such as direction of arrival estimation in receiving architectures. In the second, passive OBFNs based on monolithically-integrated Optical Butler Matrices are studied, including an ultra-compact solution using optical heterodyne techniques in silicon-on-insulator (SOI) material, and an alternative implementing a homodyne counterpart in germanium doped silica material. In this thesis, the application of photonic vector processing to the generation of quadrature digital modulations has also been investigated. Multilevel modulations are based on encoding digital information in discrete states of phase and amplitude of an electrical signal to enhance spectral efficiency, as for instance, in quadrature modulation. The signal process required for generating and demodulating this kind of signals involves vector processing (phase and amplitude control) and frequency conversion. Unlike the common electronic or digital implementation, in this thesis, different photonic based signal processing techniques are studied to produce digital modulation (photonic vector modulation, PVM) and demodulation (PVdM). These techniques are of particular interest in the case of broadband signals where the data rate required to be managed is in the order of gigabit per second, for applications like wireless backhauling of metro optical networks (known as fibre-to-the-air). The techniques described use optical dispersion in optical fibres, wavelength division multiplexing and photonic up/down conversion. Additionally, an optical heterodyne solution implemented monolithically in a photonic integrated circuit (PIC) is also described.
[ES] El procesamiento de señales de radiofrecuencia (RF) utilizando medios fotónicos es una disciplina que apareció casi al mismo tiempo que el láser y la fibra óptica. La fotónica ofrece la capacidad de manipular señales de radiofrecuencia de banda ancha, una baja atenuación, procesados basados en una amplia variedad de fenómenos lineales y no lineales y, recientemente, el potencial para implementar subsistemas fotónicos integrados. Estas características ofrecen un gran potencial para la implementación de múltiples funcionalidades incluyendo transporte óptico, conversión de frecuencia, filtrado óptico de RF, multiplexación y demultiplexación de señales, encaminamiento y conmutación, muestreo óptico, generación de tonos, líneas de retardo, conformación de haz en agrupaciones de antenas o generación fotónica de modulaciones digitales, e incluso una combinación de varias de estas funcionalidades. Esta tesis se centra en la aplicación del procesamiento vectorial en el dominio óptico de señales de radiofrecuencia en dos campos de aplicación: la conformación óptica de haces y la modulación y demodulación vectorial fotónica de señales digitales en cuadratura. El control fotónico vectorial permite manipular la amplitud y fase de las señales de radiofrecuencia en el dominio óptico, que es el procesamiento fundamental que se requiere en diferentes aplicaciones tales como las redes de conformación de haces para agrupaciones de antenas y en la modulación en cuadratura. El trabajo descrito en esta tesis incluye diferentes técnicas para implementar una versión fotónica de las redes de conformación de haces de en agrupaciones de antenas, conocidas como redes ópticas de conformación de haces (OBFN). Se estudian dos familias de redes: arquitecturas de retardo en fibra óptica y arquitecturas integradas. Las primeras permiten el control de señales de banda ancha utilizando fibras ópticas dispersivas con técnicas de multiplexado por división de longitud de onda y funcionalidades avanzadas tales como la estimación del ángulo de llegada de la señal en la antena receptora. En la segunda, se estudian redes de conformación pasivas basadas en Matrices de Butler ópticas integradas, incluyendo una solución ultra-compacta utilizando técnicas ópticas heterodinas en silicio sobre aislante (SOI), y una alternativa homodina en sílice dopado con germanio. En esta tesis, también se han investigado técnicas de procesado vectorial fotónico para la generación de modulaciones digitales en cuadratura. Las modulaciones multinivel codifican la información digital en estados discretos de fase y amplitud de una señal eléctrica para aumentar su eficiencia espectral, como por ejemplo la modulación en cuadratura. El procesado necesario para generar y demodular este tipo de señales implica el procesamiento vectorial (control de amplitud y fase) y la conversión de frecuencia. A diferencia de la implementación electrónica o digital convencional, en esta tesis se estudian diferentes técnicas de procesado fotónico tanto para la generación de modulaciones digitales (modulación vectorial fotónica, PVM) como para su demodulación (PVdM). Esto es de particular interés en el caso de señales de banda ancha, donde la velocidad de datos requerida es del orden de gigabits por segundo, para aplicaciones como backhaul inalámbrico de redes ópticas metropolitanas (conocida como fibra hasta el aire). Las técnicas descritas se basan en explotar la dispersión cromática de la fibra óptica, la multiplexación por división de longitud de onda y la conversión en frecuencia. Además, se presenta una solución heterodina implementada monolíticamente en un circuito integrado fotónico (PIC).
[CAT] El processament de senyals de radiofreqüència (RF) utilitzant mitjans fotònics és una disciplina que va aparèixer gairebé al mateix temps que el làser i la fibra òptica. La fotònica ofereix la capacitat de manipular senyals de radiofreqüència de banda ampla, una baixa atenuació, processats basats en una àmplia varietat de fenòmens lineals i no lineals i, recentment, el potencial per implementar subsistemes fotònics integrats. Aquestes característiques ofereixen un gran potencial per a la implementació de múltiples funcionalitats incloent transport òptic, conversió de freqüència, filtrat òptic de RF, multiplexació i demultiplexació de senyals, encaminament i commutació, mostreig òptic, generació de tons, línies de retard, conformació de feix en agrupacions d'antenes i la generació fotònica de modulacions digitals, i fins i tot una combinació de diverses d'aquestes funcionalitats. Aquesta tesi es centra en l'aplicació del processament vectorial en el domini òptic de senyals de radiofreqüència en dos camps d'aplicació: la conformació òptica de feixos i la modulació i demodulació vectorial fotònica de senyals digitals en quadratura. El control fotònic vectorial permet manipular l'amplitud i la fase dels senyals de radiofreqüència en el domini òptic, que és el processament fonamental que es requereix en diferents aplicacions com ara les xarxes de conformació de feixos per agrupacions d'antenes i en modulació multinivell. El treball descrit en aquesta tesi inclou diferents tècniques per implementar una versió fotònica de les xarxes de conformació de feixos en agrupacions d'antenes, conegudes com a xarxes òptiques de conformació de feixos (OBFN), amb els objectius de proporcionar un control precís en aplicacions terrestres de senyals de banda ampla a freqüències molt altes per sobre de 40 GHz en antenes de comunicacions, optimitzant la mida i el pes quan es compara amb els homòlegs elèctrics en aplicacions espacials, i la presentació de noves funcionalitats fotòniques per agrupacions d'antenes. Per tant, s'estudien dues famílies de OBFNs: arquitectures de retard en fibra òptica i arquitectures integrades. Les primeres permeten el control de senyals de banda ampla utilitzant fibres òptiques dispersives amb tècniques de multiplexació per divisió en longitud d'ona i funcionalitats avançades com ara l'estimació de l'angle d'arribada del senyal a l'antena receptora. A la segona, s'estudien xarxes de conformació passives basades en Matrius de Butler òptiques en fotònica integrada, incloent una solució ultra-compacta utilitzant tècniques òptiques heterodinas en silici sobre aïllant (SOI), i una alternativa homodina en sílice dopat amb germani. D'altra banda, també s'ha investigat en aquesta tesi tècniques de processament vectorial fotònic per a la generació de modulacions digitals en quadratura. Les modulacions multinivell codifiquen la informació digital en estats discrets de fase i amplitud d'un senyal elèctric per augmentar la seva eficiència espectral, com ara la modulació en quadratura. El processat necessari per generar i desmodular aquest tipus de senyals implica el processament vectorial (control d'amplitud i fase) i la conversió de freqüència. A diferència de la implementació electrònica o digital convencional, en aquesta tesi s'estudien diferents tècniques de processament fotònic tant per a la generació de modulacions digitals (modulació vectorial fotònica, PVM) com per la seva demodulació (PVdM). Això és de particular interès en el cas de senyals de banda ampla, on la velocitat de dades requerida és de l'ordre de gigabits per segon, per a aplicacions com backhaul sense fils de xarxes òptiques metropolitanes (coneguda com fibra fins l'aire). Les tècniques descrites es basen en explotar la dispersió cromàtica de la fibra òptica, la multiplexació per divisió en longitud d'ona i la conversió en freqüència. A més, es prese
Piqueras Ruipérez, MÁ. (2016). Photonic Vector Processing Techniques for Radiofrequency Signals [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/63264
TESIS

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Committee Chair: Anderson, David; Committee Member: Habetler, Thomas; Committee Member: Hasler, Paul; Committee Member: McClellan, James; Committee Member: Minch, Bradley.

The objective of the proposed research is to develop solutions for High-Performance Low-Cost Passives for Radar, Identification, and Communication Applications up to mm-Wave Frequencies. This research will bring to the table potential solutions that will meet three main requirements: small size (or low weight), high performance, and low cost. This research embarks on antenna design and development for passive RFID tags on LCP substrates, and then a transition towards lower cost modules investigates and explores the possibilities of using paper as RF substrates with inkjet printing as a low cost fabrication technology. Modules such as dual band antenna for Wifi frequencies (2.4 GHz and 5 GHz) and UWB (up to 10GHz) on paper substrate using inkjet printing are presented. This work then bridges into developing higher frequency modules. These include: highly selective filter design on LCP for X-band Radar application to be used as a benchmark for an easy adjustment for higher frequencies, and antenna modules LCP using inkjet printing for communication such as mm-Wave WLAN or WPAN. A transition into mm-Wave Modules then takes place for the general realization of low-cost high-performance mm-Wave modules and more specifically the low cost automotive radar. After proposing an architecture for integrated mm-Wave module, this work then investigates 2D/3D interconnections (and their integration with antennas) on LCP using conventional etching design guidelines up to 100GHz. Antenna arrays that are implemented with phase shifters for beam steering are then designed using edge fed and multilayer technology. Furthermore, crosstalk reductions for highly dense transmission lines are analyzed via simulations for the optimum performance and space saving of such mm-Wave modules such as the IC interface where space restrictions are strictly enforced.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Tentzeris, Manos; Committee Member: DeJean, Gerald; Committee Member: Ingram, Mary; Committee Member: Kavadias, Stylianos; Committee Member: Laskar, Joy. Part of the SMARTech Electronic Thesis and Dissertation Collection.