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Wang, Jun. "Physical design with fabrication : friendly layout /." View the Table of Contents & Abstract, 2004. http://sunzi.lib.hku.hk/hkuto/record/B30575643.
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Salah, Ben Romdhane Mohamed. "Design synthesis of application-specification ICs for DSP." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/15392.
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Staunstrup, Jørgen. "A formal approach to hardware design /." Boston [u.a.] : Kluwer Acad. Publ, 1994. http://www.loc.gov/catdir/enhancements/fy0820/93043582-d.html.
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Wang, Jun, and 王雋. "Physical design with fabrication: friendly layout." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2004. http://hub.hku.hk/bib/B45015119.
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Son, Kyung-Im. "A multi-class, multi-dimensional classifier as a topology selector for analog circuit design / by Kyung-Im Son." Thesis, Connect to this title online; UW restricted, 1998. http://hdl.handle.net/1773/5919.
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Sivaraman, Guru. "An emulation-based methodology for integrating design, testing and diagnosis of application-specific integrated circuits." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36470.
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Rachamadugu, Arun. "Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26603.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Laskar, Joy; Committee Member: Anderson, David; Committee Member: Cressler, John. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Rodriguez, Luis. "Design of a Monolithic Bipolar Junction Transistor Amplifier in the Common Emitter with Cascaded Common Collector Configuration." Honors in the Major Thesis, University of Central Florida, 2004. http://digital.library.ucf.edu/cdm/ref/collection/ETH/id/724.
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This item is only available in print in the UCF Libraries. If this is your Honors Thesis, you can help us make it available online for use by researchers around the world by following the instructions on the distribution consent form at http://library.ucfBachelors
Engineering and Computer Science
Electrical Engineering
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Kanitkar, Hrishikesh. "Subthreshold circuits : design, implementation and application /." Online version of thesis, 2009. http://hdl.handle.net/1850/8926.
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Long, Ethan Schuyler. "The Role of Temperature in Testing Deep Submicron CMOS ASICs." PDXScholar, 2003. https://pdxscholar.library.pdx.edu/open_access_etds/34.
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Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25μm and 0.18μm CMOS ASICs fabricated by LSI Logic. An IC’s performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC’s constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.
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Radhakrishnan, Swarnalatha Computer Science & Engineering Faculty of Engineering UNSW. "Heterogeneous multi-pipeline application specific instruction-set processor design and implementation." Awarded by:University of New South Wales. Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/29161.
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Embedded systems are becoming ubiquitous, primarily due to the fast evolution of digital electronic devices. The design of modern embedded systems requires systems to exhibit, high performance and reliability, yet have short design time and low cost. Application Specific Instruction set processors (ASIPs) are widely used in embedded system since they are economical to use, flexible, and reusable (thus saves design time). During the last decade research work on ASIPs have been carried out in mainly for single pipelined processors. Improving performance in processors is possible by exploring the available parallelism in the program. Designing of multiple parallel execution paths for parallel execution of the processor naturally incurs additional cost. The methodology presented in this dissertation has addressed the problem of improving performance in ASIPs, at minimal additional cost. The devised methodology explores the available parallelism of an application to generate a multi-pipeline heterogeneous ASIP. The processor design is application specific. No pre-defined IPs are used in the design. The generated processor contains multiple standalone pipelined data paths, which are not necessarily identical, and are connected by the necessary bypass paths and control signals. Control unit are separate for each pipeline (though with the same clock) resulting in a simple and cost effective design. By using separate instruction and data memories (Harvard architecture) and by allowing memory access by two separate pipes, the complexity of the controller and buses are reduced. The impact of higher memory latencies is nullified by utilizing parallel pipes during memory access. Efficient bypass network selection and encoding techniques provide a better implementation. The initial design approach with only two pipelines without bypass paths show speed improvements of up to 36% and switching activity reductions of up to 11%. The additional area costs around 16%. An improved design with different number of pipelines (more than two) based on applications show on average of 77% performance improvement with overheads of: 49% on area; 51% on leakage power; 17% on switching activity; and 69% on code size. The design was further trimmed, with bypass path selection and encoding techniques, which show a saving of up to 32% of area and 34% of leakage power with 6% performance improvement and 69% of code size reduction compared to the design approach without these techniques in the multi pipeline design.
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Herbert, J. M. J. "Application of formal methods to digital system design." Thesis, University of Cambridge, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.233985.
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Connor, John. "The RIT IEEE-488 Buffer design /." Online version of thesis, 1992. http://hdl.handle.net/1850/11259.
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Sistla, Anil Kumar. "Design Space Exploration of Domain Specific CGRAs Using Crowd-sourcing." Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc699959/.
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CGRAs (coarse grained reconfigurable array architectures) try to fill the gap between FPGAs and ASICs. Over three decades, the research towards CGRA design has produced number of architectures. Each of these designs lie at different points on a line drawn between FPGAs and ASICs, depending on the tradeoffs and design choices made during the design of architectures. Thus, design space exploration (DSE) takes a very important role in the circuit design process. In this work I propose the design space exploration of CGRAs can be done quickly and efficiently through crowd-sourcing and a game driven approach based on an interactive mapping game UNTANGLED and a design environment called SmartBricks. Both UNTANGLED and SmartBricks have been developed by our research team at Reconfigurable Computing Lab, UNT. I present the results of design space exploration of domain-specific reconfigurable architectures and compare the results comparing stripe vs mesh style, heterogeneous vs homogeneous. I also compare the results obtained from different interconnection topologies in mesh. These results show that this approach offers quick DSE for designers and also provides low power architectures for a suite of benchmarks. All results were obtained using standard cell ASICs with 90 nm process.
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Nguyen, Huy Tam. "Numerical transformations for area, power, and testability optimization in the synthesis of digtal signal processing ASICs." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/13548.
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Mutigwe, Charles. "Automatic synthesis of application-specific processors." Thesis, Bloemfontein : Central University of Technology, Free State, 2012. http://hdl.handle.net/11462/163.
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Thesis (D. Tech. (Engineering: Electrical)) -- Central University of technology, Free State, 2012This thesis describes a method for the automatic generation of appli- cation speci_c processors. The thesis was organized into three sepa- rate but interrelated studies, which together provide: a justi_cation for the method used, a theory that supports the method, and a soft- ware application that realizes the method. The _rst study looked at how modern day microprocessors utilize their hardware resources and it proposed a metric, called core density, for measuring the utilization rate. The core density is a function of the microprocessor's instruction set and the application scheduled to run on that microprocessor. This study concluded that modern day microprocessors use their resources very ine_ciently and proposed the use of subset processors to exe- cute the same applications more e_ciently. The second study sought to provide a theoretical framework for the use of subset processors by developing a generic formal model of computer architecture. To demonstrate the model's versatility, it was used to describe a number of computer architecture components and entire computing systems. The third study describes the development of a set of software tools that enable the automatic generation of application speci_c proces- sors. The FiT toolkit automatically generates a unique Hardware Description Language (HDL) description of a processor based on an application binary _le and a parameterizable template of a generic mi- croprocessor. Area-optimized and performance-optimized custom soft processors were generated using the FiT toolkit and the utilization of the hardware resources by the custom soft processors was character- ized. The FiT toolkit was combined with an ANSI C compiler and a third-party tool for programming _eld-programmable gate arrays (FPGAs) to create an unconstrained C-to-silicon compiler.
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Franz, Jonathan D. Duren Russell Walker. "An evaluation of CoWare Inc.'s Processor Designer tool suite for the design of embedded processors." Waco, Tex. : Baylor University, 2008. http://hdl.handle.net/2104/5254.
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Severino, Raffaele Roberto. "Design methodology for millimeter wave integrated circuits : application to SiGe BiCMOS LNAs." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14284/document.
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Grace aux récents développements des technologies d’intégration, il est aujourd’hui possible d’envisager la réalisation de circuits et systèmes intégrés sur Silicium fonctionnant à des fréquences auparavant inatteignables. Par conséquence, depuis quelques années, on assiste à la naissance de nouvelles applications en bande millimétrique, comme la communication sans fil à haut-débit à 60GHz, les radars automobiles à 76-77 et 79-82GHz, et l’imagerie millimétrique à 94GHz.Cette thèse vise, en premier lieu, à la définition d’une méthodologie de conception des circuits intégrés en bande millimétrique. Elle est par la suite validée au travers de son application à la conception des amplificateurs faible-bruit en technologie BiCMOS SiGe. Dans ce contexte, une attention particulière a été portée au développement d’une stratégie de conception et de modélisation des inductances localisées. Plusieurs exemples d’amplificateurs faible-bruit ont été réalisés, à un ou deux étages, employant des composants inductifs localisés ou distribués, à 60, 80 et 94 GHz. Tous ces circuits présentent des caractéristiques au niveau de l’état de l’art dans le domaine, ainsi en confirmant l’exactitude de la méthodologie de conception et son efficacité sur toute la planche de fréquence considérée. En outre, la réalisation d’un récepteur intégré pour applications automobiles à 80GHz est aussi décrite comme exemple d’une possible application système, ainsi que la co-intégration d’un amplificateur faible-bruit avec une antenne patch millimétrique intégrée sur SiliciumThe interest towards millimeter waves has rapidly grown up during the last few years, leading to the development of a large number of potential applications in the millimeter wave band, such as WPANs and high data rate wireless communications at 60GHz, short and long range radar at 77-79GHz, and imaging systems at 94GHz.Furthermore, the high frequency performances of silicon active devices (bipolar and CMOS) have dramatically increased featuring both fT and fmax close or even higher than 200GHz. As a consequence, modern silicon technologies can now address the demand of low-cost and high-volume production of systems and circuits operating within the millimeter wave range. Nevertheless, millimeter wave design still requires special techniques and methodologies to overcome a large number of constraints which appear along with the augmentation of the operative frequency.The aim of this thesis is to define a design methodology for integrated circuits operating at millimeter wave and to provide an experimental validation of the methodology, as exhaustive as possible, focusing on the design of low noise amplifiers (LNAs) as a case of study.Several examples of LNAs, operating at 60, 80, and 94 GHz, have been realized. All the tested circuits exhibit performances in the state of art. In particular, a good agreement between measured data and post-layout simulations has been repeatedly observed, demonstrating the exactitude of the proposed design methodology and its reliability over the entire millimeter wave spectrum. A particular attention has been addressed to the implementation of inductors as lumped devices and – in order to evaluate the benefits of the lumped design – two versions of a single-stage 80GHz LNA have been realized using, respectively, distributed transmission lines and lumped inductors. The direct comparison of these circuits has proved that the two design approaches have the same potentialities. As a matter of fact, design based on lumped inductors instead of distributed elements is to be preferred, since it has the valuable advantage of a significant reduction of the circuit dimensions.Finally, the design of an 80GHz front-end and the co-integration of a LNA with an integrated antenna are also considered, opening the way to the implementation a fully integrated receiver
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Cheung, Newton Computer Science & Engineering Faculty of Engineering UNSW. "Design automation methodologies for extensible processor platform." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2005. http://handle.unsw.edu.au/1959.4/26118.
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This thesis addresses two ubiquitous trends in the embedded system world - the increasing importance of design turnaround time as a design metric, and the move towards closing the design productivity gap. Adopting the right choice of design approach has been recognised as an integral part of the design flow in order to meet desired characteristics such as increasing software content, satisfying the growing complexities of an application, reusing off-the-shelf components, and exploring design metrics tradeoff, which closes the design productivity gap. The importance of design turnaround time is motivated by the intensive competition between manufacturers, especially makers of mainstream electronic consumer products, who shrinks the product life cycle and requires faster time-to-market to maximise economic benefits. This thesis presents a suite of design automation methodologies to automatically design embedded systems for an application in the state-of-the-art design approach - the extensible processor platform. These design automation methodologies systematise the extensible processor platform???s design flow, with particular emphasis on solving four challenging design problems: i) code segment identification; ii) instruction generation; iii) architectural customisation selection; and iv) processor evaluation. Our suite of design automation methodologies includes: i) a semi-automatic design system - to design an extensible processor that maximises the application performance while satisfying the area constraint. By specifying a fitting function to identify suitable code segments within an application, a two-level hierarchy selection algorithm is used to first select a predefined processor and then select the right instruction, and a performance estimator is used to estimate an application's performance; ii) a tool to match instructions - to automatically match the pre-designed instructions with computationally intensive code segments, reducing verification time and effort; iii) an instructions estimation model - to estimate the area overhead, latency, power consumption of extensible instructions, exploring larger design space; and iv) an instructions generation tool - to generate new extensible instructions that maximises the speedup while minimising power dissipation. A number of techniques such as system decomposition, combinational equivalence checking and regression analysis etc., have been heavily relied upon in the creation of the final design system. This thesis shows results at every stage to demonstrate the efficacy of our design methodologies in the creation of extensible processors. The methodologies and results presented in this thesis demonstrate that automating the design process for an extensible processor platform results in significant performance increase - on average, an increase of 4.74x (up to 15.71x) compared to the original base processor. Our system achieves significant design turnaround time savings (2.5% of the full simulation time for the entire design space) with majority Pareto points obtained (91% on average), and can lead to fewer and faster design iterations. Our instruction matching tool is 7.3x faster on average compared to the best known approaches to the problem (partial simulations). Our estimation model has a mean absolute error as small as 3.4% (6.7% max.) for area overhead, 5.9% (9.4% max.) for latency, and 4.2% (7.2% max.) for power consumption, compared to estimation through the time consuming synthesis and simulation steps using commercial tools. Finally, the instruction generation tool reduces energy consumption by a further 5.8% on average (up to 17.7%) compared to extensible instructions generated by previous approaches.
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Economides, Sophia Betty. "Design and application of multilayer monolithic microwave integrated circuit transformers." Thesis, King's College London (University of London), 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.312971.
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Morton, Shannon V. "Fast asynchronous VSLI circuit design techniques and their application to microprocessor design /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09phm891.pdf.
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Zhang, Mingyang 1981. "Macromodeling and simulation of linear components characterized by measured parameters." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=112589.
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Recently, microelectronics designs have reached extremely high operating frequencies as well as very small die and package sizes. This has made signal integrity an important bottleneck in the design process, and resulted in the inclusion of signal integrity simulation in the computer aided design flow. However, such simulations are often difficult because in many cases it is impossible to derive analytical models for certain passive elements, and the only available data are frequency-domain measurements or full-wave simulations. Furthermore, at such high frequencies these components are distributed in nature and require a large number of poles to be properly characterized. Simple lumped equivalent circuits are therefore difficult to obtain, and more systematic approaches are required. In this thesis we study the Vector Fitting techniques for obtaining such equivalent model and propose a more streamlined approach for preserving passivity while maintaining accuracy.
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Cabanillas, Costa Josep. "Integrated Transformers and its Application to the RFIC Design." Doctoral thesis, Universitat de Barcelona, 2002. http://hdl.handle.net/10803/1506.
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The context of this thesis is the design of CMOS low power RFIC's suitable for direct conversion architectures. Our starting point is the analysis of the characteristics of the integrated passive components (inductors and mainly transformers) from a circuit designer perspective. Then, the achieved understanding of these components is exploited in order to optimize the performance of some of the building blocks of a RF front-end. This thesis is divided in three main chapters. Chapter 1 is dedicated to the analysis of integrated transformers. It starts with a revision of the state of the art of the integrated inductors in order to set up the basis for the analysis of the monolithic transformers. Due to their influence on the component quality factor, a special insight is dedicated to the analysis of the eddy currents. Then, we introduce the integrated transformers and revise the topologies used in their implementation and their characteristics and electrical equivalent models. However, it is important to remark that the goal of this thesis is not the modeling of the component. Instead, we will use EM simulators to reproduce their behavior and point out some physical mechanisms present in integrated transformers that have not been properly considered in the equivalent electrical models presented in the literature so far. In particular, we will study eddy currents in integrated transformers and will demonstrate their dependence on the operating mode of the transformer as well as on the loads connected to the primary and the secondary. As we will see this phenomenon has a direct influence on the component model as well as on the component optimization. Thus, different optimization procedures should be applied to minimize the component losses depending on the application.
Finally, this chapter finishes with the design of a double balanced mixed that uses two differential transformers to increase the isolation between ports. It is demonstrated that a differential driving minimizes the effects of the parasitic capacitances and increases noticeably this isolation. It is also shown that the etching of the silicon underneath of the integrated transformers that reduces these parasitic capacitances also increases this isolation (even if a single-ended excitation is applied).
Chapter 2 investigates the design of oscillators having low phase noise and large tunning range. After identifying the quality factor of the integrated inductors as one of the main factors limiting the oscillator phase noise, a novel transformer-based (parallel) resonator is introduced. This new topology overcomes the performance of the common inductor-based resonators in terms of tuning range and effective quality factor.
A detailed description of the resonator is then performed in order understand its potentially and limitations. Thus, its properties are firstly studied from an electrical circuit perspective using the equivalent models discussed in the previous chapter. Then, it is realized the analysis in the EM domain in order to compare its performance with the standard inductor-based resonator. Once again, eddy currents are identified as the main factor limiting the effective quality factor of the transformer-based resonator. Thanks to the already achieved understanding of integrated transformers, the layout optimization method proposed by López-Villegas [35] for integrated inductors can be extended to the optimization of the transformer (when working in common-mode). The extension of the parallel design to N-resonators is also shortly discussed. Finally, the proposed resonator is used in a low phase-noise 1.7 GHz CMOS VCO.
Chapter 3 presents a new topology of quadrature oscillator based on the differential coupling at the second harmonic of two differential oscillators. As in the previous design, an integrated transformer plays a relevant role in this circuit being used to establish the coupling between oscillators. In order to obtain a basic understanding of the phenomena involved in the generation of quadrature signals using the proposed method and set up the design procedure several concepts must be revised. In particular, the theory on forced (or injected) and coupled oscillators is discussed and applied to the proposed quadrature oscillator. Finally, to show the feasibility and potentiality of this methodology, different designs in integrated and hybrid implementations are presented.
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Seo, Chung-Seok. "Physical Design of Optoelectronic System-on-a-Chip/Package Using Electrical and Optical Interconnects: CAD Tools and Algorithms." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-11102004-150844/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.David E. Schimmel, Committee Member ; C.P. Wong, Committee Member ; John A. Buck, Committee Member ; Abhijit Chatterjee, Committee Chair ; Madhavan Swaminathan, Committee Member. Vita. Includes bibliographical references.
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al-Sarʻāwī, Said Fares. "Design techniques for low power mixed analog-digital circuits with application to smart wireless systems /." Title page, contents and abstract only, 2003. http://web4.library.adelaide.edu.au/theses/09PH/09pha461.pdf.
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Akgul, Bilge Ebru Saglam. "The System-on-a-Chip Lock Cache." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5253.
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In this dissertation, we implement efficient lock-based synchronization by
a novel, high performance, simple and scalable hardware technique and
associated software for a target shared-memory multiprocessor
System-on-a-Chip (SoC). The custom hardware part of our solution is
provided in the form of an intellectual property (IP) hardware unit which
we call the SoC Lock Cache (SoCLC). SoCLC provides effective lock hand-off
by reducing on-chip memory traffic and improving performance in terms of
lock latency, lock delay and bandwidth consumption. The proposed solution
is independent from the memory hierarchy, cache protocol and the processor
architectures used in the SoC, which enables easily applicable
implementations of the SoCLC (e.g., as a reconfigurable or partially/fully
custom logic), and which distinguishes SoCLC from previous approaches.
Furthermore, the SoCLC mechanism has been extended to support priority
inheritance with an immediate priority ceiling protocol (IPCP) implemented
in hardware, which enhances the hard real-time performance of the system.
Our experimental results in a four-processor SoC indicate that SoCLC can
achieve up to 37% overall speedup over spin-lock and up to 48% overall
speedup over MCS for a microbenchmark with false sharing. The priority
inheritance implemented as part of the SoCLC hardware, on the other hand,
achieves 1.43X speedup in overall execution time of a robot application
when compared to the priority inheritance implementation under the
Atalanta real-time operating system. Furthermore, it has been shown that
with the IPCP mechanism integrated into the SoCLC, all of the tasks of the
robot application could meet their deadlines (e.g., a high priority task
with 250us worst case response time could complete its execution in 93us
with SoCLC, however the same task missed its deadline by completing its
execution in 283us without SoCLC). Therefore, with IPCP support, our
solution can provide better real-time guarantees for real-time systems.
To automate SoCLC design, we have also developed an SoCLC-generator tool,
PARLAK, that generates user specified configurations of a custom SoCLC. We
used PARLAK to generate SoCLCs from a version for two processors with 32
lock variables occupying 2,520 gates up to a version for fourteen
processors with 256 lock variables occupying 78,240 gates.
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Green, Johney Boyd Jr. "Application of deterministic chaos theory to cyclic variability in spark-ignition engines." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/16809.
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Chadha, Vishal. "Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992.
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Rodríguez, Vilamitjana Enric. "Design-oriented model for predicting and controlling fast-scale instabilities in switching converters : application to advanced power management integrated circuits." Doctoral thesis, Universitat Politècnica de Catalunya, 2011. http://hdl.handle.net/10803/109043.
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Trends in battery-operated portable applications require further miniaturization and eventually on-chip integration of power processing circuits along with their optimum power management control circuits, considered as key components in on-chip power subsystems which have a high impact upon the overall system in terms of size and efficiency.
On-chip power management subsystems, both in regulation and more sophisticated functionalities as wideband tracking, are ideally based on power switching converters, paradigm of high efficiency circuits. These subsystems, due to their nonlinear switched dynamic nature, can exhibit various instabilities which are mainly classified as slow-scale and fast-scale instabilities, the latter also known as subharmonic oscillations. The prediction of slow-scale instabilities can be carried out by conventional averaged dynamic models, which are derived form a simple mathematical circuit analysis and have a clear design-oriented standpoint, but due to their averaged nature, they fail to predict fast-scale instabilities. Alternatively, the prediction of the overall stability boundaries within the complete design space, encompassing fast-scale subharmonic oscillations, has hitherto been addressed from an analytic standpoint based on the discrete-time model, which are based on complex analysis that yields accurate prediction results but lacks of a circuit standpoint and hence are not aligned with a design-oriented use.
In this thesis the effect of different system parameters upon the stability boundaries is explored, demonstrating that trends towards integration, namely the reduction of reactive component size or a decrease of the relative switching frequency compared to the converter natural dynamics leads to the exhibition of fast-scale instabilities. As far as characterization is concerned, a two-fold approach has been considered both exploring the complete parameter design space of the switching regulator and categorizing it in terms of which type of nonlinear dynamic performance the circuit exhibits (design space characterization), as well as providing a novel characterization of the electrical behaviour for the different dynamic modes in terms of electrical performance metrics connatural to a power processing circuit, such as voltage ripple, average switching frequency and spectra (electrical characterization).
With the aim of having a design-oriented circuit-based model for predicting subharmonic instabilities, the thesis proposes a novel approach based on considering the ripple component at the PWM modulator input as an index to predict the fast-scale stability boundary -in the particular case of a voltage-mode buck converter in continuous conduction mode, a representative case of widespread use in battery-operated applications-. This ripple-based instability index has been validated both from the instantaneous nonlinear dynamic state equations solved numerically as well as through experimental prototypes. Finally a bridge between the ripple-based index approach and the discrete-time model is established though relating the ripple and the control signal slope at the switching instant. The approach has been extended to the discontinuous conduction-mode and to current-mode control, demonstrating the general purpose of the ripple-based fast-scale instability prediction approach. A design-oriented comprehensive frequency domain model able to concurrently predict both slow scale and fast scale instabilities through the combined application of averaged models and the ripple-based approach closes this part.
Complementarily to the prediction of fast-scale stability boundary, fast-scale instability controllers or chaos controllers are studied, first revisiting the operating principle of already existing delay-based controllers, afterwards proposing and analyzing simpler implementation-friendly chaos controllers. Under the integrated power management perspective, the thesis extends them taking into account other power processor metrics such as output ripple or transient response, thereby proposing a novel controller that, apart from improving fast-scale stability boundary, allows reducing reactive components size and the output voltage ripple.
Finally, the thesis tackles the fast-scale instabilities in more advanced topologies and functionalities, which are representative of advanced power management circuits. First, for a multilevel converter, demonstrating that its inherent lower ripple behaviour makes it less prone to exhibit fast-scale instabilities and hence a better candidate to integration, and second for a wideband switching power amplifier, exploring its nonlinear dynamic phenomena and demonstrating that in the case of a single-tone modulation with a frequency close to the filter and switching frequencies, the fast scale stability boundary condition for regulation application is a sufficient condition to guarantee stability over the entire reference period for tracking applications.Les tendències actuals i previsiblement futures en aplicacions portàtils alimentades per bateries requereixen de major miniaturització i finalment de la integració en un sol chip del circuit de processament de potència juntament amb els circuits de control i gestió optima de la energia, considerats com components clau en els subsistemes de potència, els quals tenen un important impacte global en la mida i la eficiència energètica de tot el sistema. El subsistemes de gestió de potència, tant en regulació com en funcionalitats més sofisticades com és el seguiment de senyals de gran ample de banda amb alt rendiment, són idealment basats en convertidors commutats de potència, paradigma de circuits processadors d’energia d’alt rendiment. Aquests subsistemes, degut a la seva natura no lineal, poden exhibir diverses inestabilitats, les quals es poden classificar segons l’escala temporal en escala ràpida o escala lenta. La predicció de les inestabilitats d’escala lenta es duu a terme habitualment mitjançant els models promitjats convencionals, els quals es deriven d’un anàlisi simple del circuit i tenen com a clar objectiu la simplificació del disseny del sistema, però degut a la seva natura promitjada, no permeten predir les inestabilitats d’escala ràpida. Alternativament, la predicció de la frontera complerta d’estabilitat, incloent ambdós tipus d’inestabilitats, s’ha abordat en el passat des d’un punt de vista analític mitjançant els models en temps discret, basats en una desenvolupament matemàtic més complex i acurat, però que resulta en un anàlisis que s’allunya de la perspectiva orientada al disseny del sistema. En aquest tesis, l’efecte dels diferents paràmetres de l’espai de disseny del sistema sobre la frontera d'estabilitat ha estat explorat, demostrant que les tendències cap a la integració, es a dir, la reducció dels components reactius o la reducció de la freqüència de commutació, condueix a una propensió a exhibir inestabilitats dinàmiques d’escala ràpida. Pel que fa a la caracterització d’aquestes inestabilitats, s’ha dut a terme explorant completament l’espai de disseny així com proposant una caracterització en termes de mètriques de circuit processador d’energia elèctrica del diferents modes dinàmics, incloent així el seu impacte en termes d'arrisat de tensió, espectre, i freqüència promig de commutació. Amb l’objectiu de derivar un model orientat al disseny per predir les inestabilitats d’escala ràpida, la tesi proposa un índex basat en la mesura de l’arrisat a la entrada del modulador PWM per predir de forma quantitativa aquestes inestabilitats en mode de control de tensió. Aquest índex ha estat validat mitjançant simulacions numèriques i experimentalment. Addicionalment, la tesi demostra la relació existent entre l’arrisat en el modulador i els mapes en temps discret. La proposta s’ha estès per al mode de conducció discontinua i també pel mode de control per corrent, demostrant així l’aplicabilitat general de la proposta. Finalment, s’ha proposat i estudiat un model complet en el domini de la freqüència, capaç de predir concurrentment els dos tipus de inestabilitats mitjançant l’aplicació conjunta del model promitjat i el model basat en l’arrisat. De forma complementaria a la predicció de les inestabilitats d’escala ràpida, s’han estudiat diversos controladors orientats a modificar el comportament inestable. Primer tot revisant el principi de funcionament del controladors existents, basat majoritàriament en línies de retard i posteriorment proposant i analitzant controladors que tinguin una implementació mes factible en el domini analògic. Sota la perspectiva de la integració en silici dels sistemes de potència, la tesi ha estès l’anàlisi dels controladors tenint en compte altres mètriques com ara l’arrisat de sortida o la resposta transitòria a un canvi de la carga. Així, s’ha proposat un nou controlador, el qual apart de millorar les inestabilitats d’escala ràpida, permet reduir la mida del components reactius i alhora l’arrisat de sortida del convertidor. Finalment, la tesi aborda la caracterització i predicció de les inestabilitats d’escala ràpida en topologies i funcionalitats mes avançades. Primer, per a un convertidor multinivell, demostrant que el seu inherent baix arrissat el fa menys proper a exhibir inestabilitats i per tant un millor candidat a la integració, i seguidament per a un amplificador commutat de gran ample de banda, explorant la seva dinàmica no lineal, i demostrant que en el cas d’un sol to sinusoïdal, la condició d’estabilitat per regulació estableix una condició suficient per garantir l’estabilitat per aplicacions de seguiment.
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Chatterjee, Subho. "A design methodology for robust, energy-efficient, application-aware memory systems." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50146.
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Memory design is a crucial component of VLSI system design from area, power and performance perspectives. To meet the increasingly challenging system specifications, architecture, circuit and device level innovations are required for existing memory technologies. Emerging memory solutions are widely explored to cater to strict budgets. This thesis presents design methodologies for custom memory design with the objective of power-performance benefits across specific applications. Taking example of STTRAM (spin transfer torque random access memory) as an emerging memory candidate, the design space is explored to find optimal energy design solution. A thorough thermal reliability study is performed to estimate detection reliability challenges and circuit solutions are proposed to ensure reliable operation. Adoption of the application-specific optimal energy solution is shown to yield considerable energy benefits in a read-heavy application called MBC (memory based computing). Circuit level customizations are studied for the volatile SRAM (static random access memory) memory, which will provide improved energy-delay product (EDP) for the same MBC application. Memory design has to be aware of upcoming challenges from not only the application nature but also from the packaging front. Taking 3D die-folding as an example, SRAM performance shift under die-folding is illustrated. Overall the thesis demonstrates how knowledge of the system and packaging can help in achieving power efficient and high performance memory design.
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Fisher, John Sheridan. "Application of model driven architecture design methodologies to mixed-signal system design projects." Columbus, Ohio : Ohio State University, 2006. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1143218375.
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Grobler, Frederik Antonie. "The development of harmonic content and quality of electricity supply measuring system incorporating scada processing." Thesis, Bloemfontein : Central University of Technology, Free State, 2005. http://hdl.handle.net/11462/61.
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Thesis (D.Tech (Engineering Electrical)) - Central University of Technology, Free State, 2005When Thomas Edison invented his carbon filament lamp in 1879, gas shares fell overnight. A committee of inquiry was set up to examine the future possibilities of the new method of lighting, and had reached the conclusion that electric light in the home was fanciful and absurd. Today electric light burns in practically every house in the civilised world, with many great advances in the production and use of electricity and electric power supplied by various utilities. The objective of the electric utility to deliver pure sinusoidal voltage at fairly constant magnitude throughout their system is complicated by the fact that there are currently loads on the system that produce harmonic voltages, which result in distorted voltages and currents that can adversely impact on the system performance in different ways. Because the numbers of harmonic producing loads have increased over the years, it has become necessary to address their influence, when making any additions or changes to an installation. Quality of supply measurements have long been used to characterise non-linearity on the power system, and have traditionally been measured with expensive portable analysers. A potentially faster, more integrated, and more flexible solution to measure the harmonics with a Supervisory System is accomplished by this research. Any script which aspired to cover in full detail the whole field of a subject so enormous as techniques to measure the quality of electricity supply on a SCADA system, would hardly be practical in less than a few volumes. The pretensions of this research are both modest and of a more immediate value to the reader.
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Benhaddou, Mohamed. "Définition d'une méthodologie de conception de circuits intégrés numériques indépendante de la technologie : application à la conception d'un processeur flou." Vandoeuvre-les-Nancy, INPL, 1995. http://www.theses.fr/1995INPL067N.
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Les technologies de fabrication de circuits intégrés numériques et les outils de CAO pour la conception de ceux-ci ont régulièrement évolué. La tendance actuelle est de décrire le comportement du concept à un niveau d'abstraction élevé à l'aide d'un langage de description du matériel standard comme Verilog ou VHDL, et laisser le soin aux outils de synthèse de générer les masques du circuit ou sa liste d'équipotentielles dans la bibliothèque d'un fondeur. Le problème est le prix élevé de ces outils de synthèse de haut niveau qui est dissuasif pour les PME/PMI. L’objectif de ce travail est de montrer que l'on peut démarrer le flot de conception d'un circuit par sa description comportementale de haut niveau et d'obtenir des circuits répondant au cahier des charges en utilisant deux outils de CAO abordables financièrement et répandus dans le commerce: Max+plus II pour le développement des circuits configurables et Solo 1400 pour le développement des circuits précaractérisés. Les outils de synthèse de haut niveau sont ainsi évités à l'aide d'un environnement de conception bâti autour de logiciels de portabilité entre les deux technologies et d'interfaçage entre les HDL de Max+plus II (AHDL) et Solo 1400 (model) et Verilog qui permet la modélisation des circuits intégrés numériques à différents niveaux d'abstraction. Cet environnement de conception est géré par une méthodologie simple, stricte et efficace. Un processeur flou a été conçu afin de valider la méthodologie de conception indépendante de la technologie proposée
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Wan, Wei. "A New Approach to the Decomposition of Incompletely Specified Functions Based on Graph Coloring and Local Transformation and Its Application to FPGA Mapping." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/4698.
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The thesis presents a new approach to the decomposition of incompletely specified functions and its application to FPGA (Field Programmable Gate Array) mapping. Five methods: Variable Partitioning, Graph Coloring, Bond Set Encoding, CLB Reusing and Local Transformation are developed in order to efficiently perform decomposition and FPGA (Lookup-Table based FPGA) mapping. 1) Variable Partitioning is a high quality hemistic method used to find the "best" partitions, avoiding the very time consuming testing of all possible decomposition charts, which is impractical when there are many input variables in the input function. 2) Graph Coloring is another high quality heuristic\ used to perform the quasi-optimum don't care assignment, making the program possible to accept incompletely specified function and perform a quasi-optimum assignment to the unspecified part of the function. 3) Bond Set Encoding algorithm is used to simplify the decomposed blocks during the process of decomposition. 4) CLB Reusing algorithm is used to reduce the number of CLBs used in the final mapped circuit. 5) Local Transformation concept is introduced to transform nondecomposable functions into decomposable ones, thus making it possible to apply decomposition method to FPGA mapping. All the above developed methods are incorporated into a program named TRADE, which performs global optimization over the input functions. While most of the existing methods recursively perform local optimization over some kinds of network-like graphs, and few of them can handle incompletely specified functions. Cube calculus is used in the TRADE program, the operations are global and very fast. A short description of the TRADE program and the evaluation of the results are provided at the_ end of the thesis. For many benchmarks the TRADE program gives better results than any program published in the literature.
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Zahir, Achmed Rumi. "Controller synthesis for application specific integrated circuits /." Zürich, 1991. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=9530.
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Kalab, Peter Carleton University Dissertation Engineering Electrical. "Automated microcontroller synthesis for application-specific integrated circuits." Ottawa, 1986.
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Dupuy, Jean-Yves. "Théorie et Pratique de l'Amplificateur Distribué : Application aux Télécommunications Optiques à 100 Gbit/s." Thesis, Cergy-Pontoise, 2015. http://www.theses.fr/2015CERG0759/document.
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La théorie, la conception, l'optimisation et la caractérisation d'amplificateurs distribués en technologie TBDH InP 0,7 µm, pour les systèmes de communications optiques à 100 Gbit/s, sont présentés. Nous montrons comment l'exploitation adaptée du concept d'amplificateur distribué avec une technologie de transistors bipolaires à produit vitesse-amplitude élevé a permis la réalisation d'un driver de modulateur électro-optique fournissant une amplitude différentielle d'attaque de 6,2 et 5,9 Vpp, à 100 et 112 Gbit/s, respectivement, avec une qualité de signal élevée. Ce circuit établit ainsi le record de produit vitesse-amplitude à 660 Gbit/s.V sur tranche et 575 Gbit/s.V en module hyperfréquence. Dans le cadre du projet Européen POLYSYS, il a été associé à un laser accordable et un modulateur pour la réalisation d'un module transmetteur optoélectronique compact, démontrant des performances avançant l'état de l'art des communications optiques courtes distances à 100 Gbit/sThe theory, design, optimisation and characterisation of distributed amplifiers in 0.7-µm InP DHBT technology, for 100-Gbit/s optical communication systems, are presented. We show how the appropriate implementation of the distributed amplifier concept in a bipolar transistors technology with high swing-speed product has enabled the realisation of an electro-optic modulator driver with 6.2- and 5.9-Vpp differential driving amplitude at 100 and 112 Gb/s, respectively, with a high signal quality. This circuit thus establishes the swing-speed product record at 660 Gb/s.V on wafer and at 575 Gb/s.V in a microwave module. In the frame of the European project POLYSYS, it has been co-packaged with a tunable laser and a modulator to realise a compact optoelectronic transmitter module, which has demonstrated performances advancing the state of the art of short reach 100-Gb/s optical communications
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Cronquist, Darren C. "Reconfigurable pipelined datapaths /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6988.
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Almohanadi, A. H. "Application of analytical placement techniques for floorplanning in VLSI design." Thesis, University of Kent, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.233396.
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Ranganathan, Lavakumar. "Sensor-array chip hybrid for simultaneous multiple analyte detection /." Full text open access at:, 2007. http://content.ohsu.edu/u?/etd,260.
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Petura, Oto. "True random number generators for cryptography : Design, securing and evaluation." Thesis, Lyon, 2019. http://www.theses.fr/2019LYSES053.
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Les nombres aléatoires sont essentiels pour les systèmes cryptographiques modernes. Ils servent de clés cryptographiques, de nonces, de vecteurs d’initialisation et de masques aléatoires pour la protection contre les attaques par canaux cachés. Dans cette thèse, nous traitons des générateurs de nombres aléatoires dans les circuits logiques (FPGA et ASIC). Nous présentons les méthodes fondamentales de génération de nombres aléatoires dans des circuits logiques. Ensuite, nous discutons de différents types de TRNG en utilisant le jitter d’horloge comme source d’aléa. Nous faisons une évaluation rigoureuse de divers noyaux TRNG conformes à la norme AIS-20/31 et mis en œuvre dans trois familles de FPGA différentes: Intel Cyclone V, Xilinx Spartan-6 et Microsemi SmartFusion2. Puis, nous présentons l’implémentation des noyaux TRNG sélectionnés dans des ASIC et leur évaluation. Ensuite, nous étudions en profondeur PLL-TRNG afin de fournir une conception sécurisée de ce TRNG ainsi que des tests intégrés. Enfin, nous étudions les TRNG basés sur les oscillateurs. Nous comparons de différentes méthodes d'extraction d’aléa ainsi que de différents types d'oscillateurs et le comportement du jitter d'horloge à l'intérieur de chacun d'eux. Nous proposons également des méthodes de mesure du jitter intégrée pour le test en ligne des TRNG basés sur les oscillateursRandom numbers are essential for modern cryptographic systems. They are used as cryptographic keys, nonces, initialization vectors and random masks for protection against side channel attacks. In this thesis, we deal with random number generators in logic devices (Field Programmable Gate Arrays – FPGAs and Application Specific Integrated Circuits – ASICs). We present fundamental methods of generation of random numbers in logic devices. Then, we discuss different types of TRNGs using clock jitter as a source of randomness. We provide a rigorous evaluation of various AIS-20/31 compliant TRNG cores implemented in three different FPGA families : Intel Cyclone V, Xilinx Spartan-6 and Microsemi SmartFusion2. We then present the implementation of selected TRNG cores in custom ASIC and we evaluate them. Next, we study PLL-TRNG in depth in order to provide a secure design of this TRNG together with embedded tests. Finally, we study oscillator based TRNGs. We compare different randomness extraction methods as well as different oscillator types and the behavior of the clock jitter inside each of them. We also propose methods of embedded jitter measurement for online testing of oscillator based TRNGs
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Trattles, John T. "Finite element simulation of VLSI interconnections with application to reliability design optimisation and electromigration modelling." Thesis, University of Newcastle Upon Tyne, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.334059.
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Moraes, Fernando Gehm. "Synthese topologique de macro-cellules en technologie cmos." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1994. http://hdl.handle.net/10183/17853.
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Les problèmes majeurs de la génération automatique du dessin des masques des circuits intégrés sont la dépendance vis-à-vis des règles de dessin et le dimensionnement correct des transistors. Les méthodes traditionnelles, telles que l'utilisation de cellules pré-caractérisées, manquent de flexibilité, car les portes des bibliothèques (en nombre limité) sont dessinées et dimensionnées (independarnment de l'application) pour une technologie donnée. Les méthodes de synthèse automatique du dessin des masques ont pour but de surmonter ces problèmes. Les techniques les plus couramment utilisées sont le "gate-matrix" et le "linear-matrix". L'indépendance vis-à-vis des règles de dessin est obtenue en utilisant la technique de description symbolique (dessin sous une grille unitaire), et les dimensions des transistors sont définies par le concepteur ou par un outil de dimensionnement. Nous proposons une méthode et un prototype logiciel pour la synthèse automatique des masques, en utilisant le style "linear-matrix multi-bander". La description d'entree du générateur est un fichier format SPICE (au niveau transistor), ce qui permet d'avoir un nombre très élevé de cellules, en particulier les portes complexes (A01), et ainsi avoir une meilleure optimisation lors de la phase d'assignation technologique. Les macro-cellules générées doivent être assemblées afin de réaliser un circuit complet. Deux contraintes supplémentaires sont ainsi imposées au générateur: malléabilité de la forme et position des broches d'entrées/sorties sur la périphérie de la macro-cellule. Les macro-cellules sont assemblées en utilisant un environnement de conception industriel. Les contributions de ce mémoire de doctorat sont d'une part le développement d'un générateur de macro-cellules flexible ayant les caracteristiques d'indépendance aux règles de dessin et d'intégration dans un environnement de macro-cellules, et d'autre part l'étude detailée des paramètres qui déterminent la surface occupée, les performances électriques et la puissance dissipée des macro-cellules générées automatiquement.The main problems of the automatic layout synthesis are the design rules dependence and the transistor sizing. The traditional layout synthesis methods, like standard-cells, are not flexible, since the cells in the libraries are designed and sized for a specific technology. In this way, the designer must change his library at each technology improvement. The automatic layout synthesis methods overcomes these problems (design rules dependence and transistor sizing). Examples of layout styles are gate-matrix and linear-matrix. The technology independence is achieved by symbolic description (layout under an unitary grid), and the transistor sizes are defined by the designer or by a sizing tool. From these two constraints, we develop an automatic layout synthesis tool, using a linear-matrix multi-row layout style. The input description for our tool is a Spice file. This descriptions allows to define a greater number of cells (mainly AOIs gates), resulting a technology mapping with less constraints. The generated macro-cells must be assembled in order to construct a complete circuit. Two additional constraints are then imposed to the generator : variable aspect ratio and placement of the inputs/outputs pins in the macro-cell border. The macro-cells are assembled by an industrial CAD environment. The main contributions of this thesis are the development of a macro-cell generator (with the characteristics of technology independence and easy integration in a macro-cell environment) and the analysis of the parameters playing a role in the area, delay and power consumption.
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Yu, Haiming. "Analog ASICs for a Depth of Interaction (DOI) Positron Emission Tomography (PET) dectector module /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6066.
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Hoffman, Joseph A. "VHDL modeling of ASIC power dissipation." Master's thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-10222009-124831/.
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Peixoto, Helvio Pereira. "Reuse and estimation techniques for embedded systems-on-a-chip /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Bugnet, Henri. "Conception et test d'un circuit intégré (ASIC) : application aux chambres multifils et aux photomultiplicateurs de l'expérience GRAAL." Université Joseph Fourier (Grenoble), 1995. http://www.theses.fr/1995GRE10192.
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Le projet de physique nucleaire graal installe a grenoble aupres du synchrotron europeen (esrf), fournit un faisceau de photons etiquetes de haute energie (jusqu'a 1,5 gev). Ce faisceau, produit par retrodiffusion compton, est facilement polarisable et il permet de sonder d'une maniere originale la structure du nucleon. L'ensemble de detection associe comprend entre autres, des chambres a fils proportionnelles et des hodoscopes de scintillateurs. Un ensemble de six asic (application specific integrated circuit) a ete developpe, il assure le traitement des signaux des detecteurs et le conditionnement des donnees jusqu'au systeme d'acquisition. Cette electronique integree permet l'implantation des circuits directement sur les detecteurs. Les avantages evidents qui en decoulent sont une meilleure qualite des signaux et une fiabilite accrue, toutes deux dues a la reduction de la longueur et du nombre des connexions. Le wire processor (wp), asic concu et teste durant cette these, permet le traitement des signaux issus des fils de chambres ou des photomultiplicateurs. Le circuit comprend deux voies identiques qui permettent: l'amplification, la discrimination d'amplitude, la generation d'un retard programmable et l'ecriture dans une memoire deux etats, si la mise en coincidence avec un signal exterieur de validation a eue lieu. La mesure de l'efficacite d'une chambre a fils a permis de montrer le bon fonctionnement du wp, de l'electronique de conditionnement des donnees, du systeme d'acquisition et de la chambre elle meme
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Diaz, Nava Mario. "Proposition d'une méthodologie de conception de circuits intégrés de communication : réalisation d'un communicateur pour le réseau local FIP." Phd thesis, Grenoble INPG, 1986. http://tel.archives-ouvertes.fr/tel-00320454.
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FIP=Factory Instrumentation Protocol. On réalise un circuit intégré de communication pour le réseau FIP, projet national de communication entre automates réflexes, capteurs et actionneurs. Le circuit intégré est spécifié pour permettre soit la connexion de capteurs simples, soit la connexion de capteurs intelligents ou des automates de réseau. La conception de ce circuit intégré «à la demande» résulte d'une méthodologie originale. Cette méthodologie est orientée vers la conception de circuits VLSI de communication à partir d'une bibliothèque d'opérateurs flexibles, d'une part pour réduire le temps de conception, d'autre part pour donner la possibilité aux ingénieurs non spécialistes en conception de concevoir eux-mêmes leur circuit
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Lin, Cheng-Hsien Kenny. "An ASIC application for DNA sequencing by Smith-Waterman algorithm (DNASSWA) /." [St. Lucia, Qld.], 2004. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe18716.pdf.
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Rüdiger, Jörg. "Feasability of a laterally emitting thin film electroluminescence device as an application specific integrated display." Thesis, Nottingham Trent University, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.341266.
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