Journal articles: 'Application-specific integrated circuits – Design'

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Tonge, J. D. "The Design Process for Application Specific Integrated Circuits (ASICS)." Microelectronics International 6, no. 1 (January 1989): 5–7. http://dx.doi.org/10.1108/eb044349.

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Renner, F. M., K. J. Hoffmann, R. Markert, and M. Glesner. "Design methodology of application specific integrated circuits for mechatronic systems." Microprocessors and Microsystems 24, no. 2 (April 2000): 95–103. http://dx.doi.org/10.1016/s0141-9331(99)00071-x.

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DJAHANSHAHI, HORMOZ, MAJID AHMADI, GRAHAM A. JULLIEN, and WILLIAM C. MILLER. "NEURAL NETWORK INTEGRATED CIRCUITS WITH SINGLE-BLOCK MIXED SIGNAL ARRAYS." Journal of Circuits, Systems and Computers 08, no. 05n06 (October 1998): 589–604. http://dx.doi.org/10.1142/s0218126698000377.

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This paper discusses the design and implementation of a family of mixed-signal neural network integrated circuits for general and application-specific purposes. Regular Arrays of a nonlinearly-loaded multiplier block form the core of multi-layer neural networks. Input-output circuitry and network size, however, vary depending on design applications. Salient features of the present architecture, such as modularity and reduced interconnection problems and areas are highlighted and circuit design and improvements are presented for its universal building block. Other design issues such as supply voltage and power reduction and pin limitations are discussed together with experimental results.

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Bouldin, D., W. Snapp, P. Haug, D. Sunderland, R. Brees, C. Sechen, and W. Dai. "ASIC by Design - Automated design of digital signal processing application-specific integrated circuits." IEEE Circuits and Devices Magazine 20, no. 4 (July 2004): 17–21. http://dx.doi.org/10.1109/mcd.2004.1317946.

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Abbasi. "APPLICATION SPECIFIC INTEGRATED CIRCUITS DESIGN AND IMPLEMENTATION OF RADEMACHER AND WALSH FUNCTIONS." American Journal of Engineering and Applied Sciences 6, no. 4 (April 1, 2013): 360–68. http://dx.doi.org/10.3844/ajeassp.2013.360.368.

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Richelli, Anna. "Low-Voltage Integrated Circuits Design and Application." Electronics 10, no. 1 (January 5, 2021): 89. http://dx.doi.org/10.3390/electronics10010089.

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One of the most challenging tasks for analog and digital designers is to maintain the circuit performances by developing novel circuit structures, robust, reliable, and capable of operating with low supply voltage [...]

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Hurst, S. L. "Application and design with analog integrated circuits." Microelectronics Journal 25, no. 5 (August 1994): 401. http://dx.doi.org/10.1016/0026-2692(94)90087-6.

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Schmidt, Alexander, Holger Kappert, Wolfgang Heiermann, and Rainer Kokozinski. "A Cyclic RSD Analog-Digital-Converter for Application Specific High Temperature Integrated Circuits up to 250°C." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000214–19. http://dx.doi.org/10.4071/hitec-2012-wp13.

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Silicon-on-Insulator (SOI) CMOS is the most commonly used technology for integrated circuits suitable for high temperatures and harsh environmental conditions. Data acquisition circuitry operating at these conditions has to consider the impact of wide temperature range operation. Therefore, the accurate operation of elementary building blocks is essential for proper system performance. To overcome the accuracy limitations set by channel leakage and performance degradation of NMOS and PMOS transistors, advanced circuit design methods are necessary. By introducing advanced leakage compensation, the overall performance of analog circuits at elevated temperatures is significantly improved. In this paper we present a cyclic analog-to-digital converter with a resolution of 12 bit, fabricated in a 1.0 μm SOI CMOS process. It utilizes the redundant signed digit (RSD) principle in a switched capacitor circuit and is thus insensitive to amplifier or comparator offset. In order to reduce the conversion error, leakage current compensated switches have been used. The ADC features two high gain operational amplifiers. Thereby a gain of more than 110 dB over the whole temperature range has been realized. The ADC's performance has been verified up to 250°C with an input voltage range from 0 V to 5 V. Preliminary results report an accuracy of more than 10 bits with a conversion rate of 1.25 kS/s. The supply voltage is 5 V with a maximum power consumption of 3.4 mW for the analog part of the circuit. The ADC is intended as an IP module to be used in customer specific mixed signal integrated circuits.

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Paraskevopoulos, D. E., and C. F. Fey. "Studies in LSI technology economics. III. Design schedules for application-specific integrated circuits." IEEE Journal of Solid-State Circuits 22, no. 2 (April 1987): 223–29. http://dx.doi.org/10.1109/jssc.1987.1052706.

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Ali, Kamal S., and Adel L. Ali. "Application specific integrated circuit design on a PC platform." Computers & Industrial Engineering 31, no. 1-2 (October 1996): 123–26. http://dx.doi.org/10.1016/0360-8352(96)00093-9.

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Zhao, Chun, Ce Zhou Zhao, and Bin Da. "A Novel Technique for Arithmetic Elements Standard Cell Library Establishment Based on Tanner Tools." Advanced Materials Research 569 (September 2012): 273–76. http://dx.doi.org/10.4028/www.scientific.net/amr.569.273.

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The economic and efficient accomplishment of an application-specific integrated circuit design depends heavily upon the choice of the library. Therefore, it is important to build library that full fills the design requirement. Tanner Tools is a set of software for designing integrated circuits. The great advantage of Tanner is that it can provide a complete circuit design tools in desktop computers. The paper aims to create a standard cell library establishment on the 0.5 micro complementary metal–oxide–semiconductor mixed signal process based on the Tanner Tools.

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Ikedo, Tsuneo. "Design and performance evaluation of a pixel cache implemented within application- specific integrated circuits." Visual Computer 12, no. 5 (June 1, 1996): 215–33. http://dx.doi.org/10.1007/s003710050060.

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Ikedo, Tsuneo. "Design and performance evaluation of a pixel cache implemented within application-specific integrated circuits." Visual Computer 12, no. 5 (May 1996): 215–33. http://dx.doi.org/10.1007/bf01782236.

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Burton, D. P. "Book review: Custom-Specific Integrated Circuits Design and Fabrication." IEE Proceedings G (Electronic Circuits and Systems) 132, no. 6 (1985): 287. http://dx.doi.org/10.1049/ip-g-1.1985.0057.

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Gierczak, Miroslaw Gracjan, Jacek Wróblewski, and Andrzej Dziedzic. "The design and fabrication of electromagnetic microgenerator with integrated rectifying circuits." Microelectronics International 34, no. 3 (August 7, 2017): 131–39. http://dx.doi.org/10.1108/mi-02-2017-0010.

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Purpose The paper focuses on design, fabrication and characterization of electromagnetic microgenerators with integrated rectifying circuits to convert AC output signal to DC one. The work includes research on simulation of voltage-rectifying circuits, including charge pump, realization of the experimental printed circuit board (PCB) with selected electronic circuits and the execution of the final structure with integrated rectifying circuit. Measurements were performed on these circuits. Design/methodology/approach Electromagnetic microgenerators include multipole permanent magnets secured on rotor three-phase brushless direct current (BLDC) motor and planar multilayer multiple coils. These were fabricated using low temperature co-fired ceramics (LTCC) technology. In our experiment, six rectifying circuits were simulated and tested with a structure consisting of eight layers of coils and with an outer diameter of 50 mm fabricated earlier. Findings The microgenerator with Graetz bridge generates higher output power than the modified charge pump at the same rotary speed. However, it is less stable for the distance change between the structure and the magnets than the modified charge pump, which has more constant output power in a wider range of load resistance. Originality/value The presented electronic rectifying circuits are novel for LTCC-based electromagnetic microgenerator application. The structure with integrated rectifying circuits allows generation of electrical output power larger than 100 mW at the rotor speed of about 8,000 rpm.

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Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (October 1, 2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

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Ilijin, Sandra, and Predrag Petkovic. "Implementation of control logic in the scoreboard of tennis." Serbian Journal of Electrical Engineering 12, no. 2 (2015): 219–36. http://dx.doi.org/10.2298/sjee1502219i.

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This paper presents one original solution of control logic for scoreboard in tennis match. The main goal is to simplify the process of recording points. Instead of using six buttons the chair umpire (referee) will use only two control buttons or a joystick to assign a point to a player. The proposed system takes care of all other data processing. The system is designed in Application Specific Integrated Circuits (ASIC) and Standard Application Specific Integrated Circuits (SASIC) technology to demonstrate similarities and differences between two design technologies. Finally it is realized on FPGA type EP2C35F672C6 from Cyclone II Altera?s family.

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Tung, Dam Minh, Nguyen Van Toan, and Jeong-Gun Lee. "A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA." Electronics 9, no. 4 (April 10, 2020): 633. http://dx.doi.org/10.3390/electronics9040633.

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Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

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Liou, Jian-Chiun, and Cheng-Fu Yang. "Design and fabrication of micro-LED array with application-specific integrated circuits (ASICs) light emitting display." Microsystem Technologies 24, no. 10 (November 20, 2017): 4089–99. http://dx.doi.org/10.1007/s00542-017-3640-1.

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Rydygier, Przemysław, Władysław Dąbrowski, Tomasz Fiutowski, and Piotr Wiącek. "Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode Arrays." International Journal of Electronics and Telecommunications 56, no. 4 (November 1, 2010): 399–404. http://dx.doi.org/10.2478/v10177-010-0053-9.

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Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode ArraysIn the paper we present the design and test results of an integrated circuit combining a sample&hold circuit and an analogue multiplexer. The circuit has been designed as a building block for a multi-channel Application Specific Integrated Circuit (ASIC) for recording signals from alive neuronal tissue using high-density micro-electrode arrays (MEAs). The design is optimised with respect to critical requirements for such applications, i.e. short sampling time, low power dissipation, good linearity and high dynamic range. Presented design comprises sample&hold circuits with class AB operational amplifier, novel shift register, which allows minimising cross-coupling of the clock signal and control logic. The circuit has been designed in 0.35μm CMOS process and has been successfully implemented in a prototype multi-channel ASIC.

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Pogra, Vivek, Santosh Kumar Vishvakarma, and Balwinder Raj. "Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Application." Sensor Letters 18, no. 1 (January 1, 2020): 31–38. http://dx.doi.org/10.1166/sl.2020.4176.

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This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the Internet. The transfer of data between different networks and internet of things (IoT) platform is controlled by IoT platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to the fact that it is designed for IoT applications. It is described in VHDL at RTL level and simulation is done on the Vivado 2016.2.

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Dinh, Vu Duc Anh. "PAID – A NOVEL FRAMEWORK FOR DESIGN AND SIMULATION OF ASYNCHRONOUS CIRCUITS." Science and Technology Development Journal 14, no. 2 (June 30, 2011): 37–45. http://dx.doi.org/10.32508/stdj.v14i2.1907.

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Contrary to the synchronous circuits, the asynchronous circuits operate with a mechanism of local synchronization (without clock signal). For many years, they showed their relevance with respect to the synchronous circuits thanks to their properties of robustness, low power, low noise and modularity. However, the lack of design methods and associated tools prevents them from being widely spread. This paper deals with a new design methodology for integrated asynchronous circuits and EDA tools. The suggested design method allows on one hand to model circuits in a highlevel language, and on the other hand to generate circuits using only elementary logical gates and Muller gates. This method was prototyped by the development of an EDA design tool for asynchronous circuits. The combination of design methodologies and supporting tools creates a design framework for asynchronous circuits, namely PAiD ("Project of Asynchronous Circuit Design"). This framework allows compilation and synthesis of circuits, described by high-level language ADL ("Asynchronous Description Language"), to generate asynchronous circuits. The result of the synthesizer is a functional netlist of the circuits. This netlist can be then mapped to a specific-technology gate library for asynchronous circuits. During the design process, the circuit can be tested through the simulation process in different levels of abstraction.

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HOLMAN, W. T. "RADIATION-TOLERANT DESIGN FOR HIGH PERFORMANCE MIXED-SIGNAL CIRCUITS." International Journal of High Speed Electronics and Systems 14, no. 02 (June 2004): 353–66. http://dx.doi.org/10.1142/s0129156404002405.

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Modern semiconductor processes can provide significant intrinsic hardness against radiation effects in digital and analog circuits. Current design techniques using commercial processes for radiation-tolerant integrated circuits are summarized, with an emphasis on their application in high performance mixed-signal circuits and systems. Examples of "radiation hardened by design" (RHBD) methodologies are illustrated for reducing the vulnerability of circuits and components to total dose, single-event, and dose-rate effects.

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Zhang, Yi, Junlong Zhou, Li Chen, and Jin Sun. "A Variability-Aware Robust Design Methodology for Integrated Circuits by Geometric Programming." Journal of Circuits, Systems and Computers 28, no. 05 (May 2019): 1950073. http://dx.doi.org/10.1142/s0218126619500737.

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Process variations have continuously posed significant challenges to the performance and yield of integrated circuits (ICs). The performance modeling and robust optimization method considering process variations has become an important research task in today’s IC design. Aiming at solving the problems of strong nonlinearity and high-dimensional problems in circuit design, this paper proposes a general robust optimization method for ICs by geometric programming. This method first employs regularization sparse models to model a specific performance metric as a posynomial function in terms of design parameters, in order to reduce parameter space dimensionality and to accurately capture the nonlinear relationship between performance perturbations and process variations. Based on the posynomial performance models, this method further uses an uncertainty set to represent the uncertainties of process variations, and formulates the problem of robust optimization under process variations as a general geometric programming model that can be efficiently solved. Experimental results demonstrate that, the proposed method not only enhances the accuracy and efficiency of circuit performance modeling, but also improves the performance yield significantly compared with traditional circuit design methods.

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Uchevler, Bahram N., and Kjetil Svarstad. "Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions." International Journal of Reconfigurable Computing 2018 (July 10, 2018): 1–25. http://dx.doi.org/10.1155/2018/3276159.

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With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/software implementation platform.

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Chen, Ching-Han, Ming-Yi Lin, and Xing-Chen Guo. "High-performance fieldbus application-specific integrated circuit design for industrial smart sensor networks." Journal of Supercomputing 74, no. 9 (March 20, 2017): 4451–69. http://dx.doi.org/10.1007/s11227-017-2010-1.

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Yan, Wei, and John Chandy. "Phase Calibrated Ring Oscillator PUF Design and Application." Computers 7, no. 3 (July 26, 2018): 40. http://dx.doi.org/10.3390/computers7030040.

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A Ring Oscillator Physical Unclonable Function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabrication process to produce random outputs that are nevertheless stable across multiple measurements. Though industry has a growing need for PUF implementations on Field Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (ASIC), the bit errors in PUF responses become a bottleneck and limit the usage. In this work, we comprehensively evaluate the RO PUF’s stability on FPGAs, and we propose a phase calibration process to improve the stability of RO PUFs. We also make full use of the instability of PUFs to provide a novel solution for authentication. The results show that the bit errors in our PUFs are reduced to less than 1%.

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Kornegay, Kevin T., and Robert W. Brodersen. "Integrated Test Solutions for a System Design Environment." VLSI Design 1, no. 4 (January 1, 1994): 345–57. http://dx.doi.org/10.1155/1994/39791.

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While the performance, density, and complexity of application-specific systems increase at a rapid pace, equivalent advances are not being made in making them more easily testable, diagnosable, and maintainable. Even though testability bus standards, like JTAG Boundary Scan, have been developed to help eliminate these costs, there exists a need for efficient hardware and software tools to support them. Hence, a testability design and hardware support environment for application-specific systems is described which provides a designer with a set of hardware modules and circuitry, that support these standards and software tools for automatic incorporation of testability hardware, as well as automatic test vector and test program generation.

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Malecha, Karol, Jan Macioszczyk, Piotr Slobodzian, and Jacek Sobkow. "Application of microwave heating in ceramic-based microfluidic module." Microelectronics International 35, no. 3 (July 2, 2018): 126–32. http://dx.doi.org/10.1108/mi-11-2017-0062.

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Purpose This paper aims to focus on the application of low temperature co-fired ceramic (LTCC) technology in the fabrication of a microfluidic module with integrated microwave components. The design, technology and performance of such an LTCC-based module is investigated. The rapid heating of liquid samples on a microliter scale is shown to be possible with the use of microwaves. Design/methodology/approach The developed microwave-microfluidic module was fabricated using well-known LTCC technology. The finite element method was used to design the geometry of the microwave circuit. Various numerical simulations for different liquids were performed. Finally, the performance of the real LTCC-based microwave-microfluidic module was examined experimentally. Findings LTCC materials and technology can be used in the fabrication of microfluidic modules which use microwaves in the heating of the liquid sample. LTCC technology permits the fabrication of matching circuits with appropriate geometry, whereas microwave power can be used to heat up the liquid samples on a microliter scale. Research limitations/implications The main limitation of the presented work is found to be in conjunction with LTCC technology. The dimensions and shape of the deposited conductors (e.g. microstrip line, matching circuit) depend on the screen-printing process. A line with resolution lower than 75 µm with well-defined edges is difficult to obtain. This can have an effect on the high-frequency properties of the LTCC modules. Practical implications The presented LTCC-based microfluidic module with integrated microwave circuits provides an opportunity for the further development of various micro-total analysis systems or lab-on-chips in which the rapid heating of liquid samples in low volumes is needed (e.g. miniature real-time polymerase chain reaction thermocycler). Originality/value Examples of the application of LTCC technology in the fabrication of microwave circuits and microfluidic systems can be found in the available literature. However, the LTCC-based module which combines microwave and microfluidic components has yet to have been reported. The preliminary work on the design, fabrication and properties of the LTCC microfluidic module with integrated microwave components is presented in this paper.

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Kledrowetz, Vilem, Roman Prokop, Lukas Fujcik, Michal Pavlik, and Jiří Háze. "Low-power ASIC suitable for miniaturized wireless EMG systems." Journal of Electrical Engineering 70, no. 5 (September 1, 2019): 393–99. http://dx.doi.org/10.2478/jee-2019-0071.

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Abstract Nowadays, the technology advancements of signal processing, low-voltage low-power circuits and miniaturized circuits have enabled the design of compact, battery-powered, high performance solutions for a wide range of, particularly, biomedical applications. Novel sensors for human biomedical signals are creating new opportunities for low weight wearable devices which allow continuous monitoring together with freedom of movement of the users. This paper presents the design and implementation of a novel miniaturized low-power sensor in integrated circuit (IC) form suitable for wireless electromyogram (EMG) systems. Signal inputs (electrodes) are connected to this application-specific integrated circuit (ASIC). The ASIC consists of several consecutive parts. Signals from electrodes are fed to an instrumentation amplifier (INA) with fixed gain of 50 and filtered by two filters (a low-pass and high-pass filter), which remove useless signals and noise with frequencies below 20 Hz and above 500 Hz. Then signal is amplified by a variable gain amplifier. The INA together with the reconfigurable amplifier provide overall gain of 50, 200, 500 or 1250. The amplified signal is then converted to pulse density modulated (PDM) signal using a 12-bit delta-sigma modulator. The ASIC is fabricated in TSMC0.18 mixed-signal CMOS technology.

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Alexandru, Mihaela, Viorel Banu, Miguel Vellvehi, Philippe Godignon, and José Millán. "Design of Digital Electronics for High Temperature Using Basic Logic Gates Made of 4H-SiC MESFETs." Materials Science Forum 711 (January 2012): 104–8. http://dx.doi.org/10.4028/www.scientific.net/msf.711.104.

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– 4H-SiC MESFET transistors are very attractive devices for high temperature application and communications. The JFET and MESFET transistors have a promising potential for integrated circuits able to operate at high temperature and harsh radiation environments, due to the superior electrical, mechanical and chemical proprieties of 4H-SiC. Progresses in the manufacturing of high quality SiC substrates open the possibility to new circuit applications.

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Pogra, Vivek, Amandeep Singh, Santosh Kumar Vishvakarma, and Balwinder Raj. "Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Applications." Sensor Letters 18, no. 9 (September 1, 2020): 700–705. http://dx.doi.org/10.1166/sl.2020.4239.

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This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the internet. The transfer of data between different networks and electronic systems is controlled by internet of things (IoT) platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to SPI feature along with DMA on ASIC for IoT applications. It is described in very high speed integrated circuit hardware description language (VHDL) at register transfer level (RTL) and simulation is done on the Vivado 2016.2.

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Barajas, Enrique, Xavier Aragones, Diego Mateo, and Josep Altet. "Differential Temperature Sensors: Review of Applications in the Test and Characterization of Circuits, Usage and Design Methodology." Sensors 19, no. 21 (November 5, 2019): 4815. http://dx.doi.org/10.3390/s19214815.

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Differential temperature sensors can be placed in integrated circuits to extract a signature of the power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper first discusses the singularity that differential temperature sensors provide with respect to other sensor topologies, with circuit monitoring being their main application. The paper focuses on the monitoring of radio-frequency analog circuits. The strategies to extract the power signature of the monitored circuit are reviewed, and a list of application examples in the domain of test and characterization is provided. As a practical example, we elaborate the design methodology to conceive, step by step, a differential temperature sensor to monitor the aging degradation in a class-A linear power amplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how, for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamic range is required. A circuit solution for this objective is proposed, as well as recommendations for the dimensions and location of the devices that form the temperature sensor. The paper concludes with a description of a simple procedure to monitor time variability.

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Huang, Chun, Ying-Jie Han, Jun-Wei Sun, Wei-Jun Zhu, Yan-Feng Wang, and Qing-Lei Zhou. "The Design and Application of Exclusive OR Logical Computation Based on DNA 3-Arm Sub-Tile Self-Assembly." Journal of Nanoelectronics and Optoelectronics 15, no. 11 (November 1, 2020): 1327–34. http://dx.doi.org/10.1166/jno.2020.2853.

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DNA algorithmic self-assembly plays a vital role in DNA computing, which is applied to create new DNA tiles and then guides these tiles into an algorithmic lattice. However, the larger the logical calculation scale is, the more tile sets will be needed, so that computing model design and experiment will be increasingly difficult. This paper presents a new DNA ‘3-arm sub-tile strategy’ that constructs XOR and half-adder logical circuits. The types of DNA tile corresponding to the logical values is unified in DNA XOR and half-adder logical circuits, which have only three kinds of DNA tiles: logic ‘0’, logic ‘1’ and fixation tile. Compared with the previous references, the amount of DNA tile types has been greatly reduced. Moreover, the half-adder molecular circuit has a distinctive feature, which is an application of the expansion of the XOR logic circuit. Meanwhile, a set of DNA 3-arm sub-tiles suitable for half-adder logical computation is designed on the NUPACK online server. The simulated experiments show that the correct rate of base pairing of the designed DNA encoding is high and the structures are stable. The DNA 3-arm sub-tile self-assembly methods provide a new way to form DNA logical circuits, and has a great potential in the expansion of the integrated circuits.

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Singh, N. S. S. "Programmed Tool for Quantifying Reliability and Its Application in Designing Circuit Systems." Journal of Electrical and Computer Engineering 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/410758.

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As CMOS technology scales down to nanotechnologies, reliability continues to be a decisive subject in the design entry of nanotechnology-based circuit systems. As a result, several computational methodologies have been proposed to evaluate reliability of those circuit systems. However, the process of computing reliability has become very time consuming and troublesome as the computational complexity grows exponentially with the dimension of circuit systems. Therefore, being able to speed up the task of reliability analysis is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into developing a MATLAB-based automated reliability tool by incorporating the generalized form of the existing computational approaches that can be found in the current literature. Secondly, a comparative study involving those existing computational approaches is carried out on a set of standard benchmark test circuits. Finally, the paper continues to find the exact error bound for individual faulty gates as it plays a significant role in the reliability of circuit systems.

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Jendernalik, W., G. Blakiewicz, A. Handkiewicz, and M. Melosik. "Analogue CMOS ASICs in Image Processing Systems." Metrology and Measurement Systems 20, no. 4 (December 1, 2013): 613–22. http://dx.doi.org/10.2478/mms-2013-0052.

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Abstract In this paper a survey of analog application specific integrated circuits (ASICs) for low-level image processing, called vision chips, is presented. Due to the specific requirements, the vision chips are designed using different architectures best suited to their functions. The main types of the vision chip architectures and their properties are presented and characterized on selected examples of prototype integrated circuits (ICs) fabricated in complementary metal oxide semiconductor (CMOS) technologies. While discussing the vision chip realizations the importance of low-cost, low-power solutions is highlighted, which are increasingly being used in intelligent consumer equipment. Thanks to the great development of the automated design environments and fabrication methods, new, so far unknown applications of the vision chips become possible, as for example disposable endoscopy capsules for photographing the human gastrointestinal tract for the purposes of medical diagnosis.

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Levi, T., N. Lewis, J. Tomas, and S. Renaud. "Application of IP-Based Analog Platforms in the Design of Neuromimetic Integrated Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 11 (November 2012): 1629–41. http://dx.doi.org/10.1109/tcad.2012.2204992.

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Galajda, Pavol, Martin Pecovsky, Miroslav Sokol, Martin Kmec, and Dusan Kocur. "Recent Advances in ASIC Development for Enhanced Performance M-Sequence UWB Systems." Sensors 20, no. 17 (August 26, 2020): 4812. http://dx.doi.org/10.3390/s20174812.

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Short-range ultra-wideband (UWB) radar sensors belong to very promising sensing techniques that have received vast attention recently. The M-sequence UWB sensing techniques for radio detection and ranging feature several advantages over the other short-range radars, inter alia superior integration capabilities. The prerequisite to investigate their capabilities in real scenarios is the existence of physically available hardware, i.e., particular functional system blocks. In this paper, we present three novel blocks of M-sequence UWB radars exploiting application-specific integrated circuit (ASIC) technology. These are the integrated 15th-order M-sequence radar transceiver on one chip, experimental active Electronic Communication Committee (ECC) bandpass filter, and miniature transmitting UWB antenna with an integrated amplifier. All these are custom designs intended for the enhancement of capabilities of an M-sequence-based system family for new UWB short-range sensing applications. The design approaches and verification of the manufactured prototypes by measurements of the realized circuits are presented in this paper. The fine balance on technology capabilities (Fc of roughly 120 GHz) and thoughtful design process of the proposed blocks is the first step toward remarkably minimized devices, e.g., as System on Chip designs, which apparently allow broadening the range of new applications.

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Tosun, Suleyman, and Tohid Taghizad Gogjeh Yaran. "Genetic Algorithm-based Reliability Optimization for High-Level Synthesis." Journal of Circuits, Systems and Computers 28, no. 03 (February 24, 2019): 1950039. http://dx.doi.org/10.1142/s0218126619500397.

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Soft errors (SEs) are a type of transient errors in integrated circuits (ICs) caused by radiation effects in the chips. They have become the major concern in IC design process in each CMOS technology generation since the decrease in supply voltage levels for shrinking transistor sizes makes the circuits more vulnerable than before. Previous studies generally use hardware redundancy for combinational circuits and error correcting codes for memory elements to mitigate or eliminate the SEs. However, adding extra hardware in final design may not always be possible if the design has tight area constraints. Different implementations of the same function may have different soft error rates (SERs) due to their error masking capabilities. Therefore, we can obtain various versions of the same function with different area, latency, and reliability values. Allocating the best resources to the operations of the design under area and latency constraints to optimize the overall system reliability has NP-complete time complexity. Evolutionary computing-based methods suit very well for this optimization problem. Motivated by this fact, in this paper, we present a genetic algorithm (GA)-based design method to increase the reliability of application-specific integrated circuits (ASICs). In this method, we use different versions of the same resources, each having a different area, latency, and reliability values. The goal of the GA-based optimizer is to allocate the best available resources to the application nodes to maximize the reliability of the design under tight area and latency constraints. Our experimental results show that we achieve up to 20.86% reliability improvement against a heuristic method with no additional area overhead. In order to further increase the reliability of the final design, we also propose a heuristic-based post-processing method, which adds duplicate resources to the final design without violating the constraint.

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Breslin, Catherine, and Adrian O'Lenskie. "Neuromorphic hardware databases for exploring structure–function relationships in the brain." Philosophical Transactions of the Royal Society of London. Series B: Biological Sciences 356, no. 1412 (August 29, 2001): 1249–58. http://dx.doi.org/10.1098/rstb.2001.0904.

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Neuromorphic hardware is the term used to describe full custom–designed integrated circuits, or silicon ‘chips’, that are the product of neuromorphic engineering—a methodology for the synthesis of biologically inspired elements and systems, such as individual neurons, retinae, cochleas, oculomotor systems and central pattern generators. We focus on the implementation of neurons and networks of neurons, designed to illuminate structure–function relationships. Neuromorphic hardware can be constructed with either digital or analogue circuitry or with mixed–signal circuitry—a hybrid of the two. Currently, most examples of this type of hardware are constructed using analogue circuits, in complementary metal–oxide–semiconductor technology. The correspondence between these circuits and neurons, or networks of neurons, can exist at a number of levels. At the lowest level, this correspondence is between membrane ion channels and field–effect transistors. At higher levels, the correspondence is between whole conductances and firing behaviour, and filters and amplifiers, devices found in conventional integrated circuit design. Similarly, neuromorphic engineers can choose to design Hodgkin–Huxley model neurons, or reduced models, such as integrate–and–fire neurons. In addition to the choice of level, there is also choice within the design technique itself; for example, resistive and capacitive properties of the neuronal membrane can be constructed with extrinsic devices, or using the intrinsic properties of the materials from which the transistors themselves are composed. So, silicon neurons can be built, with dendritic, somatic and axonal structures, and endowed with ionic, synaptic and morphological properties. Examples of the structure–function relationships already explored using neuromorphic hardware include correlation detection and direction selectivity. Establishing a database for this hardware is valuable for two reasons: first, independently of neuroscientific motivations, the field of neuromorphic engineering would benefit greatly from a resource in which circuit designs could be stored in a form appropriate for reuse and re–fabrication. Analogue designers would benefit particularly from such a database, as there are no equivalents to the algorithmic design methods available to designers of digital circuits. Second, and more importantly for the purpose of this theme issue, is the possibility of a database of silicon neuron designs replicating specific neuronal types and morphologies. In the future, it may be possible to use an automated process to translate morphometric data directly into circuit design compatible formats. The question that needs to be addressed is: what could a neuromorphic hardware database contribute to the wider neuroscientific community that a conventional database could not? One answer is that neuromorphic hardware is expected to provide analogue sensory–motor systems for interfacing the computational power of symbolic, digital systems with the external, analogue environment. It is also expected to contribute to ongoing work in neural–silicon interfaces and prosthetics. Finally, there is a possibility that the use of evolving circuits, using reconfigurable hardware and genetic algorithms, will create an explosion in the number of designs available to the neuroscience community. All this creates the need for a database to be established, and it would be advantageous to set about this while the field is relatively young. This paper outlines a framework for the construction of a neuromorphic hardware database, for use in the biological exploration of structure–function relationships.

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Pevtsov, E. Ph, T. A. Demenkova, and A. A. Shnyakin. "Design for Testability of Integrated Circuits and Project Protection Difficulties." Russian Technological Journal 7, no. 4 (August 11, 2019): 60–70. http://dx.doi.org/10.32362/2500-316x-2019-7-4-60-70.

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Design solutions of domestic VLSI were obtained as a result of the application of computeraided design tools of a foreign supplier (CAD Synopsys, Cadence Design Systems and Mentor Graphics), based on standard libraries of PDK elements (Project Design KIT) of factories and IC-modules also supplied mainly by foreign companies. As a rule, the developer does not have its own production facilities, using the services provided by foreign factories (fablesscompanies). Due to this fact, relevant are the studies aimed at the development of a complex of measures, excluding the possibility of unauthorized changes into IC, i.e. protection of projects against intentional hardware and technology violations made during the formation of the control information for handing it over to the production facility and/or in case of IC manufacture at the factory. This paper considers this task from the standpoint of the analysis of the methodology of design for testability (DFT), i.e., a complex of measures that provide obtaining solutions at the design stage. The solutions include the verification of the correct performance of the manufactured chip by means of external tests and/or self-testing procedures. It was proposed, inter alia: 1) to analyze the libraries of standard elements used in the project with full disclosure of their specifications; 2) to create nodes with the physical non-cloning function in the projects on the basis of the libraries of standard elements in models and analysis programs; 3) to analyze IP modules used in the project with the maximum disclosure of structure, methods and algorithms for providing test coverings; 4) to provide for the development in projects of special test kits and methods of their generation at the design stage of functions in order to detect malicious nodes and programs both within SoC cores and at the level of system buses; 5) to develop at the design stage and to apply during tests a technique of special hardware measurements of parameters of the manufactured circuits and analysis of their results, inter alia, according to measurements of delays in distribution of signals and/or buses current consumption.

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Myderrizi, Indrit, and Ali Zeki. "A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology." Journal of Circuits, Systems and Computers 26, no. 11 (April 17, 2017): 1750182. http://dx.doi.org/10.1142/s0218126617501821.

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With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with fully controllable output voltage swing that is useful to reduce the power dissipation and delay in the signaling paths. Implemented in UMC 0.13-[Formula: see text][Formula: see text]m multi-threshold CMOS process, the SRD achieves 26 ps propagation delay at 200[Formula: see text]mV output swing for a pulse signal input at 1[Formula: see text]GHz. Post-layout simulations of the proposed SRD and a DAC application circuit, incorporating the SRD, operating at 1[Formula: see text]GHz, validate the design.

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Kong, Qing Chen, Guang Can Zhang, and Yong Xin Li. "Research on the Development of Large Application Specific Integrated Circuit Based on SOPC." Advanced Materials Research 328-330 (September 2011): 1663–66. http://dx.doi.org/10.4028/www.scientific.net/amr.328-330.1663.

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This paper introduces a design of ASIC with the advantages of high performance, low power, low cost and short development cycle, which is especially suitable for the middle and small scale production of complicated large programmable ASIC. Through introducing the performance and latest development of HardCopy series devices and Stratix FPGA series devices, and based on the development platform of Quartus II and Nios II system, this paper analyzes the complete development process of Stratix FPGA and HardCopy ASIC based on SOPC. This paper concludes the seamless transplant from Stratix FPGA to HardCopy ASIC based on the SOPC with IP multiplexing, which is the most promising development direction of producing large programmable ASIC with high performance and low cost in the future.

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BODDHU, SANJAY K., JOHN C. GALLAGHER, and SARANYAN A. VIGRAHAM. "A COMMERCIAL OFF-THE-SHELF IMPLEMENTATION OF AN ANALOG NEURAL COMPUTER." International Journal on Artificial Intelligence Tools 17, no. 02 (April 2008): 241–58. http://dx.doi.org/10.1142/s021821300800387x.

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For most applications, analog electrical circuit implementations of continuous-valued neural networks have been abandoned in favor of digital simulations. This is not surprising, as both precision and accuracy can be more easily ensured in digital computers. Still, because they use far fewer transistors and support components, analog circuits can still be orders of magnitude smaller than their digital simulations. In some application, like micro-robotics and embedded control, one might be willing to tolerate less accuracy and precision for the size and power benefits. One would not under any condition, however, tolerate significant behavioral mismatches between the differential equation and electrical circuit forms of the neural networks in question. In this paper, we will present a design for an analog neural computer that embodies the commonly used continuous time recurrent neural network. We will show that the computer possesses excellent behavioral congruence to the differential equation form even in the presence of significant practical compromises. We will also discuss the implications of this work for both practical Commercial, Off-The-Shelf (COTS) and Application-Specific Integrated Circuit (ASIC) devices.

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Bintang, Sanusi. "Desain Tata Letak Sirkuit Terpadu sebagai Hak Kekayaan Intelektual dalam Hukum Indonesia." Kanun Jurnal Ilmu Hukum 20, no. 1 (April 18, 2018): 23–38. http://dx.doi.org/10.24815/kanun.v20i1.9897.

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Desain tata letak sirkuit terpadu sebagai cetak biru untuk sirkuit terpadu, digunakan dalam berbagai produk teknologi informasi, seperti komputer, telepon selular, dan peralatan komunikasi, memiliki ciri khas tersendiri yang tidak sesuai untuk ditempatkan dalam rezim hukum hak kekayaan intelektual yang ada, karena itu, perlu diatur dalam peraturan perundang-undangan khusus (sui generis). Penelitian ini menggunakan metode penelitian hukum normatif dengan mengaplikasikan pendekatan peraturan perundang-undangan dan pendekatan perbandingan. Indonesia telah mengundangkan hukum tentang Desain Tata Letak Sirkuit Terpadu, tetapi undang-undang ini memiliki beberapa kelemahan. Kelemahan yang ada berkaitan dengan kelengkapan dan kualitas norma serta penegakan hukumnya. Kelemahan tersebut tidak hanya dari aspek teknik perancangan peraturan perundang-undangan, tetapi juga berakar pada budaya hukum. Design of Integrated Circuits as Intellectual Property Rights in Indonesian Laws Design of integrated circuits as blue prints for integrated circuit used in various products of information technology, such as computer, cellular phone, and telecomunication media, has its own characteristics which is not fit to be put under the previous intellectual property law regimes, therefore, it needs to be regulate under a specific legislation (sui generis). This research utilizes doctrinal legal research method by applying statute approach and comparative approach. Indonesia has enacted laws on Design of Integrated Circuits, but the law has certain limitations. The limitations is regarding the adequacy of subject matter, the quality of norms, and the legal enforcement. The limitations is not only from the aspect of technical legal drafting, but also rooted on legal culture.

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Fu, Xiu Hui, and Jun Mu. "Design of Mobile Jumping Robot Based on DSP2407." Advanced Materials Research 328-330 (September 2011): 1216–19. http://dx.doi.org/10.4028/www.scientific.net/amr.328-330.1216.

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The paper designs a kind of mobile jumping robot that can choose different movement strategies according to different surroundings. In order to achieve the purpose, we provide the integrated design of the robot which contains the information collection system and the mobile system. Then we describe the hardware structures and the control process in detail. First, we create the mechanical structure and analyze the kinematics model of it. Second, we give the specific design of the mobile actuating mechanisms. At last, we design the hardware circuits and control system of the robot based on TMS320LF2407A chip and put the robot into the experiments. Through the experiments, robot combines the wheeled movement and jumping movement effectively. The ultrasonic sensor is added to robot, and it makes the one smarter than any other traditional robots. The diversity of movement enhances the robot environmental adaptability and expands the range of application.

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ELIAHOU-NIV, S. "A MECHANICAL DARLINGTON MODEL FOR MEMS APPLICATIONS." Journal of Circuits, Systems and Computers 15, no. 03 (June 2006): 313–19. http://dx.doi.org/10.1142/s0218126606002988.

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This paper presents the design and Micro-Electro-Mechanical-System (MEMS) realization of a Darlington-pair circuit used in power electronics engineering. MEMS are integrated micro devices or systems combining electrical and mechanical components fabricated using integrated circuits processing techniques. The size range of the components is from micrometers up to a couple of millimeters. Current MEMS applications include almost all engineering fields. Since MEMS is a newly developed technology, very few studies have been carried out directly on knowledge transferring from different engineering disciplines. The objective of this paper is to demonstrate a mechanical model developing of a power electronic circuit, to characterize and to analyze its performance and its suitability to MEMS application.

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Smith, M. J. S., C. Portmann, C. Anagnostopoulos, P. S. Tschang, R. Rao, P. Valdenaire, and H. Ching. "Cell libraries and assembly tools for analog/digital CMOS and BiCMOS application-specific integrated circuit design." IEEE Journal of Solid-State Circuits 24, no. 5 (October 1989): 1419–32. http://dx.doi.org/10.1109/jssc.1989.572628.

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Weikle, R. M., T. W. Crowe, and E. L. Kollberg. "Multiplier and Harmonic Generator Technologies for Terahertz Applications." International Journal of High Speed Electronics and Systems 13, no. 02 (June 2003): 429–56. http://dx.doi.org/10.1142/s012915640300179x.

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Harmonic generation based on frequency multipliers has proven to be the most successful and widely used solid-state technology for generating power at submillimeter wavelengths. Over the last several years, the development of new device technologies, implementation of innovative circuits, and application of advanced integrated-circuit processing techniques to frequency multiplier design have resulted in unprecedented levels of performance throughout the submillimeter-wave frequency band. This paper reviews the technological innovations, device options, circuit architectures, and fabrication technologies that have made harmonic generation such a successful approach to source development in the submillimeter spectrum.

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Stornelli, Vincenzo, Leonardo Pantoli, Gianluca Barile, Alfiero Leoni, and Emanuele D’Amico. "Silicon Photomultiplier Sensor Interface Based on a Discrete Second Generation Voltage Conveyor." Sensors 20, no. 7 (April 5, 2020): 2042. http://dx.doi.org/10.3390/s20072042.

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This work presents the design of a discrete second-generation voltage conveyor (VCII) and its capability to be used as electronic interface for silicon photomultipliers. The design addressed here exploits directly at the transistor level, with commercial components, the proposed interface; the obtained performance is valuable considering both the discrete elements and the application. The architecture adopted here realizes a transimpedance amplifier that is also able to drive very high input impedance, as usually requested by photons detection. Schematic and circuital design of the discrete second-generation voltage conveyor is presented and discussed. The complete circuit interface requires a bias current of 20 mA with a dual 5V supply voltage; it has a useful bandwidth of about 106 MHz, and considering also the reduced dimensions, it is a good candidate to be used in portable applications without the need of high-cost dedicated integrated circuits.

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Journal articles on the topic 'Application-specific integrated circuits – Design'

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