Relevant bibliographies by topics / Approximate computing multiplier

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Academic literature on the topic 'Approximate computing multiplier'

Author: Grafiati
Published: 4 June 2025
Last updated: 15 July 2025

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Journal articles on the topic "Approximate computing multiplier"

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O, Vignesh, Mangalam H, and AnjuBala K. "Survey on Approximate Multipliers for Image Processing." European Journal of Advances in Engineering and Technology 5, no. 5 (2018): 344–49. https://doi.org/10.5281/zenodo.10708304.

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<strong>ABSTRACT </strong> Approximate computing has become ravishing approach for designing high performance and low energy consumption with limited loss in accuracy for many digital logic designs. Since there is a trade-off between speed/power with accuracy shown through previous research works. The demand of high speed and power efficiency as well as the feature of error tolerant applications has driven the development of approximate arithmetic circuits. The most important arithmetic modules in a processor are adder and multipliers to determine the performance for many computing tasks in today&rsquo;s digital systems. A comparative study of efficient algorithm and architecture for various approximate multipliers are presented in this survey. Approximate multiplier reduces the transistor count, power consumption, delay and it provides high speed output. The result shows that the proposed Approximate multiplier design accomplish significant reductions in power dissipation, delay and transistor count compared to an exact accurate multiplier design with small loss in accuracy. Comparison of extensive simulation results are shown for approximate multiplier. An application in image processing is performed, where peak signal to noise ratio of the image is analyzed. The image quality of the approximate multiplier shows satisfactory result compared to an accurate multiplier.
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Vinodia, Ayushi. "Energy-Efficient Approximate Multiplier with Flexible Precision." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 741–51. http://dx.doi.org/10.22214/ijraset.2024.61704.

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Abstract: The method that can be utilized to increase accuracy and decrease energy use is approximate multiplication. A key component of many error-tolerant applications is multiplication. Approximate multipliers are increasingly utilized in energyefficient computing for applications tolerant of inaccuracy. Apart from multiplier performance, determining the appropriate approximate multiplier is challenging due to considerations of area and delay. Therefore, selecting the type of approximate full adder (FA) becomes a crucial decision-making factor. These adders are employed for summing partial products in multipliers. This study presents the design and evaluation of an approximate multiplier employing four distinct approximate adders. The design undergoes simulation and synthesis using Xilinx and Model Sim. Compared to previously proposed approximate multipliers, the proposed circuits demonstrate substantial reductions in area, time delay, and power consumption. According to experimental data, the area, latency, and average power consumption of the suggested adjustable approximate multiplier can be lowered by 10%, 34.96 ns, and 300 mW when contrasted to the Wallace tree multiplier.
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Arham Dodal. "Efficient Approximate Multiplier for Image Processing Application." Journal of Information Systems Engineering and Management 10, no. 25s (2025): 712–22. https://doi.org/10.52783/jisem.v10i25s.4117.

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The field of approximate computing has garnered significant interest as a promising area for relatively error-resistant applications. At its core, approximate computing revolves around a trade-off between efficiency and accuracy. To optimize power consumption, delay, and area, a certain level of accuracy is sacrificed, provided it remains within acceptable limits. This research introduces a novel design for an approximate 4:2 compressor. Two distinct configurations for implementing this compressor are proposed and evaluated within the framework of an 8x8 Dadda multiplier. The study assesses both technology-dependent and technology-independent parameters, comparing them with the most recent approximate multipliers reported in recent literature. The performance of these multipliers is tested using a 45-nm standard CMOS technology node. Additionally, the quality and precision of the proposed approximate multiplier are evaluated using a range of statistical metrics. To demonstrate their practical utility, the proposed multipliers are applied to image processing tasks. The results indicate that the proposed designs outperform existing approximate multipliers in terms of efficiency for image processing applications.
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Lu, Mi. "Runtime accuracy alterable approximate floatingpoint multipliers." International Robotics & Automation Journal 8, no. 2 (2022): 52–56. http://dx.doi.org/10.15406/iratj.2022.08.00244.

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Modern systems demand high computational power within limited resources. Approximate computing is a promising approach to design arithmetic units with tight resources for error-tolerant applications such as image and signal processing and computer vision. A floating-point multiplier is one of the arithmetic units with the highest complexity in such applications. Designing a floating-point multiplier based on the approximate computing technique can reduce its complexity as well as increase performance and energy efficiency. However, an unknown error rate for upcoming input data is problematic to design appropriate approximate multipliers. The existing solution is to utilize an error estimator relying on statistical analysis. In this paper, we propose new approximate floating-point multipliers based on an accumulator and reconfigurable adders with an error estimator. Unlike previous designs, our proposed designs are able to change the levels of accuracy at runtime. Thus, we can make errors distributed more evenly. In contrast to other designs, our proposed design can maximize the performance gain since reconfigurable multipliers are able to operate two multiplications in parallel once the low accuracy mode is selected. Furthermore, we apply a simple rounding technique to approximate floating-point multipliers for additional improvement. Our simulation results reveal that our new method can reduce area by 70.98% when error tolerance margin of our target application is 5%, and when its error tolerance margin is 3%, our rounding enhanced simple adders-based approximate multiplier can save area by 65.9%, and our reconfigurable adder-based approximate multiplier with rounding can save the average delay and energy by 54.95% and 46.67% respectively compared to an exact multiplier.
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Osta, Mario, Ali Ibrahim, and Maurizio Valle. "Approximate Computing Circuits for Embedded Tactile Data Processing." Electronics 11, no. 2 (2022): 190. http://dx.doi.org/10.3390/electronics11020190.

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In this paper, we demonstrate the feasibility and efficiency of approximate computing techniques (ACTs) in the embedded Support Vector Machine (SVM) tensorial kernel circuit implementation in tactile sensing systems. Improving the performance of the embedded SVM in terms of power, area, and delay can be achieved by implementing approximate multipliers in the SVD. Singular Value Decomposition (SVD) is the main computational bottleneck of the tensorial kernel approach; since digital multipliers are extensively used in SVD implementation, we aim to optimize the implementation of the multiplier circuit. We present the implementation of the approximate SVD circuit based on the Approximate Baugh-Wooley (Approx-BW) multiplier. The approximate SVD achieves an energy consumption reduction of up to 16% at the cost of a Mean Relative Error decrease (MRE) of less than 5%. We assess the impact of the approximate SVD on the accuracy of the classification; showing that approximate SVD increases the Error rate (Err) within a range of one to eight percent. Besides, we propose a hybrid evaluation test approach that consists of implementing three different approximate SVD circuits having different numbers of approximated Least Significant Bits (LSBs). The results show that energy consumption is reduced by more than five percent with the same accuracy loss.
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Zanandrea, Vinicius, Fabiane Benitti, and Cristina Meinhardt. "Energy-efficient Multiplier Design Through Approximate Computing: Current Trends and Future Prospects." Journal of Integrated Circuits and Systems 19, no. 3 (2024): 1–15. https://doi.org/10.29292/jics.v19i3.927.

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Approximate Computing can be effectively applied in error-tolerant applications in order to improve the energy efficiency of the circuits. Arithmetic units such as adders and multipliers are the core components in many embedded devices and hardware accelerators. In particular, multipliers have a significant influence on the performance and power characteristics of the system where they are inserted. As a result, approximate multiplier design has become an important research subject in recent years. This work discusses the state-of-the-art on the use of approximate computing to design energy-efficient multipliers. We observe that most of the proposed approximate multipliers rely on approximations in the partial product reduction, mainly exploiting approximate compressors or approximate adders. In addition, there are only few works targeting neural networks, which demonstrates that there is room for explore an approximate multiplier design in this application.The set of information provided in this paper allows to identify gaps in the literature and possibilities for new research on the design of low-power multipliers.
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Kenta, Shirane, Yamamoto Takahiro, and Tomiyama Hiroyuki. "A design methodology for approximate multipliers in convolutional neural networks: A case of MNIST." International Journal of Reconfigurable and Embedded Systems 10, no. 1 (2021): 1–10. https://doi.org/10.11591/ijres.v10.i1.pp1-10.

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In this paper, we present a case study on approximate multipliers for MNIST Convolutional Neural Network (CNN). We apply approximate multipliers with different bit-width to the convolution layer in MNIST CNN, evaluate the accuracy of MNIST classification, and analyze the trade-off between approximate multiplier&rsquo;s area, critical path delay and the accuracy. Based on the results of the evaluation and analysis, we propose a design methodology for approximate multipliers. The approximate multipliers consist of some partial products, which are carefully selected according to the CNN input. With this methodology, we further reduce the area and the delay of the multipliers with keeping high accuracy of the MNIST classification.
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Ashwini, Banoth, Vyasa Ranjith Kumar, Nallawar Amulya, and Dr P. .Munaswamy. "A Low-Power High-Accuracy Approximate Multiplier Using High-Order Approximate Compressors." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–9. https://doi.org/10.55041/ijsrem40282.

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To address the need to reduce power consumption, approximate multipliers have emerged as a potential solution for fault-tolerant applications. In this work, we present a new 8x8 approximate multiplier that focuses on minimizing performance while maintaining a high degree of accuracy. The design features two key features: firstly, based on their importance, different weights are handled by the compressors with different levels of precision, allowing for a trade-off between energy efficiency and minimum error. Second, higher order approximation compressors such as 8:2 compressors are used for intermediate weights to simplify the drive chain logic. This is, to our knowledge, the first design to successfully integrate higher-order approximate compressors into an approximate multiplier. Compared to a precision multiplier such as the Dadda tree multiplier, experimental results show that the proposed design offers significant energy savings while maintaining high accuracy. Key Words:- Approximate computing; Arithmetic circuits; Logic design; Low-power design; Partial Product reduction
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Prasad, M. V. S. Ram, B. Kushwanth, P. R. D. Bharadwaj, and P. T. Sai Teja. "Low-power and high-speed approximate multiplier using higher order compressors for measurement systems." ACTA IMEKO 11, no. 2 (2022): 1. http://dx.doi.org/10.21014/acta_imeko.v11i2.1244.

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At present, approximate multipliers are used in the image processing applications. These approximate multipliers are designed with the help of higher order compressors to decrease the number of addition stages involved for the lessening stages. The approximate computing is the best technique to improve the power efficiency and reduce delay path. With the use of approximate computing multiple compressors are designed. In this paper, 10:2 compressors are designed and implemented in the 32-bit multiplier and compared with the exact 32-bit multipliers. The proposed higher bit compressors along with the lower bit compressors are implemented to reduce the delay of the design. This type of digital circuits has much significance in measurement technologies, for enabling fast and accurate measurements. With the use of approximate compressors, the result may be ineffective, but the power consumption and delay are getting reduced. Hence, these proposed multipliers are only implemented the digital signal processing applications, where there is need for combining two or more signals. The proposed multiplier is used for implementing FIR filter resulted 27 ns delay which is far better than the exact multiplier having 119 ns. These multipliers also used in image processing applications and PSNR of image has been employed.
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Geethika, Ratnala. "Area and Power Optimized VLSI Architecture of Approximate Multiplier." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 06 (2024): 1–5. http://dx.doi.org/10.55041/ijsrem35995.

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When it comes to error-resistant applications, approximation computing offers the ability to reduce design complexity while increasing performance in terms of size, latency, and power efficiency. This brief discusses an innovative design technique for approximating multipliers. When it comes to error-resistant applications, approximation computing offers the ability to reduce design complexity while increasing performance in terms of size, latency, and power efficiency. Within the scope of this short, a unique 4-2 approximate compressor is presented. This compressor is complimentary to existing compressors that have been developed in previous work. Additionally, A proposed multiplier is built using the compressors, a constant approximation, and error correction. The simulation results show that the designed approximation multiplier performs satisfactorily. Within the Xilinx-Vivado environment, the implementation, synthesis, and simulation are carried out and recorded using the verilog HDL programming language. Key Words: approximate multiplier, exact compressor, approximate compressor and Verilog HDL.
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Dissertations / Theses on the topic "Approximate computing multiplier"

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Válek, Matěj. "Aproximativní implementace aritmetických operací v obrazových filtrech." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2021. http://www.nusl.cz/ntk/nusl-445540.

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Tato diplomová práce se zabývá  aproximativní implementace aritmetických operací v obrazových filtrech. Zejména tedy využitím aproximativních technik pro úpravu způsobu násobení v netriviálním obrazovém filtru. K tomu je využito několik technik, jako použití převodu násobení s pohyblivou řadovou čárkou na násobení s pevnou řadovou čárkou, či využití evolučních algoritmů zejména kartézkého genetického programování pro vytvoření nových aproximovaných násobiček, které vykazují přijatelnou chybu, ale současně redukují výpočetní náročnost filtrace. Výsledkem jsou evolučně navržené aproximativní násobičky zohledňující distribuci dat v obrazovém filtru a jejich nasazení v obrazovém filtru a porovnání původního filtru s aproximovaným fitrem na sadě barevných obrázků.
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Book chapters on the topic "Approximate computing multiplier"

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Wu, Ying, Chuangtao Chen, Chenyi Wen, Weikang Qian, Xunzhao Yin, and Cheng Zhuo. "Approximate Multiplier Design for Energy Efficiency: From Circuit to Algorithm." In Approximate Computing. Springer International Publishing, 2012. http://dx.doi.org/10.1007/978-3-030-98347-5_3.

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Sowmya, K. B., and Rajat Raj. "Approximate Multiplier for Power Efficient Multimedia Applications." In Proceedings of the International Conference on Paradigms of Computing, Communication and Data Sciences. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-8742-7_33.

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Sathiyapriya, S., and C. S. Manikandababu. "Design and Analysis of Approximate Multiplier for Image Processing Application." In Advances in Intelligent Systems and Computing. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-5029-4_16.

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Parvathi, M. "High-Accurate, Area-Efficient Approximate Multiplier for Error-Tolerant Applications." In Advances in Intelligent Systems and Computing. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-4032-5_10.

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Naga Sravanthi, V., and Sudheer Kumar Terlapu. "Design and Performance Analysis of Rounding Approximate Multiplier for Signal Processing Applications." In Smart Intelligent Computing and Applications. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9690-9_41.

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Senthil Kumar, V. M., and S. Ravindrakumar. "Design of an Area-Efficient FinFET-Based Approximate Multiplier in 32-nm Technology for Low-Power Application." In Advances in Intelligent Systems and Computing. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-3393-4_52.

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Zhang, Tingting, Honglan Jiang, Weiqiang Liu, et al. "Majority Logic-Based Approximate Multipliers for Error-Tolerant Applications." In Approximate Computing. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-98347-5_6.

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Aizaz, Zainab, Kavita Khare, and Aizaz Tirmizi. "Approximate Computing-Based Unsigned Multipliers for Image Processing Applications." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-6780-1_7.

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Terui, Akira. "GPGCD, an Iterative Method for Calculating Approximate GCD, for Multiple Univariate Polynomials." In Computer Algebra in Scientific Computing. Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-15274-0_22.

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Weis, Christian, Christina Gimmler-Dumont, Matthias Jung, and Norbert Wehn. "Design of Efficient, Dependable SoCs Based on a Cross-Layer-Reliability Approach with Emphasis on Wireless Communication as Application and DRAM Memories." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_18.

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AbstractMany applications show an inherent error resilience due to their probabilistic behavior. This inherent error resilience can be exploited to reduce the design margin for advanced technology nodes resulting in more energy and area efficient implementation. We present in this chapter a cross-layer approach for efficient reliability management in wireless baseband processing with special emphasis on memories since memories are most susceptible to dependability problems. A multiple-antenna (MIMO) system will be used as design example. Further on we focus on DRAMs (Dynamic Random Access Memories). All today’s computing systems rely on dependable DRAMs. In the future DRAM memories will become more undependable due to further scaling. This has to be counterbalanced with higher refresh rates, which leads to a higher DRAM power consumption. Recent research activities resulted in the concept of “approximate DRAM” to save power and improve performance by lowering the refresh rate or disabling refresh completely. Here, we present a holistic simulation environment for investigations on approximate DRAM and show the impact on error-resilient applications.
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Conference papers on the topic "Approximate computing multiplier"

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Crimmins, Aden, and Sonia Lopez Alarcon. "Approximate Quantum Array Multiplier." In 2024 IEEE International Conference on Quantum Computing and Engineering (QCE). IEEE, 2024. https://doi.org/10.1109/qce60285.2024.00017.

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Chen, Ruiqi, Yangxintong Lyu, Han Bao, et al. "FPGA-Based Approximate Multiplier for FP8." In 2025 IEEE 33rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2025. https://doi.org/10.1109/fccm62733.2025.00079.

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N, Bathlin Nelmin, R. S. Shaji, Hariprasad S, Sudeshna Shettygari, Vasan J. K, and Vijayan V. "Design of Approximate Multiplier Using Highly Compressed 5_2 Counter." In 2025 6th International Conference on Mobile Computing and Sustainable Informatics (ICMCSI). IEEE, 2025. https://doi.org/10.1109/icmcsi64620.2025.10883373.

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Velagaleti, Silpa Kesav, and Sujay Malraju. "Design and Implementation of LUT Based Approximate Multiplier for Energy-Efficient Computing." In 2025 3rd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT). IEEE, 2025. https://doi.org/10.1109/dicct64131.2025.10986416.

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Petla, Sai Tharun, Venkata Sudhakar Chowdam, Priyanka Ponkala, Thrisha Nichenametla, and Paramesh Polturu. "Comparative Analysis of Energy-Efficient Approximate Multiplier and Wallace Tree Multiplier for Error-Tolerant Applications." In 2025 3rd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT). IEEE, 2025. https://doi.org/10.1109/dicct64131.2025.10986753.

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Sravani, C. H., G. Mamatha, D. Jayanthi, and K. Jamal. "Dynamic Shifts for Approximate Multiplier: Clock Synchronized Operations in SSAM." In 2024 4th International Conference on Soft Computing for Security Applications (ICSCSA). IEEE, 2024. https://doi.org/10.1109/icscsa64454.2024.00118.

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Buxy, Nihar, and Shilpa D. R. "Innovative Approaches to Low-Cost Multiplier Design Using Approximate Computing and Clock Gating." In 2025 3rd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT). IEEE, 2025. https://doi.org/10.1109/dicct64131.2025.10986468.

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Hemalatha, M., T. Pavani, K. Ushaswini, K. Pallavi, K. Poornima, and J. Jaitra Manavi. "High-Speed and Area-Efficient Approximate Multiplier Using Truncation Technique." In 2024 OPJU International Technology Conference (OTCON) on Smart Computing for Innovation and Advancement in Industry 4.0. IEEE, 2024. http://dx.doi.org/10.1109/otcon60325.2024.10688060.

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G, Harissh, Mathumitha R, Dharini R. S, Valli PA, and Navya Mohan. "Low Power, High Accuracy Approximate Multiplier for Error-Resilient Image Processing Application." In 2024 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER). IEEE, 2024. http://dx.doi.org/10.1109/discover62353.2024.10750693.

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Lakshmi, L. J. N. Sree, and G. L. Madhumati. "Design of Dadda Multiplier with Minimum Area Delay Power(ADP) Product by using an Approximate Novel Compressor." In 2024 15th International Conference on Computing Communication and Networking Technologies (ICCCNT). IEEE, 2024. http://dx.doi.org/10.1109/icccnt61001.2024.10724161.

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