To see the other types of publications on this topic, follow the link: Approximate computing multiplier.
Journal articles on the topic 'Approximate computing multiplier'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 journal articles for your research on the topic 'Approximate computing multiplier.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.
1
O, Vignesh, Mangalam H, and AnjuBala K. "Survey on Approximate Multipliers for Image Processing." European Journal of Advances in Engineering and Technology 5, no. 5 (2018): 344–49. https://doi.org/10.5281/zenodo.10708304.
Full textAbstract:
<strong>ABSTRACT </strong> Approximate computing has become ravishing approach for designing high performance and low energy consumption with limited loss in accuracy for many digital logic designs. Since there is a trade-off between speed/power with accuracy shown through previous research works. The demand of high speed and power efficiency as well as the feature of error tolerant applications has driven the development of approximate arithmetic circuits. The most important arithmetic modules in a processor are adder and multipliers to determine the performance for many computing tasks in today’s digital systems. A comparative study of efficient algorithm and architecture for various approximate multipliers are presented in this survey. Approximate multiplier reduces the transistor count, power consumption, delay and it provides high speed output. The result shows that the proposed Approximate multiplier design accomplish significant reductions in power dissipation, delay and transistor count compared to an exact accurate multiplier design with small loss in accuracy. Comparison of extensive simulation results are shown for approximate multiplier. An application in image processing is performed, where peak signal to noise ratio of the image is analyzed. The image quality of the approximate multiplier shows satisfactory result compared to an accurate multiplier.
2
Vinodia, Ayushi. "Energy-Efficient Approximate Multiplier with Flexible Precision." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 741–51. http://dx.doi.org/10.22214/ijraset.2024.61704.
Full textAbstract:
Abstract: The method that can be utilized to increase accuracy and decrease energy use is approximate multiplication. A key component of many error-tolerant applications is multiplication. Approximate multipliers are increasingly utilized in energyefficient computing for applications tolerant of inaccuracy. Apart from multiplier performance, determining the appropriate approximate multiplier is challenging due to considerations of area and delay. Therefore, selecting the type of approximate full adder (FA) becomes a crucial decision-making factor. These adders are employed for summing partial products in multipliers. This study presents the design and evaluation of an approximate multiplier employing four distinct approximate adders. The design undergoes simulation and synthesis using Xilinx and Model Sim. Compared to previously proposed approximate multipliers, the proposed circuits demonstrate substantial reductions in area, time delay, and power consumption. According to experimental data, the area, latency, and average power consumption of the suggested adjustable approximate multiplier can be lowered by 10%, 34.96 ns, and 300 mW when contrasted to the Wallace tree multiplier.
3
Arham Dodal. "Efficient Approximate Multiplier for Image Processing Application." Journal of Information Systems Engineering and Management 10, no. 25s (2025): 712–22. https://doi.org/10.52783/jisem.v10i25s.4117.
Full textAbstract:
The field of approximate computing has garnered significant interest as a promising area for relatively error-resistant applications. At its core, approximate computing revolves around a trade-off between efficiency and accuracy. To optimize power consumption, delay, and area, a certain level of accuracy is sacrificed, provided it remains within acceptable limits. This research introduces a novel design for an approximate 4:2 compressor. Two distinct configurations for implementing this compressor are proposed and evaluated within the framework of an 8x8 Dadda multiplier. The study assesses both technology-dependent and technology-independent parameters, comparing them with the most recent approximate multipliers reported in recent literature. The performance of these multipliers is tested using a 45-nm standard CMOS technology node. Additionally, the quality and precision of the proposed approximate multiplier are evaluated using a range of statistical metrics. To demonstrate their practical utility, the proposed multipliers are applied to image processing tasks. The results indicate that the proposed designs outperform existing approximate multipliers in terms of efficiency for image processing applications.
4
Lu, Mi. "Runtime accuracy alterable approximate floatingpoint multipliers." International Robotics & Automation Journal 8, no. 2 (2022): 52–56. http://dx.doi.org/10.15406/iratj.2022.08.00244.
Full textAbstract:
Modern systems demand high computational power within limited resources. Approximate computing is a promising approach to design arithmetic units with tight resources for error-tolerant applications such as image and signal processing and computer vision. A floating-point multiplier is one of the arithmetic units with the highest complexity in such applications. Designing a floating-point multiplier based on the approximate computing technique can reduce its complexity as well as increase performance and energy efficiency. However, an unknown error rate for upcoming input data is problematic to design appropriate approximate multipliers. The existing solution is to utilize an error estimator relying on statistical analysis. In this paper, we propose new approximate floating-point multipliers based on an accumulator and reconfigurable adders with an error estimator. Unlike previous designs, our proposed designs are able to change the levels of accuracy at runtime. Thus, we can make errors distributed more evenly. In contrast to other designs, our proposed design can maximize the performance gain since reconfigurable multipliers are able to operate two multiplications in parallel once the low accuracy mode is selected. Furthermore, we apply a simple rounding technique to approximate floating-point multipliers for additional improvement. Our simulation results reveal that our new method can reduce area by 70.98% when error tolerance margin of our target application is 5%, and when its error tolerance margin is 3%, our rounding enhanced simple adders-based approximate multiplier can save area by 65.9%, and our reconfigurable adder-based approximate multiplier with rounding can save the average delay and energy by 54.95% and 46.67% respectively compared to an exact multiplier.
5
Osta, Mario, Ali Ibrahim, and Maurizio Valle. "Approximate Computing Circuits for Embedded Tactile Data Processing." Electronics 11, no. 2 (2022): 190. http://dx.doi.org/10.3390/electronics11020190.
Full textAbstract:
In this paper, we demonstrate the feasibility and efficiency of approximate computing techniques (ACTs) in the embedded Support Vector Machine (SVM) tensorial kernel circuit implementation in tactile sensing systems. Improving the performance of the embedded SVM in terms of power, area, and delay can be achieved by implementing approximate multipliers in the SVD. Singular Value Decomposition (SVD) is the main computational bottleneck of the tensorial kernel approach; since digital multipliers are extensively used in SVD implementation, we aim to optimize the implementation of the multiplier circuit. We present the implementation of the approximate SVD circuit based on the Approximate Baugh-Wooley (Approx-BW) multiplier. The approximate SVD achieves an energy consumption reduction of up to 16% at the cost of a Mean Relative Error decrease (MRE) of less than 5%. We assess the impact of the approximate SVD on the accuracy of the classification; showing that approximate SVD increases the Error rate (Err) within a range of one to eight percent. Besides, we propose a hybrid evaluation test approach that consists of implementing three different approximate SVD circuits having different numbers of approximated Least Significant Bits (LSBs). The results show that energy consumption is reduced by more than five percent with the same accuracy loss.
6
Zanandrea, Vinicius, Fabiane Benitti, and Cristina Meinhardt. "Energy-efficient Multiplier Design Through Approximate Computing: Current Trends and Future Prospects." Journal of Integrated Circuits and Systems 19, no. 3 (2024): 1–15. https://doi.org/10.29292/jics.v19i3.927.
Full textAbstract:
Approximate Computing can be effectively applied in error-tolerant applications in order to improve the energy efficiency of the circuits. Arithmetic units such as adders and multipliers are the core components in many embedded devices and hardware accelerators. In particular, multipliers have a significant influence on the performance and power characteristics of the system where they are inserted. As a result, approximate multiplier design has become an important research subject in recent years. This work discusses the state-of-the-art on the use of approximate computing to design energy-efficient multipliers. We observe that most of the proposed approximate multipliers rely on approximations in the partial product reduction, mainly exploiting approximate compressors or approximate adders. In addition, there are only few works targeting neural networks, which demonstrates that there is room for explore an approximate multiplier design in this application.The set of information provided in this paper allows to identify gaps in the literature and possibilities for new research on the design of low-power multipliers.
7
Kenta, Shirane, Yamamoto Takahiro, and Tomiyama Hiroyuki. "A design methodology for approximate multipliers in convolutional neural networks: A case of MNIST." International Journal of Reconfigurable and Embedded Systems 10, no. 1 (2021): 1–10. https://doi.org/10.11591/ijres.v10.i1.pp1-10.
Full textAbstract:
In this paper, we present a case study on approximate multipliers for MNIST Convolutional Neural Network (CNN). We apply approximate multipliers with different bit-width to the convolution layer in MNIST CNN, evaluate the accuracy of MNIST classification, and analyze the trade-off between approximate multiplier’s area, critical path delay and the accuracy. Based on the results of the evaluation and analysis, we propose a design methodology for approximate multipliers. The approximate multipliers consist of some partial products, which are carefully selected according to the CNN input. With this methodology, we further reduce the area and the delay of the multipliers with keeping high accuracy of the MNIST classification.
8
Ashwini, Banoth, Vyasa Ranjith Kumar, Nallawar Amulya, and Dr P. .Munaswamy. "A Low-Power High-Accuracy Approximate Multiplier Using High-Order Approximate Compressors." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–9. https://doi.org/10.55041/ijsrem40282.
Full textAbstract:
To address the need to reduce power consumption, approximate multipliers have emerged as a potential solution for fault-tolerant applications. In this work, we present a new 8x8 approximate multiplier that focuses on minimizing performance while maintaining a high degree of accuracy. The design features two key features: firstly, based on their importance, different weights are handled by the compressors with different levels of precision, allowing for a trade-off between energy efficiency and minimum error. Second, higher order approximation compressors such as 8:2 compressors are used for intermediate weights to simplify the drive chain logic. This is, to our knowledge, the first design to successfully integrate higher-order approximate compressors into an approximate multiplier. Compared to a precision multiplier such as the Dadda tree multiplier, experimental results show that the proposed design offers significant energy savings while maintaining high accuracy. Key Words:- Approximate computing; Arithmetic circuits; Logic design; Low-power design; Partial Product reduction
9
Prasad, M. V. S. Ram, B. Kushwanth, P. R. D. Bharadwaj, and P. T. Sai Teja. "Low-power and high-speed approximate multiplier using higher order compressors for measurement systems." ACTA IMEKO 11, no. 2 (2022): 1. http://dx.doi.org/10.21014/acta_imeko.v11i2.1244.
Full textAbstract:
At present, approximate multipliers are used in the image processing applications. These approximate multipliers are designed with the help of higher order compressors to decrease the number of addition stages involved for the lessening stages. The approximate computing is the best technique to improve the power efficiency and reduce delay path. With the use of approximate computing multiple compressors are designed. In this paper, 10:2 compressors are designed and implemented in the 32-bit multiplier and compared with the exact 32-bit multipliers. The proposed higher bit compressors along with the lower bit compressors are implemented to reduce the delay of the design. This type of digital circuits has much significance in measurement technologies, for enabling fast and accurate measurements. With the use of approximate compressors, the result may be ineffective, but the power consumption and delay are getting reduced. Hence, these proposed multipliers are only implemented the digital signal processing applications, where there is need for combining two or more signals. The proposed multiplier is used for implementing FIR filter resulted 27 ns delay which is far better than the exact multiplier having 119 ns. These multipliers also used in image processing applications and PSNR of image has been employed.
10
Geethika, Ratnala. "Area and Power Optimized VLSI Architecture of Approximate Multiplier." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 06 (2024): 1–5. http://dx.doi.org/10.55041/ijsrem35995.
Full textAbstract:
When it comes to error-resistant applications, approximation computing offers the ability to reduce design complexity while increasing performance in terms of size, latency, and power efficiency. This brief discusses an innovative design technique for approximating multipliers. When it comes to error-resistant applications, approximation computing offers the ability to reduce design complexity while increasing performance in terms of size, latency, and power efficiency. Within the scope of this short, a unique 4-2 approximate compressor is presented. This compressor is complimentary to existing compressors that have been developed in previous work. Additionally, A proposed multiplier is built using the compressors, a constant approximation, and error correction. The simulation results show that the designed approximation multiplier performs satisfactorily. Within the Xilinx-Vivado environment, the implementation, synthesis, and simulation are carried out and recorded using the verilog HDL programming language. Key Words: approximate multiplier, exact compressor, approximate compressor and Verilog HDL.
11
Rizos, Ioannis, Georgios Papatheodorou, and Aristides Efthymiou. "Designing Approximate Reduced Complexity Wallace Multipliers." Electronics 14, no. 2 (2025): 333. https://doi.org/10.3390/electronics14020333.
Full textAbstract:
In the nano-scale era, enhancing speed while minimizing power consumption and area is a key objective in integrated circuits. This demand has motivated the development of approximate computing, particularly useful in error-tolerant applications such as multimedia, machine learning, signal processing, and scientific computing. In this research, we present a novel method to create approximate integer multiplier circuits. This work is based on a modification of the well-known Wallace tree multiplier, called the Reduced Complexity Wallace Multiplier (RCWM). Approximation is introduced by replacing conventional Full Adders with approximate ones during the partial product reduction phase. This research investigates the characteristics of 8×8-, 16×16-, and 32×32-bit Approximate Reduced Complexity Wallace Multipliers (ARCWM), evaluating their accuracy, area usage, delay, and power consumption. Given the vast search space created by different combinations and placements of these approximate Adders, a Genetic Algorithm was used to efficiently explore this space and optimize the ARCWMs. The resulting ARCWMs have an area reduction of up to 65% and a power consumption reduction of up to 70%, with no worse delay than the RCWM. Multipliers created with this method can be used in any application that requires parallel multiplication, such as neural accelerators, trading accuracy for area and power reduction. Additionally, an ARCWM can be used alongside a slow shift-and-accumulate multiplier trading off accuracy for faster calculation. This methodology provides valuable guidance for designers in selecting the optimal configuration of approximate Full Adders, tailored to the specific requirements of their applications. Alongside the methodology, we provide all of the tools used to achieve our results as open-source code, including the Register-Transfer Level (RTL) code of the 8×8-, 16×16-, and 32×32-bit Wallace Multipliers.
12
C, Hema, Shravani G, P. Sivaphaneendra, Sinchana ., and Soundarya L. "Implementation of Hardware and Energy Efficient Approximate Multiplier Architectures Using 4-2 Compressor for Images." International Journal for Research in Applied Science and Engineering Technology 11, no. 4 (2023): 2177–83. http://dx.doi.org/10.22214/ijraset.2023.50528.
Full textAbstract:
Abstract: Approximate computing is tentatively applied in some digital signal processing applications which have an inherent tolerance for erroneous computing results. The approximate arithmetic blocks are utilized in them to improve the electrical performance of these circuits. Multiplier is one of the fundamental units in computer arithmetic blocks. Moreover, the 4-2 compressors are widely employed in the parallel multipliers to accelerate the compression process of partial products. In this brief, three novel approximate 4-2 compressors are proposed and utilized in 8-bit multipliers. Meanwhile, an error-correcting module (ECM) is presented to promote the error performance of approximate multiplier with the proposed 4-2 compressors. In this brief, the number of the approximate 4-2 compressor’s outputs is innovatively reduced to one, which brings further improvements in the energy-efficiency. This Design is implemented using Verilog HDL and simulated by Modelsim 6.4 c and synthesized by Xilinx tool.
13
Faraji, S. Rasoul, Pierre Abillama, and Kia Bazargan. "Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs." ACM Transactions on Reconfigurable Technology and Systems 15, no. 3 (2022): 1–25. http://dx.doi.org/10.1145/3494570.
Full textAbstract:
Multipliers are used in virtually all Digital Signal Processing (DSP) applications such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is needed, as in 4K video processing, or where hardware resources are limited, as in mobile and IoT devices. We propose a novel, low-cost, low energy, and high-speed approximate constant coefficient multiplier (CCM) using a hybrid binary-unary encoding method. The proposed method implements a CCM using simple routing networks with no logic gates in the unary domain, which results in more efficient multipliers compared to Xilinx LogiCORE IP CCMs and table-based KCM CCMs (Flopoco) on average. We evaluate the proposed multipliers on 2-D discrete cosine transform algorithm as a common DSP module. Post-routing FPGA results show that the proposed multipliers can improve the {area, area × delay, power consumption, and energy-delay product} of a 2-D discrete cosine transform on average by {30%, 33%, 30%, 31%}. Moreover, the throughput of the proposed 2-D discrete cosine transform is on average 5% more than that of the binary architecture implemented using table-based KCM CCMs. We will show that our method has fewer routability issues compared to binary implementations when implementing a DCT core.
14
Liu, Hao, Mingjiang Wang, Longxin Yao, and Ming Liu. "A Piecewise Linear Mitchell Algorithm-Based Approximate Multiplier." Electronics 11, no. 12 (2022): 1913. http://dx.doi.org/10.3390/electronics11121913.
Full textAbstract:
In the field of integrated circuits, the computational cost has always been a crucial design metric. In recent years, with the continuous development in the field of computing, the requirements for computation have been growing rapidly. Reducing the computational cost and improving computational efficiency have become the key issues in the field. There are many error-tolerant applications in the multimedia field where approximate computing techniques can be applied to improve computational efficiency and reduce computational costs at the cost of acceptable computational errors. This paper proposed a piecewise linear Mitchell algorithm based on Mitchell logarithmic approximation multiplication algorithm. Additionally, the Pwl-Mit multiplier is designed according to the improved algorithm combined with the data truncation technique. The proposed approximate multiplier has better statistical performance compared with the state-of-the-art multipliers. The design is simulated and synthesized at the TSMC 65 nm process, and its reliability is verified using discrete cosine transform (DCT) transform.
15
Jonnalagadda, Muktesha Mani Pradeep Sarma, Saikrishna Dabbakuti, Raju Gumma, and Tirupati Rao Karumanchi. "Energy Efficient Compact Approximate Multplier for Error-Resilient Applications." International Journal for Research in Applied Science and Engineering Technology 13, no. 3 (2025): 2792–98. https://doi.org/10.22214/ijraset.2025.67907.
Full textAbstract:
Abstract: This study focuses on enhancing system performance through approximate computing by proposing efficient 8- transistor and 20-transistor 4:2 compressors for approximate multipliers. These designs leverage CMOS technology with constant and conditional approximation techniques to minimize errors while eliminating the need for an error recovery module. The 20-transistor compressor achieves higher accuracy at a slight area cost, while the proposed multiplier demonstrates a 50% reduction in area and a 93% improvement in power-delay-product compared to exact multipliers
16
Dhanasekar, J., and V. K. Sudha. "Implementation of Energy Effective Error Resistant Adders and Multipliers in Image Denoising Applications." Journal of Nanoelectronics and Optoelectronics 18, no. 1 (2023): 33–42. http://dx.doi.org/10.1166/jno.2023.3371.
Full textAbstract:
The design of digital VLSI circuits must take energy efficiency into consideration. Reducing the circuit’s power consumption, which has been a major issue since 2000, would increase the necessity for energy efficiency. Error-tolerant systems heavily rely on approximate computation methods to increase power efficiency. The key factors of the system’s overall power consumption and area computation are adders and multipliers, which are also crucial in approximate computing. High energy-efficiency adders can be used to create additional multipliers. In order to dramatically minimize power consumption, this work builds and implements 8×8 Dadda multipliers using 1 bit approximation adders. Calculation is sped up by using the Dadda multiplier. In turn, by reducing propagation latency, the suggested design lowers power consumption in digital CMOS circuitry. The proposed multiplier design with approximate adders, which was created in Verilog HDL, simulated in FPGA, and synthesized in FPGA platform, is implemented on an ASIC platform using Cadence 90 nm Technology. The Gaussian filter additionally employs the proposed Dadda multiplier for picture denoising in approximation adder-based image processing applications.
17
R., Sireesha, K.Raju, Rani B.Geetha, and V.Saraswathi. "Optimizing Power Consumption in Signal Processing through Approximate Compressors." Journal of VLSI Design and its Advancement 7, no. 1 (2024): 33–41. https://doi.org/10.5281/zenodo.10795836.
Full textAbstract:
<em>The majority of computer arithmetic applications are highly precise and reliable because they are implemented utilising digital logic circuits. However, a lot of applications, like those in voice processing, multimedia, image processing, and image enhancement, segmentation, compression, and so on, can withstand computational mistakes and imprecision and still yield meaningful and practical results. It is not always appropriate or efficient to utilise exact and accurate models and algorithms in these kinds of applications. When constructing energy-efficient systems, for example, the paradigm of inexact computing focuses on relaxing absolutely accurate and perfectly predictable building components. This enables imprecise computing to take advantage of a possible boost in performance and power efficiency together with a drop in complexity and cost, rerouting the current design process of digital circuits and systems. Using this feature, approximation (or inexact) computing focuses on designing simpler, yet approximate circuits that perform better and/or use less power than precise (exact) logic circuits. In certain digital signal processing applications, approximate computing is used in a hesitant manner because it naturally tolerates inaccurate computing outputs. They use the approximation arithmetic blocks in them to enhance these circuits' electrical performance. This enables imprecise computing to take advantage of a possible boost in performance and power efficiency together with a drop in complexity and cost, rerouting the current design process of digital circuits and systems. Using this feature, approximation (or inexact) computing focuses on designing simpler, yet approximate circuits that perform better and/or use less power than precise (exact) logic circuits. In certain digital signal processing applications, approximate computing is used in a hesitant manner because it naturally tolerates inaccurate computing outputs. They use the approximation arithmetic blocks in them to enhance these circuits' electrical performance. The approach we developed in this research may greatly lower the cost and power consumption of signal processing jobs by employing approximate compressors to create low-power approximate multipliers and minimising the mistakes resulting from the approximation. Our primary focus in this was using compressors to approximate partial product reductions.</em> <strong><em> </em></strong>
18
Kumar D., Anil. "Design and FPGA Implementation of High Throughput and Low Latency Machine Learning based Approximate Multiplier for Image Processing Applications." WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL 17 (July 5, 2022): 287–99. http://dx.doi.org/10.37394/23203.2022.17.33.
Full textAbstract:
One of the uses of approximate circuits is machine learning (ML) and with the help of inexact logic minimization as well as through probabilistic pruning, these approximate computing circuits can be implemented. Nowadays, these approximate circuits have been widely explored due to their essential factors such as compact silicon areas well as low power consumption in movable devices. This research work shows how a 4:2 compressor can be designed using inexact logic minimization and thereby reversing a few bits of the output to ensure efficiency as well as accuracy. The average area, propagation delay as well as the average power of the proposed 4:2 compressor is been calculated and are employed in the 8 × 8 and 16x16 Dadda multiplier and truncation and rounding-based scalable approximate multiplier (TOSAM). Using Vivado Design Software Systems in 45nm technology, all the simulations were carried out and the MATLAB tool make use of error analysis to distinguish between precise as well as approximate proposed circuits. This work is mainly concentrated on the design of exact and approximate multipliers and measures the error between them and minimization of this error using the Machine Learning approach and finally validated the results on the Artix-7 FPGA development board of part XCA7CSG324_110t, the partial products which are generated by multipliers are added using 4:2 compressor adder. In the case of digital processing at nano-metric scales, approximate or inexact computing is considered one of the important examples. For computer arithmetic designs, inexact computation plays a significant role, and the new approximate 4:2 compressors are used in a multiplier that is based on TOSAM. These architectures mainly depend on various compression aspects to enable inaccuracy in computing which is described as error rate and is also referred to as normalized error distance which is used to satisfy circuit-based figures of merit, the number of transistors, delay as well as consumption of power. For a Dadda multiplier, four distinct approaches for exploiting the suggested approximation compressors are designed as well as evaluated. The usage of approximate multipliers for image processing, as well as a wide range of simulation results, are presented in this work. When contrasted to an accurate design, the proposed designs achieve a substantial reduction in the number of transistors, power dissipation as well as delay. Furthermore, the presented multiplier models exhibit outstanding image multiplication capabilities in terms of average normalized error distance as well as peak signal-to-noise ratio that is more than 50dB for the analyzed image samples. The proposed ML-based digital system has been developed in Vivado Design Suite and synthesized which is designed using Verilog HDL. Based on obtained results, 17% reduction in power, 21% reduction in latency, and 33% improvement in throughput.
19
Venkata Sudhakar, Chowdam, Suresh Babu Potladurty, and Prasad Reddy Karipireddy. "Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 2 (2025): 398. https://doi.org/10.11591/ijres.v14.i2.pp398-411.
Full textAbstract:
<p>The multiplier is an essential component in real-time applications. Even though approximation arithmetic affects output accuracy in multipliers, it offers a realistic avenue to constructing power area and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this paper, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HA) and full adders (A-FA), which are strategically placed to add partial products at the most significant bit (MSB) positions, and OR gates are used to add partial products at the lower significant bit (LSB). In addition, this research article demonstrates unsigned and signed multipliers using the ripple carry adder (RCA), carry save adder (CSA), conditional sum adder (COSA), carry select adder (CSLA), and clock gating technique. The proposed multipliers are implemented in Verilog hardware description language (HDL) and simulated on the Xilinx VIVADO 2021.2 design tool with target platform Artix-7 AC701 FPGA. The simulation results found that unsigned and signed approximate multiplier power consumption was reduced by 13% and 18.18% respectively and enhanced accuracy.</p>
20
Zanandrea, Vinicius, Douglas Borges, Vagner Rosa, and Cristina Meinhardt. "On the Use of Low-power Devices, Approximate Adders and Near-threshold Operation for Energy-efficient Multipliers." Journal of Integrated Circuits and Systems 18, no. 2 (2023): 1–12. http://dx.doi.org/10.29292/jics.v18i2.754.
Full textAbstract:
With the rising importance of power consumption in battery-powered devices, approximate computing techniques have emerged as a promising approach to strike a balance between exact computation and power savings, leading to improved delays. This paper investigates the combination of near-threshold operation and approximate adders to design power-efficient multipliers. We analyzed four multiplier architectures using 16 nm low-power and high-performance models. At the transistor level, three strategies for approximate full adders are explored, focusing on both partial product reduction and the final addition stage of the multipliers. Eleven test cases are thoroughly evaluated to identify the most suitable approximate circuit, considering the trade-offs among power, performance, and accuracy. The obtained results demonstrate a substantial reduction in power consumption at near-threshold operation. The replacement of exact full adders with the approximate copy strategy in the least significant bits of the multipliers leads to a reduction of up to 34.4% in power consumption and 19.2% in delay. The design-space exploration carried out in this study provides valuable insights for designers to choose the best approximate multiplier based on specific design requirements.
21
Uppugunduru, Anil Kumar, and Ershad Ahmed Syed. "Compressor based approximate multiplier architectures for media processing applications." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 4 (2021): 2953–61. https://doi.org/10.11591/ijece.v11i4.pp2953-2961.
Full textAbstract:
Approximate computing is an attractive technique to gain substantial improvement in the area, speed, and power in applications where exact computation is not required. This paper proposes two improved multiplier designs based on a new 4:2 approximate compressor circuit to simplify the hardware at the partial product reduction stage. The proposed multiplier designs are targeted towards error-tolerant applications. Exhaustive error and hardware analysis has been carried out on the existing and proposed multiplier designs. The results prove that the proposed approximate multiplier architecture performs better than the existing architectures without significant compromise on quality metrics. Experimental results show that die-area and power consumed are reduced up to 28%, and 25.29% respectively in comparison with the existing designs without significant compromise on accuracy.
22
Satyanarayana, P. V. V., M. Venkanna, S. Jayasri, J. Vasavi Kalyani, and B. Ramjee. "Design & Implementation of Approximate 7:2 Compressor Based 16-bit Dadda Multiplier using Verilog." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 1 (2023): 39–48. http://dx.doi.org/10.35940/ijrte.a7570.0512123.
Full textAbstract:
Now a days the technology is growing day by day with faster rate. Particularly the usage of electronics is increasing in wide range of ways depending on their intended purpose and preferences. In this regard multipliers are playing a vital role because they allow us to perform complex arithmetic operations involving large numbers more efficiently. Instead of performing a series of addition or subtraction operations, a multiplier allows us to perform the operation in a single step within no time that is the challenge of today’s world. So in addition to being more efficient, multipliers also have practical applications in fields such as engineering, computer science, and cryptography also used , for example, in the design of digital circuits and in the encryption and decryption of data. Overall, multipliers playing an important role in mathematics and its applications and are essential tools for performing complex computations efficiently. Compressors play a vital role in realizing the high speed multipliers. In error resilient applications such as Image processing, Multimedia and Matrix multiplication the approximate computing is used, which provides meaningful results faster with lower power consumption. In previous work the compressors are designed using the full adders which provides accurate results. The 4:2 and 5:2 approximate compressors are then introduced with 18% delay reduction and ADP reduction up to 52%. Now the further work concentrated on the implementation of 7:2 Approximate Compressor based multiplier, to further enhance the performance of multipliers. The proposed design will be expected to provide maximum extent of reduction in area, delay or power consumption and achieves improvement in terms of speed as compared to the 4:2 and 5:2 compressor based approximate multiplier.
23
Kumar, Uppugunduru Anil, and Syed Ershad Ahmed. "Compressor based approximate multiplier architectures for media processing applications." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 4 (2021): 2953. http://dx.doi.org/10.11591/ijece.v11i4.pp2953-2961.
Full textAbstract:
Approximate computing is an attractive technique to gain substantial improvement in the area, speed, and power in applications where exact computation is not required. This paper proposes two improved multiplier designs based on a new 4:2 approximate compressor circuit to simplify the hardware at the partial product reduction stage. The proposed multiplier designs are targeted towards error-tolerant applications. Exhaustive error and hardware analysis has been carried out on the existing and proposed multiplier designs. The results prove that the proposed approximate multiplier architecture performs better than the existing architectures without significant compromise on quality metrics. Experimental results show that die-area and power consumed are reduced upto 28%, and 25.29% respectively in comparison with the existing designs without significant compromise on accuracy.
24
E., Sindhu Dharani, and Sharmila Raj V. "LOW POWER AND LOW AREA MULTIPLICATION CIRCUITS THROUGH PARTIAL PRODUCT PERFORATION." International Journal of Computational Research and Development 1, no. 2 (2017): 44–48. https://doi.org/10.5281/zenodo.437990.
Full textAbstract:
Focus on hardware-level approximation by introducing the partial product perforation technique for designing approximate multiplication circuits. The partial product perforation method for creating approximate multipliers. It omit the generation of some partial products, thus reducing the number of partial products that have to be accumulated; we decrease the area, power. The major contributions of this work, the software-based perforation technique on the design of hardware circuits, obtaining the optimized design solutions regarding the power–area–error tradeoffs. Analyze in a mathematically rigorous manner the arithmetic accuracy of partial product perforation and prove that it delivers a bounded and predictable output error. Error analysis is not bound to specific multiplier architecture and can be applied with error guarantees to every multiplication circuit regardless of its architecture that compared with the respective exact design, the partial product perforation. Index Terms: Approximate Arithmetic Circuits, Approximate Computing, Approximate Multiplier, Error Analysis & Low Power.
25
Yang, Zhixi, Xianbin Li, and Jun Yang. "Approximate Compressor-Based Multiplier Design Methodology for Error-Resilient Digital Signal Processing." Journal of Circuits, Systems and Computers 29, no. 14 (2020): 2050233. http://dx.doi.org/10.1142/s0218126620502333.
Full textAbstract:
As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25[Formula: see text]dB for image processing; similarly, with a decrease of 0.3[Formula: see text]dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.
26
P, V. V. Satyanarayana, Venkanna M., Jayasri S., Vasavi Kalyani J., and Ramjee B. "Design & Implementation of Approximate 7:2 Compressor Based 16-bit Dadda Multiplier using Verilog." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 1 (2023): 39–48. https://doi.org/10.35940/ijrte.A7570.0512123.
Full textAbstract:
<strong>Abstract:</strong> Now a days the technology is growing day by day with faster rate. Particularly the usage of electronics is increasing in wide range of ways depending on their intended purpose and preferences. In this regard multipliers are playing a vital role because they allow us to perform complex arithmetic operations involving large numbers more efficiently. Instead of performing a series of addition or subtraction operations, a multiplier allows us to perform the operation in a single step within no time that is the challenge of today’s world. So in addition to being more efficient, multipliers also have practical applications in fields such as engineering, computer science, and cryptography also used , for example, in the design of digital circuits and in the encryption and decryption of data. Overall, multipliers playing an important role in mathematics and its applications and are essential tools for performing complex computations efficiently. Compressors play a vital role in realizing the high speed multipliers. In error resilient applications such as Image processing, Multimedia and Matrix multiplication the approximate computing is used, which provides meaningful results faster with lower power consumption. In previous work the compressors are designed using the full adders which provides accurate results. The 4:2 and 5:2 approximate compressors are then introduced with 18% delay reduction and ADP reduction up to 52%. Now the further work concentrated on the implementation of 7:2 Approximate Compressor based multiplier, to further enhance the performance of multipliers. The proposed design will be expected to provide maximum extent of reduction in area, delay or power consumption and achieves improvement in terms of speed as compared to the 4:2 and 5:2 compressor based approximate multiplier.
27
Kanala, Vijaya Swathi S. Lakshmi Kanth. "An Ultra-Efficient Approximate Multiplier with Error Compensation for Error-Resilient Applications." International Journal in Engineering Sciences 1, no. 5 (2024): 16.24. https://doi.org/10.5281/zenodo.13889040.
Full textAbstract:
Approximate computing offers a pathway to boost hardware efficiency for error-resilient tasks such as neural networks and image processing by prioritizing speed over absolute accuracy. This briefing introduces an ultra-efficient approximate multiplier featuring error compensation. It integrates a constant compensation term for the least significant half of the product, achieving a nuanced hardware-accuracy equilibrium. Further refining precision is a low-complexity error compensation module (ECM). Through simulation with HSPICE utilizing 7nm tri-gate FinFET technology, this design significantly amplifies the energy-delay product, surpassing both exact and existing approximate designs by averages of 77% and 54% respectively. MATLAB simulations corroborate its accuracy, aligning closely with exact multipliers commonly employed in neural networks, boasting an average Peak Signal-to-Noise Ratio (PSNR) exceeding 51dB in image multiplication. Consequently, it emerges as a compelling substitute for precise multipliers in practical, error-resilient applications.
28
V.P, Visanthi. "DESIGN AND IMPLEMENTATION OF A NOVEL ENERGY-EFFICIENT MULTIPLIER CIRCUIT USING APPROXIMATE COMPUTING TECHNIQUE." International Journal Of Trendy Research In Engineering And Technology 07, no. 02 (2023): 01–05. http://dx.doi.org/10.54473/ijtret.2023.7201.
Full textAbstract:
A promising paradigm for many imprecision-tolerant applications has recently been identified as approximate arithmetic. By reducing accuracy standards, it can significantly reduce circuit complexity, latency, and energy consumption. In this research, we present a unique significance-driven logic compression (SDLC) approach for an energy-efficient approximate multiplier design. An algorithmic and adjustable lossy compression of the partial product rows based on their progressive bit importance is the core of this approach. To lessen the number of product rows, the resulting product terms are then commutatively remapped. As a result, the multiplier's complexity in terms of the number of logic cells and the lengths of critical routes is significantly decreased.
29
Y, Joseph, Naga Rohini K, Sudheer Babu M, Srinadh G, and K. Akhila. "Optimized Majority Logic Approximate Adders and Multipliers for Low-Power Computing." International Journal for Modern Trends in Science and Technology 11, no. 03 (2025): 149–56. https://doi.org/10.5281/zenodo.15084775.
Full textAbstract:
<em>Approximate arithmetic circuits based on CMOS technology have been widely explored for their potential in low-power and error-tolerant computing. Various designs of approximate adders and multipliers for both fixed-point and floating-point arithmetic have been proposed. As a key paradigm in nanoscale technologies, approximate computing enables energy-efficient arithmetic operations while tolerating computational errors. Majority logic (ML), particularly its fundamental component—the 3-input majority voter—has been extensively utilized in digital circuit design across emerging technologies. In this work, we propose a one-bit approximate full adder based on majority logic, along with multi-bit approximate full adder designs. Additionally, we explore their application in Quantum-Dot Cellular Automata (QCA) as a case study. The proposed designs are evaluated based on hardware efficiency metrics, including delay and area, as well as error performance. Comparative analysis with existing circuits from the literature demonstrates that the optimized designs achieve superior performance. Furthermore, we highlight the significance of Finite Impulse Response (FIR) filters in signal processing and communication. Since FIR filter performance heavily relies on adder and multiplier units, our proposed approximate arithmetic circuits offer potential improvements in power and area efficiency for such applications.</em>
30
Leon, Vasileios, Theodora Paparouni, Evangelos Petrongonas, Dimitrios Soudris, and Kiamal Pekmestzi. "Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers." ACM Transactions on Embedded Computing Systems 20, no. 5 (2021): 1–21. http://dx.doi.org/10.1145/3448980.
Full textAbstract:
Approximate computing has emerged as a promising design alternative for delivering power-efficient systems and circuits by exploiting the inherent error resiliency of numerous applications. The current article aims to tackle the increased hardware cost of floating-point multiplication units, which prohibits their usage in embedded computing. We introduce AFMU (Approximate Floating-point MUltiplier), an area/power-efficient family of multipliers, which apply two approximation techniques in the resource-hungry mantissa multiplication and can be seamlessly extended to support dynamic configuration of the approximation levels via gating signals. AFMU offers large accuracy configuration margins, provides negligible logic overhead for dynamic configuration, and detects unexpected results that may arise due to the approximations. Our evaluation shows that AFMU delivers energy gains in the range 3.6%–53.5% for half-precision and 37.2%–82.4% for single-precision, in exchange for mean relative error around 0.05%–3.33% and 0.01%–2.20%, respectively. In comparison with state-of-the-art multipliers, AFMU exhibits up to 4–6× smaller error on average while delivering more energy-efficient computing. The evaluation in image processing shows that AFMU provides sufficient quality of service, i.e., more than 50 db PSNR and near 1 SSIM values, and up to 57.4% power reduction. When used in floating-point CNNs, the accuracy loss is small (or zero), i.e., up to 5.4% for MNIST and CIFAR-10, in exchange for up to 63.8% power gain.
31
Tabrizchi, Sepehr, Atiyeh Panahi, Fazel Sharifi, Hamid Mahmoodi, and Abdel-Hameed A. Badawy. "Energy-Efficient Ternary Multipliers Using CNT Transistors." Electronics 9, no. 4 (2020): 643. http://dx.doi.org/10.3390/electronics9040643.
Full textAbstract:
In recent decades, power consumption has become an essential factor in attracting the attention of integrated circuit (IC) designers. Multiple-valued logic (MVL) and approximate computing are some techniques that could be applied to integrated circuits to make power-efficient systems. By utilizing MVL-based circuits instead of binary logic, the information conveyed by digital signals increases, and this reduces the required interconnections and power consumption. On the other hand, approximate computing is a class of arithmetic computing used in systems where the accuracy of the computation can be traded-off for lower energy consumption. In this paper, we propose novel designs for exact and inexact ternary multipliers based on carbon-nanotube field-effect transistors (CNFETs). The unique characteristics of CNFETs make them a desirable alternative to MOSFETs. The simulations are conducted using Synopsys HSPICE. The proposed design is compared against existing ternary multipliers. The results show that the proposed exact multiplier reduces the energy consumption by up to 6 times, while the best inexact design improves energy efficiency by up to 35 time compared to the latest state-of-the-art methods. Using the imprecise multipliers for image processing provides evidence that these proposed designs are a low-power system with an acceptable error.
32
Swami G, Narayan, Bhuvana D T, Keerthana M R, Ankita B, and Manoja E. "Optimization of Delay and Area for Approximate Radix-8 Booth Multiplier." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–6. https://doi.org/10.55041/ijsrem39405.
Full textAbstract:
This paper investigates the optimization of Radix-8 Booth Multipliers, which are essential for efficient arithmetic operations in modern digital systems, particularly in applications such as digital signal processing, telecommunications, and image processing where rapid and accurate calculations are crucial. The study aims to enhance performance by focusing on reducing both delay and area while ensuring that acceptable accuracy levels are maintained for error-tolerant applications. To achieve these optimization goals, we compare three methodologies: the Carry Save Adder (CSA), the Kogge Stone Adder (KSA), and the Carry Look-Ahead Adder (CLA), each of which presents unique advantages and trade-offs in terms of speed, area utilization, and power consumption. The results of our analysis demonstrate that the Kogge Stone Adder provides the best overall performance in terms of speed and area efficiency, making it the most suitable choice for optimizing Radix-8 Booth Multipliers, particularly in scenarios where high performance and efficient resource use are critical. By emphasizing these findings, this study contributes valuable insights into the design of more efficient multipliers that can meet the increasing demands of contemporary digital applications. Key Words: Radix-8 Booth Multiplier, approximate computing, delay optimization, area optimization, Carry Save Adder (CSA), Kogge Stone Adder (KSA), Carry Look-Ahead Adder (CLA), digital systems, arithmetic operations, performance enhancement, error-tolerant applications, partial product generation, hardware description languages (HDLs), digital signal processing, machine learning, approximation techniques, simulation and testing, power consumption, ASIC design.
33
Manogna, Manchiryala, and M. Shiva Kumar. "Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits using Quantam-Dot Celluar Automata (QCA) Technique." International Journal for Research in Applied Science and Engineering Technology 11, no. 10 (2023): 704–19. http://dx.doi.org/10.22214/ijraset.2023.56082.
Full textAbstract:
Abstract: In this paper, we propose an approximate multiplier that is Approximate computing (AC) offers benefits by reducing the requirement for accuracy, thereby reducing delay. The majority logic (ML) gate functions as the fundamental logic block of many emerging nanotechnologies. These adders are designed to prevent the propagation of inexact carry-out signals to higher order computing parts to enhance accuracy. We implemented the proposed multiplier by using a unique partial product reduction (PPR) circuitry, which was based on the parallel approximate 6:3 compressor. The implemented by quantum-dot cellular automata (QCA) are analyzed to evaluate the adder designs. A significant improvement is observed over previous designs based on the experimental results. The proposed design is further designed using kogge stone adder. Finally, It has added advantage that reduces logic size and facilitates with less power and delay. Here we are using Verilog HDL and Xilinx ISE14.8 software tools for simulation and synthesis purpose
34
Park, Hyun-Sang. "Approximate Computing Based 24×8 Multiplier Architecture for Image Processing Algorithms." Journal of Korean Institute of Information Technology 15, no. 1 (2017): 123. http://dx.doi.org/10.14801/jkiit.2017.15.1.123.
Full text
35
Rust, Jochen, Nils Heidmann, and Steffen Paul. "Approximate computing of two-variable numeric functions using multiplier-less gradients." Microprocessors and Microsystems 48 (February 2017): 48–55. http://dx.doi.org/10.1016/j.micpro.2016.09.005.
Full text
36
Osorio, Roberto, and Gabriel Rodríguez. "Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors." IEEE Access 7 (April 29, 2019): 14. https://doi.org/10.1109/ACCESS.2019.2913743.
Full textAbstract:
Approximate computing has been exploited for many years in application-specific architectures. Recently, it has also been proposed for low-power programmable processors. However, this poses some challenges as, in a microprocessor, the energy consumed by fetching and decoding an instruction may be significantly higher than that of the execution itself. Therefore, approximate computing would be advisable only for those instructions, in which the execution stage is significantly expensive in terms of energy consumption. In this paper, we present new architectures for truncated SIMD multipliers able to calculate signed and unsigned products from 8 × 8 to 64× 64 bits. Next, we analyze the precision loss incurred by truncation for all product sizes. We implement accurate and truncated architectures for both scalar and SIMD products and find that truncation allows area savings of up to 27%. The proposed design is experimentally evaluated in different scenarios, showing potential energy savings ranging from 29% to 42%. Finally, this paper analyzes the overall convenience of introducing truncated SIMD architectures with respect to accurate SIMD and scalar architectures.
37
Osorio, Roberto R., and Gabriel Rodriguez. "Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors." IEEE Access 7 (2019): 56353–66. http://dx.doi.org/10.1109/access.2019.2913743.
Full text
38
Lee, Edward H., and S. Simon Wong. "Analysis and Design of a Passive Switched-Capacitor Matrix Multiplier for Approximate Computing." IEEE Journal of Solid-State Circuits 52, no. 1 (2017): 261–71. http://dx.doi.org/10.1109/jssc.2016.2599536.
Full text
39
Izadi, Azin, and Vahid Jamshidi. "LHTAM: Low-power and high-speed approximate multiplier for tiny inexact computing systems." Computers and Electrical Engineering 123 (April 2025): 110215. https://doi.org/10.1016/j.compeleceng.2025.110215.
Full text
40
Shafiabadi, Mohammad Ali, and Fazel Sharifi. "Approximate 5-2 Compressor Cell Using Spin-Based Majority Gates." SPIN 10, no. 02 (2020): 2040004. http://dx.doi.org/10.1142/s2010324720400044.
Full textAbstract:
One of the most interesting solutions for decreasing the static power of computational circuits is to use approximate computing. Approximate computing has been extensively considered to trade-off limited accuracy for improvements in other circuit metrics such as area, power and performance. On the other hand, the increasing leakage power and limited scalability have become serious obstacles that prevent the continuous miniaturization of conventional CMOS-based logic circuits. Spintronic devices are being considered as a promising alternative technology for silicon-based FET to implement digital circuits. In this paper, an approximate 5-2 compressor cell is presented using spin-based devices. The proposed circuit is designed by majority gates which can be implemented very easily and efficiently by spintronic threshold device (STD). The proposed design has been simulated comprehensively for both quantitative and qualitative metrics. The results show that the spin-based compressor decreases the power consumption about 7X compared to the best state-of-the-art design. Also, the application simulations using the multiplier implemented by the proposed compressor indicate the acceptable results.
41
Lim, Kaeun, Jinhyun Kim, Eunsu Kim, and Youngmin Kim. "Enhanced Dual Carry Approximate Adder with Error Reduction Unit for High-Performance Multiplier and In-Memory Computing." Electronics 14, no. 9 (2025): 1702. https://doi.org/10.3390/electronics14091702.
Full textAbstract:
The Dual Carry Approximate Adder (DCAA) is proposed as an advanced 8-bit approximate adder featuring dual carry-out and carry-in full adders (FAs) along with an Error Reduction Unit (ERU) to enhance accuracy. The 8-bit adder is partitioned into upper and lower 4-bit blocks, connected via a dual carry-out full adder and a dual carry-in full adder. To minimize impact on the critical path, an ERU is designed for efficient error correction. Four variants of the DCAA are provided, allowing users to select the most suitable design based on their specific power, area, and accuracy requirements. The DCAA achieves a 78% reduction in Mean Error Distance (MED) while maintaining high computational speed and efficiency. When applied to Wallace Tree multipliers, it reduces delay by 32% compared to ripple carry adders (RCAs), and in in-memory computing (IMC) architectures, it significantly improves accuracy with minimal delay overhead. Experimental results demonstrate that the DCAA offers a well-balanced trade-off between accuracy, speed, and resource efficiency, making it suitable for high-performance, error-tolerant applications. Compared to existing approximate adders, DCAA exhibits superior error correction capabilities while achieving significantly lower delay. Furthermore, its efficient hardware implementation enables seamless integration into various computing paradigms, including AI accelerators and neuromorphic processors. Additionally, the scalability of the design allows for flexible adaptation to different bit-widths, making it a versatile solution for next-generation computing architectures.
42
Manikantta Reddy, K., M. H. Vasantha, Y. B. Nithin Kumar, Ch Keshava Gopal, and Devesh Dwivedi. "Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications." Integration 81 (November 2021): 268–79. http://dx.doi.org/10.1016/j.vlsi.2021.08.001.
Full text
43
Stella, K., T. Vinith, K. Sriram, and P. Vignesh. "A Reliable Low Power Multiplier Using Fixed Width Scalable Approximation." Journal of Physics: Conference Series 2070, no. 1 (2021): 012135. http://dx.doi.org/10.1088/1742-6596/2070/1/012135.
Full textAbstract:
Abstract Recent Approximate computing is a change in perspective in energy-effective frameworks plan and activity, in light of the possibility that we are upsetting PC frameworks effectiveness by requesting a lot of precision from them. Curiously, enormous number of utilization areas, like DSP, insights, and AI. Surmised figuring is appropriate for proficient information handling and mistake strong applications, for example, sign and picture preparing, PC vision, AI, information mining and so forth Inexact registering circuits are considered as a promising answer for lessen the force utilization in inserted information preparing. This paper proposes a FPGA execution for a rough multiplier dependent on specific partial part-based truncation multiplier circuits. The presentation of the proposed multiplier is assessed by contrasting the force utilization, the precision of calculation, and the time delay with those of a rough multiplier dependent on definite calculation introduced. The estimated configuration acquired energy effective mode with satisfactory precision. When contrasted with ordinary direct truncation proposed model fundamentally impacts the presentation. Thusly, this novel energy proficient adjusting based inexact multiplier design outflanked another cutthroat model.
44
Siliveri, Swetha, and Dr N. Siva Sankara Reddy. "Performance Enhancement of CNFET-based Approximate Compressor for Error Resilient Image Processing." International Journal of Electrical and Electronics Research 11, no. 3 (2023): 851–58. http://dx.doi.org/10.37391/ijeer.110332.
Full textAbstract:
The approximate computing has emerged as an appealing approach to minimize energy consumption. By implementing inexact circuits at the transistor level, significant enhancements in various performance metrics such as power consumption, delay, energy, and area can be achieved. Consequently, researchers worldwide have been actively exploring the application of inexact techniques in circuit design. This paper introduces a novel technique for designing low-power digital circuits called extremely low power modified gate diffusion input (ELP-MGDI). This technique combines the principles of Modified Gate Diffusion Input with the utilization of Carbon Nano Tube Field-Effect Transistors (CNTFETs). The Objective of this paper is to enhance the power, delay, and area characteristics of a 4:2 compressor and multiplier by employing ELP-MGDI approach. To achieve this, we conducted thorough analysis and simulations using the Verilog-A simulator 32 nm CNFET technology Stanford University within the Cadence Virtuoso Tool. The results show extremely power, delay reduction and power-delay-product (PDP) of approximate multiplier has been improved by over 99%, and the circuit area has been reduced by 55%. The proposed processing module demonstrates superior performance compared to their conventional counterparts.
45
Salmanpour, Ferdos, Mohammad Hossein Moaiyeri, and Farnaz Sabetzadeh. "Ultra-Compact Imprecise 4:2 Compressor and Multiplier Circuits for Approximate Computing in Deep Nanoscale." Circuits, Systems, and Signal Processing 40, no. 9 (2021): 4633–50. http://dx.doi.org/10.1007/s00034-021-01688-8.
Full text
46
Shao, Botang, and Peng Li. "Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 4 (2015): 1081–90. http://dx.doi.org/10.1109/tcsi.2015.2388839.
Full text
47
S, Mrs Saranya. "Synthesis and Performance Characterization of a Pipelined 32-Bit Vedic Multiplier for High-Speed Digital Systems." INTERNATIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 05 (2025): 1–9. https://doi.org/10.55041/ijsrem46909.
Full textAbstract:
Abstract— This paper introduces a high speed, area and power efficient approximation method for 32 bit arithmetic operations with a Vedic multiplier and parallel prefix adder (PPA). Vedic multiplication methods are highly recognized for their high-speed calculations, while parallel prefix adders offer lower latency in addition. By combining both methods, we introduced an optimized hardware architecture that offers lower area overhead without compromising computational efficiency. The proposed 32- bit arithmetic unit employing the Urdhva-Tiryagbhyam technique, multiplication is executed with reduced delay, while the PPA significantly enhances addition by minimizing carry propagation time. The given design is synthesized and compared in terms of area, delay, and power. Index Terms— Vedic Multiplier, Parallel Prefix Adder, Approximate Computing, Arithmetic Operations, Area Efficiency
48
Aswathy, E. R. Assistant Professor Department of Electronics &. Communication Engineering Vidya Academy of Science &. Technology India, and S. Swapna Kumar Head of the Department Department of Electronics &. Communication Engineering Vidya Academy of Science &. Technology India Dr. "Highly efficient 4:2 compressor using carry based approximate full adder on digital circuit design." Scienxt Journal of Recent Trends in VLSI Design 2, no. 1 (2024): 1–15. https://doi.org/10.5281/zenodo.13637847.
Full textAbstract:
The 4:2 compressors have been widely used in multiplier realizations. For rapiddigital arithmetic integrated circuits, we suggest a very efficient 4:2 compressorcircuit. Four: 2 compressor circuits were built using a carry-based approximationfull adder. In error-tolerant applications where precise processing units are notalways essential, approximate computing can decrease design complexity whileenhancing performance and power efficiency. They can be substituted with theirapproximate counterparts. A new design technique for carrying-basedapproximation of full adders has been modified to include variable probabilityterms. Most multimedia programs can glean useful information from slightlyerroneous results. As a result, we do not need to generate precise results. This shortintroduces a novel gate level logic modification technique for approximating a fulladder in order to take advantage of the relaxation of numerical exactness. Forreducing the area, the sum term is changing to recommend the carry-basedapproximation adder (CBAA) instead of the considerable XOR operation in thetypical full adder. The power consumption, area, and delay of the suggested 4:2compressor circuit were compared to previously reported circuits, and the proposedcircuit was found to have the lowest power consumption, least area, and least delay.It is recommended to employ a Proposed Compressor to increase efficiency whiledecreasing error rate. VHDL circuit construction is simulated by using Xilinx ISE14.7.
49
Devloo, Philippe R. B., Agnaldo M. Farias, Sônia M. Gomes, Weslley Pereira, Antonio J. B. dos Santos, and Frédéric Valentin. "New H(div)-conforming multiscale hybrid-mixed methods for the elasticity problem on polygonal meshes." ESAIM: Mathematical Modelling and Numerical Analysis 55, no. 3 (2021): 1005–37. http://dx.doi.org/10.1051/m2an/2021013.
Full textAbstract:
This work proposes a family of multiscale hybrid-mixed methods for the two-dimensional linear elasticity problem on general polygonal meshes. The new methods approximate displacement, stress, and rotation using two-scale discretizations. The first scale level setting consists of approximating the traction variable (Lagrange multiplier) in discontinuous polynomial spaces, and of computing elementwise rigid body modes. In the second level, the methods are made effective by solving completely independent local boundary Neumann elasticity problems written in a mixed form with weak symmetry enforced via the rotation multiplier. Since the finite-dimensional space for the traction variable constraints the local stress approximations, the discrete stress field lies in the H(div) space globally and stays in local equilibrium with external forces. We propose different choices to approximate local problems based on pairs of finite element spaces defined on affine second-level meshes. Those choices generate the family of multiscale finite element methods for which stability and convergence are proved in a unified framework. Notably, we prove that the methods are optimal and high-order convergent in the natural norms. Also, it emerges that the approximate displacement and stress divergence are super-convergent in the L2-norm. Numerical verifications assess theoretical results and highlight the high precision of the new methods on coarse meshes for multilayered heterogeneous material problems.
50
Gopal, Srinivasan, Pawan Agarwal, Joe Baylon, et al. "A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8, no. 3 (2018): 506–18. http://dx.doi.org/10.1109/jetcas.2018.2852624.
Full text