Relevant bibliographies by topics / Architecture ARM

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Architecture ARM'

Author: Grafiati
Published: 4 June 2021
Last updated: 13 February 2022

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Journal articles on the topic "Architecture ARM"

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Stojev, M. "ARM System Architecture." Microelectronics Journal 29, no. 7 (July 1998): 472. http://dx.doi.org/10.1016/s0026-2692(98)80011-6.

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Jaggar, D. "Arm Architecture And Systems." IEEE Micro 17, no. 4 (July 1997): 9–11. http://dx.doi.org/10.1109/mm.1997.612174.

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Peterson, Steven L., and Ghazi M. Rayan. "Shoulder and Upper Arm Muscle Architecture." Journal of Hand Surgery 36, no. 5 (May 2011): 881–89. http://dx.doi.org/10.1016/j.jhsa.2011.01.008.

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Dall, Christoffer, Shih-Wei Li, Jin Tack Lim, and Jason Nieh. "ARM Virtualization." ACM SIGOPS Operating Systems Review 52, no. 1 (August 28, 2018): 45–56. http://dx.doi.org/10.1145/3273982.3273987.

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Katbab, A. "A multiprocessor architecture for robot-arm control." Microprocessing and Microprogramming 24, no. 1-5 (August 1988): 673–80. http://dx.doi.org/10.1016/0165-6074(88)90128-7.

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Penneman, Niels, Danielius Kudinskas, Alasdair Rawsthorne, Bjorn De Sutter, and Koen De Bosschere. "Formal virtualization requirements for the ARM architecture." Journal of Systems Architecture 59, no. 3 (March 2013): 144–54. http://dx.doi.org/10.1016/j.sysarc.2013.02.003.

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Goodacre, J., and A. N. Sloss. "Parallelism and the ARM instruction set architecture." Computer 38, no. 7 (July 2005): 42–50. http://dx.doi.org/10.1109/mc.2005.239.

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KIM, D. H. "Addressing Mode Extension to the ARM/Thumb Architecture." Advances in Electrical and Computer Engineering 14, no. 2 (2014): 85–88. http://dx.doi.org/10.4316/aece.2014.02014.

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Wang, Ding. "Embedded Arm Control Architecture for Remote PID Controller." Advanced Materials Research 816-817 (September 2013): 394–97. http://dx.doi.org/10.4028/www.scientific.net/amr.816-817.394.

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The remote control of controller is a main trend of development for control system. The lots of work in them all mainly regards internet as the base of frames in the network. There are many levels of technologies for the remote control of controller. Its implements are important technologies among these levels. So, a remote PID controller is completed physically using ARM-based microprocessors. In this paper, how it is built is proposed. The realizations of the control algorithms are focused on specially. The physical prototype was implemented and proved that Embedded ARM control architecture for remote PID controller is correct and effective.
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Wu, Jing, Huapeng Wu, Yuntao Song, Ming Li, Yang Yang, and Daniel A. M. Alcina. "Open software architecture for east articulated maintenance arm." Fusion Engineering and Design 109-111 (November 2016): 474–79. http://dx.doi.org/10.1016/j.fusengdes.2016.02.074.

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Dissertations / Theses on the topic "Architecture ARM"

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Hildingson, Malte. "Porting an interpreter and just-in-time compiler to the XScale architecture." Thesis, University West, Department of Informatics and Mathematics, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:hv:diva-547.

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Carter, Adrian D. "The Light Within: A Graduate Architecture School in Roanoke, Virginia." Thesis, Virginia Tech, 2013. http://hdl.handle.net/10919/23727.

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In urban conditions architecture often loses a connection with the surrounding context and viewers through inappropriate scale, design orientation and the misuse of light during the day and night. In areas of density, perception is everything. This exploration seeks to express architecture as a language of light and transparency by emphasizing a long linear connection with the ground plane and surrounding city. This creates horizontal bands of space that emit and receive various forms of light. The goal of this thesis is to portray itself as a glowing beacon of attraction while simultaneously displaying its inner workings.
Master of Architecture
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Oliveira, Daniel Alfonso Gonçalves de. "Energy consumption and performance of HPC architecture for Exascale." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/105048.

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Uma das principais preocupações para construir a próxima geração de sistemas PAD é o consumo de energia. Para quebrar a barreira de exascale a comunidade científica precisa investigar alternativas que possam lidar com o problema de consumo de energia. Sistemas PAD atuais não se preocupam com energia e já consomem GigaWatts. Requisitos de consumo de energia restringirão fortemente sistemas futuros. Nesse contexto processadores de alta potência abrem espaço para novas arquiteturas. Duas arquiteturas surgem no contexto de PAD. A primeira arquitetura são as unidades de processamento gráfico (GPU), GPUs possuem vários núcleos de processamento, suportando milhares de threads simultâneas, se adaptando bem a aplicações massivamente paralelas. Hoje alguns dos melhores sistemas PAD possuem GPUs que demonstram um alto desempenho por um baixo consumo de energia para várias aplicações paralelas. A segunda arquitetura são os processadores de baixo consumo, processadores ARM estão melhorando seu desempenho e mantendo o menor consumo de energia possível. Como exemplo desse ganho, projetos como Mont-Blanc apostam no uso de ARM para construir um sistema PAD energeticamente eficiente. Este trabalho visa verificar o potencial dessas arquiteturas emergentes. Avaliamos essas arquiteturas e comparamos com a arquitetura mais comum encontrada nos sistemas PAD atuais. O principal objetivo é analisar o consumo de energia e o desempenho dessas arquiteturas no contexto de sistemas PAD. Portanto, benchmarks heterogêneos foram executados em todas as arquiteturas. Os resultados mostram que a arquitetura de GPU foi a mais rápida e a melhor em termos de consumo de energia. GPU foi pelo menos 5 vezes mais rápida e consumiu 18 vezes menos energia considerando todos os benchmarks testados. Também observamos que processadores de alta potência foram mais rápidos e consumiram menos energia, para tarefas com uma carga de trabalho leve, do que comparado com processadores de baixo consumo. Entretanto, para tarefas com carga de trabalho leve processadores de baixo consumo apresentaram um consumo de energia melhor. Concluímos que sistemas heterogêneos combinando GPUs e processadores de baixo consumo podem ser uma solução interessante para alcançar um eficiência energética superior. Apesar de processadores de baixo consumo apresentarem um pior consumo de energia para cargas de trabalho pesadas. O consumo de energia extremamente baixo durante o processamento é inferior ao consumo ocioso das demais arquiteturas. Portanto, combinando processadores de baixo consumo para gerenciar GPUs pode resultar em uma eficiência energética superior a sistemas que combinam processadores de alta potência com GPUs.
One of the main concerns to build the new generation of High Performance Computing (HPC) systems is energy consumption. To break the exascale barrier, the scientific community needs to investigate alternatives that cope with energy consumption. Current HPC systems are power hungry and are already consuming Megawatts of energy. Future exascale systems will be strongly constrained by their energy consumption requirements. Therefore, general purpose high power processors could be replaced by new architectures in HPC design. Two architectures emerge in the HPC context. The first architecture uses Graphic Processing Units (GPU). GPUs have many processing cores, supporting simultaneous execution of thousands of threads, adapting well to massively parallel applications. Today, top ranked HPC systems feature many GPUs, which present high processing speed at low energy consumption budget with various parallel applications. The second architecture uses Low Power Processors, such as ARM processors. They are improving the performance, while still aiming to keep the power consumption as low as possible. As an example of this performance gain, projects like Mont-Blanc bet on ARM to build energy efficient HPC systems. This work aims to verify the potential of these emerging architectures. We evaluate these architectures and compare them to the current most common HPC architecture, high power processors such as Intel. The main goal is to analyze the energy consumption and performance of these architectures in the HPC context. Therefore, heterogeneous HPC benchmarks were executed in the architectures. The results show that the GPU architecture is the fastest and the best in terms of energy efficiency. GPUs were at least 5 times faster while consuming 18 times less energy for all tested benchmarks. We also observed that high power processors are faster than low power processors and consume less energy for heavy-weight workloads. However, for light-weight workloads, low power processors presented a better energy efficiency. We conclude that heterogeneous systems combining GPUs and low power processors can be an interesting solution to achieve greater energy efficiency, although low power processors presented a worse energy efficiency for HPC workloads. Their extremely low power consumption during the processing of an application is less than the idle power of the other architectures. Therefore, combining low power processors with GPUs could result in an overall energy efficiency greater than high power processors combined with GPUs.
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Buchanan, Christopher R. "Structural architecture and evolution of the Humber Arm Allochthon, Frenchman's Cove - York Harbour, Bay of Islands, Newfoundland /." Internet access available to MUN users only, 2004. http://collections.mun.ca/u?/theses,110605.

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Sheen, Sean Kai. "Astro - A Low-Cost, Low-Power Cluster for CPU-GPU Hybrid Computing using the Jetson TK1." DigitalCommons@CalPoly, 2016. https://digitalcommons.calpoly.edu/theses/1567.

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With the rising costs of large scale distributed systems many researchers have began looking at utilizing low power architectures for clusters. In this paper, we describe our Astro cluster, which consists of 46 NVIDIA Jetson TK1 nodes each equipped with an ARM Cortex A15 CPU, 192 core Kepler GPU, 2 GB of RAM, and 16 GB of flash storage. The cluster has a number of advantages when compared to conventional clusters including lower power usage, ambient cooling, shared memory between the CPU and GPU, and affordability. The cluster is built using commodity hardware and can be setup for relatively low costs while providing up to 190 single precision GFLOPS of computing power per node due to its combined GPU/CPU architecture. The cluster currently uses one 48-port Gigabit Ethernet switch and runs Linux for Tegra, a modified version of Ubuntu provided by NVIDIA as its operating system. Common file systems such as PVFS, Ceph, and NFS are supported by the cluster and benchmarks such as HPL, LAPACK, and LAMMPS are used to evaluate the system. At peak performance, the cluster is able to produce 328 GFLOPS of double precision and a peak of 810W using the LINPACK benchmark placing the cluster at 324th place on the Green500. Single precision benchmarks result in a peak performance of 6800 GFLOPs. The Astro cluster aims to be a proof-of-concept for future low power clusters that utilize a similar architecture. The cluster is installed with many of the same applications used by top supercomputers and is validated using the several standard supercomputing benchmarks. We show that with the rise of low-power CPUs and GPUs, and the need for lower server costs, this cluster provides insight into how ARM and CPU-GPU hybrid chips will perform in high-performance computing.
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Asay, Isaac. "Compacting Loads and Stores for Code Size Reduction." DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1164.

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It is important for compilers to generate executable code that is as small as possible, particularly when generating code for embedded systems. One method of reducing code size is to use instruction set architectures (ISAs) that support combining multiple operations into single operations. The ARM ISA allows for combining multiple memory operations to contiguous memory addresses into a single operation. The LLVM compiler contains a specific memory optimization to perform this combining of memory operations, called ARMLoadStoreOpt. This optimization, however, relies on another optimization (ARMPreAllocLoadStoreOpt) to move eligible memory operations into proximity in order to perform properly. This mover optimization occurs before register allocation, while ARMLoadStoreOpt occurs after register allocation. This thesis implements a similar mover optimization (called MagnetPass) after register allocation is performed, and compares this implementation with the existing optimization. While in most cases the two optimizations provide comparable results, our implementation in its current state requires some improvements before it will be a viable alternative to the existing optimization. Specifically, the algorithm will need to be modified to reduce computational complexity, and our implementation will need to take care not to interfere with other LLVM optimizations.
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Verbryke, Matthew R. "Preliminary Implementation of a Modular Control System for Dual-Arm Manipulation with a Humanoid Robot." University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1543838768677697.

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Zhang, Zimo. "Effect Of Chain End Functional And Chain Architecture On Surface Segregation." University of Akron / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=akron1498513871263316.

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Freire, Luciano Ondir. "Desenvolvimento de uma arquitetura de controle descentralizada para veículos submarinos baseada em CAN, ARM e Engenharia de Sistemas- CANARMES." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3152/tde-09072014-103454/.

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Os veículos submarinos não tripulados tem uma importância crescente devido à sua flexibilidade e baixo custo. Devido à sua complexidade intrínseca, eles requerem diversas competências diferentes para serem desenvolvidos e permitem realizar pesquisas em vários campos do conhecimento. No contexto de uma universidade, que possui pessoal heterogêneo e de alta rotatividade, faz-se mister adotar uma organização que permita que os esforços de cada aluno possam ser reusados pelos outros, de modo as atividades de pesquisa possam avançar com pouca perda de tempo e retrabalho. Tal necessidade pode ser respondida pela aplicação de conceitos da engenharia de sistemas, tais como modularidade, separação formal entre soluções tecnológicas e necessidades, classificação funcional, critérios para escolha do método de desenvolvimento, uso de referencial normativo técnico, plano tecnológico, integração, verificação e validação e gerenciamento de configurações. Este trabalho se limita a desenvolver uma arquitetura de controle, observando os conceitos de engenharia de sistemas, aplicada a um AUV. É feita uma comparação com outras arquiteturas similares do estado da arte e mostram-se resultados de testes em piscina para esta arquitetura. É mostrado também que foi possível estabelecer a continuidade do desenvolvimento por outros alunos, validando a utilidade da metodologia. Conclui-se que, para aumentar a eficiência da pesquisa universitária, é necessário observar aspectos gerenciais e institucionais além dos aspectos técnicos ao conceber soluções técnicas.
The unmanned underwater vehicles have a growing position due to their flexibility and low cost. Due to their inherent complexity, they require many different skills to be developed and they allow conducting research in various fields of knowledge. In the context of a university, which has heterogeneous staff and high turnover, there is the need of adopting an organization that allows the efforts of each student be reused by others, so research activities can proceed with little loss of time and rework. This need can be answered by the application of system engineering concepts such as modularity, formal separation between technology solutions and needs, functional classification, criteria for the choice of development method, use of technical reference standard, technological plan, integration, verification and validation and configuration management. This work is limited to development of a control architecture, observing the concepts of systems engineering, applied to an AUV. A comparison is made with other similar architectures in the state of the art and shows up test results in the pool for this architecture. It is also shown that it was possible to keep the development by other students, validating the utility of the methodology. It is concluded that in order to increase the efficiency of university research, it must be observed managerial and institutional aspects beyond the technical aspects when designing technical solutions.
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Serman, François. "Reducing hardware TCB in favor of certifiable virtual machine monitor." Thesis, Lille 1, 2016. http://www.theses.fr/2016LIL10189/document.

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Cette thèse a pour objet la conception d'un hyperviseur logiciel sécurisé, à vocation de certification. Les plus hauts niveaux de certification requièrent l'usage de méthodes formelles, permettant de démontrer la validité d'un produit par rapport à une spécification à l'aide de la logique mathématique. Le matériel prouvé n'existant pas, les mécanismes d'hypervision sont implémentés en logiciel. Cela contribue à réduire la base de confiance, et donc la quantité de modélisation et de preuve à produire. En outre, cela rend possible la virtualisation de systèmes sur des plateformes qui ne sont pas dotées d'instructions de virtualisation. Les principaux challenges sont l'analyse du jeu d'instruction qui, malgré l'existence de documentation, comporte des ambiguïtés, des particularités dépendantes de l'implémentation et des comportements non définis. Puis, l'identification des intensions d'un système invité étant donné un flot d'instructions discret afin de rester en interposition avec le matériel sous-jacent. Pour ce faire, le code machine de l'invité est analysé et les instructions menaçant l'intégrité ou la confidentialité du système sont remplacées par des trapes logicielles, provoquant une analyse du contexte afin d'autoriser ou non leur exécution. Reposant sur l'existence d'un CPU et d'une MMU prouvés, seul du code privilégié est susceptible d'outrepasser les droits d'accès configurés par l'hyperviseur. Il n'est donc pas nécessaire d'hyperviser le code non privilégié. Les micro-noyau, généralement choisis pour leur légèreté, ont donc un second avantage : ils réduisent au minimum le surcoût de l’hypervision
This thesis presents the design of a secured, software based hypervisor for certification purposes. The highest levels of certification require formal methods, which demonstrate the correctness of a product with regard to its specification using mathematical logic. Proven hardware is not available off-the-shelf. In order to reduce the Trusted Computing Base (TCB) and hence, the amount of specification and proofs to produce, virtualization mechanism are software-made. In addition, this enables virtualization on platforms which do not have virtualization-enabled hardware. The challenge for achieving this goal is twofold. On one hand, despite an existing documentation, the instruction set to be analysed has tedious corner cases, implementation-dependant behaviour or even worse, undefined behaviour. On the other hand to infer the system behaviors has to be infered given a discrete instruction flow, in order to remain interposed between the guest and the underlying hardware. For achieving this, the guest's machine code is analysed, and sensitive instructions (which threaten confidentiality or integrity) are replaced by traps, which enable arbitration given the actual guest context. Relying on hypothetically proven processor and memory management unit, only privileged code may bypass the configuration setup by the hypervisor and access the hardware. Thus, analysing unprivileged code is worthless in this case. Micro-kernel design which tends to offload most of the code in userspace, are suitable here. Using that paradigm reduces the overhead induced by certified virtualization
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Books on the topic "Architecture ARM"

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ARM system architecture. Harlow, England: Addison-Wesley, 1996.

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ARM system-on-chip architecture. New York: Addison-Wesley, 2000.

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Istendael, Geert van. Arm Brussel. Amsterdam: Atlas, 1992.

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Han, Janselijn, ed. Architectuur en verbeelding =: Architecture and imagination. Zwolle: Waanders, 1989.

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Il'vickaya, Svetlana. Architectural comparative aspect of Orthodox monasteries in the Balkan countries and Russia. ru: INFRA-M Academic Publishing LLC., 2020. http://dx.doi.org/10.12737/1039637.

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The monograph is devoted to the concept of comparative (comparative) architecture is a modern approach to the study and analysis of Orthodox architecture. Reveals and architectural comparative aspect of monastic ensembles and churches — the main sources of Orthodoxy in the Balkan countries and Russia, the keepers of the architectural and artistic values and are centers for religious education in modern society. For the first time the regularities of formation of architecture of Orthodox monasteries and built a comparative model of their organization. For students, postgraduates and lecturers of architectural faculties of universities, architects, designers, and also for a wide range of readers interested in the problems of Orthodox cult architecture.
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Peter, Haiko, Krimmel Bernd, and Ulmer Renate, eds. Architecture. New York: Rizzoli, 1988.

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Natural architecture. New York: Princeton Architectural Press, 2007.

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A, Papadakēs, ed. Poetic architecture. London: New Architecture Group, 2005.

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Mathieu, Caroline. Orsay: Architecture. Paris: Editions Scala, 2003.

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1952-, Knevitt Charles, ed. Community architecture: How people are creating their own environment. London: Penguin, 1987.

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Book chapters on the topic "Architecture ARM"

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Zawidzki, Machi. "Arm-Z." In Discrete Optimization in Architecture, 31–35. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-1109-2_4.

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Wang, K. C. "ARM Architecture and Programming." In Embedded and Real-Time Operating Systems, 7–46. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-51517-5_2.

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Kusswurm, Daniel. "Armv8-32 Architecture." In Modern Arm Assembly Language Programming, 1–11. Berkeley, CA: Apress, 2020. http://dx.doi.org/10.1007/978-1-4842-6267-2_1.

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Kusswurm, Daniel. "Armv8-64 Architecture." In Modern Arm Assembly Language Programming, 215–22. Berkeley, CA: Apress, 2020. http://dx.doi.org/10.1007/978-1-4842-6267-2_10.

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Coelho, Bruno, Fernando Costa, and Gil M. Gonçalves. "ARM: Architecture for Recruitment Matchmaking." In E-Business and Telecommunications, 81–99. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-30222-5_4.

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Kusswurm, Daniel. "Armv8-32 SIMD Architecture." In Modern Arm Assembly Language Programming, 131–40. Berkeley, CA: Apress, 2020. http://dx.doi.org/10.1007/978-1-4842-6267-2_7.

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Kusswurm, Daniel. "Armv8-32 Floating-Point Architecture." In Modern Arm Assembly Language Programming, 91–99. Berkeley, CA: Apress, 2020. http://dx.doi.org/10.1007/978-1-4842-6267-2_5.

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Kumar, Pratik, Nagendra Chowdary, and Anish Mathuria. "Alphanumeric Shellcode Generator for ARM Architecture." In Security, Privacy, and Applied Cryptography Engineering, 38–39. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-41224-0_3.

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Ermakov, Mikhail. "Static Binary Code Instrumentation for ARM Architecture." In Lecture Notes in Computer Science, 105–16. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-74313-4_9.

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Elahi, Ata, and Trevor Arjeski. "Logic Gates and Introduction to Computer Architecture." In ARM Assembly Language with Hardware Experiments, 17–34. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-11704-1_2.

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Conference papers on the topic "Architecture ARM"

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Jeff, Brian. "Big.LITTLE system architecture from ARM." In the 49th Annual Design Automation Conference. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2228360.2228569.

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Pinto, S., A. Oliveira, J. Pereira, J. Cabral, J. Monteiro, and A. Tavares. "Lightweight multicore virtualization architecture exploiting ARM TrustZone." In IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society. IEEE, 2017. http://dx.doi.org/10.1109/iecon.2017.8216603.

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Dall, Christoffer, Shih-Wei Li, Jin Tack Lim, Jason Nieh, and Georgios Koloventzos. "ARM Virtualization: Performance and Architectural Implications." In 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). IEEE, 2016. http://dx.doi.org/10.1109/isca.2016.35.

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Mahalingam, P. R., and Shimmi Asokan. "A framework for optimizing GCC for ARM architecture." In the International Conference. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2345396.2345452.

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Payandeh, S., and A. Goldenberg. "A control architecture for arm/hand manipulating system." In Fifth International Conference on Advanced Robotics 'Robots in Unstructured Environments. IEEE, 1991. http://dx.doi.org/10.1109/icar.1991.240435.

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Suzuki, Akihiro, and Shuichi Oikawa. "Implementation of Virtual Machine Monitor for ARM Architecture." In 2010 IEEE 10th International Conference on Computer and Information Technology (CIT). IEEE, 2010. http://dx.doi.org/10.1109/cit.2010.387.

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De Moura, Rodrigo C., Giovane O. Torres, Mauricio L. Pilla, Laercio L. Pilla, Amarildo T. Da Costa, and Felipe M. G. Franca. "Value Reuse Potential in ARM Architectures." In 2016 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). IEEE, 2016. http://dx.doi.org/10.1109/sbac-pad.2016.30.

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Tian, Yaqin, Dan Meng, and Xiaoyi Lin. "The lightweight design of the support arm." In Proceedings of the International Conference on Civil, Architecture and Environmental Engineering (ICCAE2016). CRC Press/Balkema P.O. Box 11320, 2301 EH Leiden, The Netherlands: CRC Press/Balkema, 2017. http://dx.doi.org/10.1201/9781315116259-142.

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Pinto, S., D. Oliveira, J. Pereira, N. Cardoso, M. Ekpanyapong, J. Cabral, and A. Tavares. "Towards a lightweight embedded virtualization architecture exploiting ARM TrustZone." In 2014 IEEE Emerging Technology and Factory Automation (ETFA). IEEE, 2014. http://dx.doi.org/10.1109/etfa.2014.7005255.

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Suzuki, A., and S. Oikawa. "SIVARM: A Virtual Machine Monitor for the ARM architecture." In 2010 IEEE Region 10 Conference (TENCON 2010). IEEE, 2010. http://dx.doi.org/10.1109/tencon.2010.5686426.

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Reports on the topic "Architecture ARM"

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Laros, James H.,, Kevin Pedretti, Simon David Hammond, Michael J. Aguilar, Matthew Leon Curry, Ryan Grant, Robert J. Hoekstra, et al. FY18 L2 Milestone #6360 Report: Initial Capability of an Arm-based Advanced Architecture Prototype System and Software Environment. Office of Scientific and Technical Information (OSTI), September 2018. http://dx.doi.org/10.2172/1493831.

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Laros, James H.,, Kevin Pedretti, Simon David Hammond, Michael J. Aguilar, Matthew Leon Curry, Ryan Grant, Robert J. Hoekstra, et al. FY18 L2 Milestone #8759 Report: Vanguard Astra and ATSE ? an ARM-based Advanced Architecture Prototype System and Software Environment. Office of Scientific and Technical Information (OSTI), September 2018. http://dx.doi.org/10.2172/1470822.

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Qi, Fei, Zhaohui Xia, Gaoyang Tang, Hang Yang, Yu Song, Guangrui Qian, Xiong An, Chunhuan Lin, and Guangming Shi. A Graph-based Evolutionary Algorithm for Automated Machine Learning. Web of Open Science, December 2020. http://dx.doi.org/10.37686/ser.v1i2.77.

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Abstract:
As an emerging field, Automated Machine Learning (AutoML) aims to reduce or eliminate manual operations that require expertise in machine learning. In this paper, a graph-based architecture is employed to represent flexible combinations of ML models, which provides a large searching space compared to tree-based and stacking-based architectures. Based on this, an evolutionary algorithm is proposed to search for the best architecture, where the mutation and heredity operators are the key for architecture evolution. With Bayesian hyper-parameter optimization, the proposed approach can automate the workflow of machine learning. On the PMLB dataset, the proposed approach shows the state-of-the-art performance compared with TPOT, Autostacker, and auto-sklearn. Some of the optimized models are with complex structures which are difficult to obtain in manual design.
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Nord, Robert L., John Bergey, Jr Blanchette, Klein Stephen, and Mark. Impact of Army Architecture Evaluations. Fort Belvoir, VA: Defense Technical Information Center, April 2009. http://dx.doi.org/10.21236/ada512398.

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Thomason, L. S., Robert Weber, and John Kohler. Architecture Reporting and Monitoring System (ARMS). Fort Belvoir, VA: Defense Technical Information Center, September 1995. http://dx.doi.org/10.21236/ada327623.

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Reddy, Prameela V., and Charles G. Schroeder. Data Warehouse Architecture for Army Installations. Fort Belvoir, VA: Defense Technical Information Center, November 1999. http://dx.doi.org/10.21236/ada371882.

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Lenahan, Jack. Are Service Oriented Architectures the Only Valid Architectural Approach for the Transformation to Network Centric Warfare? (Briefing Charts). Fort Belvoir, VA: Defense Technical Information Center, June 2004. http://dx.doi.org/10.21236/ada462299.

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Katsube, Y., K. Nagami, and H. Esaki. Toshiba's Router Architecture Extensions for ATM : Overview. RFC Editor, February 1997. http://dx.doi.org/10.17487/rfc2098.

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Dattathreya, Macam S. Open Network Architecture for Army Vehicle Electronics. Fort Belvoir, VA: Defense Technical Information Center, December 2009. http://dx.doi.org/10.21236/ada513205.

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Chen, H., R. Tsang, J. Brandt, and J. Hutchins. A survey of IP over ATM architectures. Office of Scientific and Technical Information (OSTI), July 1997. http://dx.doi.org/10.2172/554171.

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