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Journal articles on the topic 'Architecture ARM'

Author: Grafiati
Published: 4 June 2021
Last updated: 13 February 2022

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1

Stojev, M. "ARM System Architecture." Microelectronics Journal 29, no. 7 (July 1998): 472. http://dx.doi.org/10.1016/s0026-2692(98)80011-6.

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2

Jaggar, D. "Arm Architecture And Systems." IEEE Micro 17, no. 4 (July 1997): 9–11. http://dx.doi.org/10.1109/mm.1997.612174.

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3

Peterson, Steven L., and Ghazi M. Rayan. "Shoulder and Upper Arm Muscle Architecture." Journal of Hand Surgery 36, no. 5 (May 2011): 881–89. http://dx.doi.org/10.1016/j.jhsa.2011.01.008.

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4

Dall, Christoffer, Shih-Wei Li, Jin Tack Lim, and Jason Nieh. "ARM Virtualization." ACM SIGOPS Operating Systems Review 52, no. 1 (August 28, 2018): 45–56. http://dx.doi.org/10.1145/3273982.3273987.

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5

Katbab, A. "A multiprocessor architecture for robot-arm control." Microprocessing and Microprogramming 24, no. 1-5 (August 1988): 673–80. http://dx.doi.org/10.1016/0165-6074(88)90128-7.

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6

Penneman, Niels, Danielius Kudinskas, Alasdair Rawsthorne, Bjorn De Sutter, and Koen De Bosschere. "Formal virtualization requirements for the ARM architecture." Journal of Systems Architecture 59, no. 3 (March 2013): 144–54. http://dx.doi.org/10.1016/j.sysarc.2013.02.003.

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7

Goodacre, J., and A. N. Sloss. "Parallelism and the ARM instruction set architecture." Computer 38, no. 7 (July 2005): 42–50. http://dx.doi.org/10.1109/mc.2005.239.

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8

KIM, D. H. "Addressing Mode Extension to the ARM/Thumb Architecture." Advances in Electrical and Computer Engineering 14, no. 2 (2014): 85–88. http://dx.doi.org/10.4316/aece.2014.02014.

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9

Wang, Ding. "Embedded Arm Control Architecture for Remote PID Controller." Advanced Materials Research 816-817 (September 2013): 394–97. http://dx.doi.org/10.4028/www.scientific.net/amr.816-817.394.

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The remote control of controller is a main trend of development for control system. The lots of work in them all mainly regards internet as the base of frames in the network. There are many levels of technologies for the remote control of controller. Its implements are important technologies among these levels. So, a remote PID controller is completed physically using ARM-based microprocessors. In this paper, how it is built is proposed. The realizations of the control algorithms are focused on specially. The physical prototype was implemented and proved that Embedded ARM control architecture for remote PID controller is correct and effective.
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10

Wu, Jing, Huapeng Wu, Yuntao Song, Ming Li, Yang Yang, and Daniel A. M. Alcina. "Open software architecture for east articulated maintenance arm." Fusion Engineering and Design 109-111 (November 2016): 474–79. http://dx.doi.org/10.1016/j.fusengdes.2016.02.074.

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11

Promberger, Laura, Marco Clemencic, Ben Couturier, Aritz Brosa Iartza, and Niko Neufeld. "Porting the LHCb Stack from x86 (Intel) to aarch64 (ARM) and ppc64le (PowerPC)." EPJ Web of Conferences 214 (2019): 05016. http://dx.doi.org/10.1051/epjconf/201921405016.

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LHCb is undergoing major changes in its data selection and processing chain for the upcoming LHC Run 3 starting in 2021. With this in sight several initiatives have been launched to optimise the software stack. This contribution discusses porting the LHCb Stack from x86_64 architecture to both architectures aarch64 and ppc64le with the goal to evaluate the performance and the cost of the computing infrastructure for the High Level Trigger (HLT). This requires porting a stack with more than five million lines of code and finding working versions of external libraries provided by LCG. Across all software packages the biggest challenge is the growing use of vectorisation - as many vectorisation libraries are specialised on x86 architecture and do not have any support for other architectures. In spite of these challenges we have successfully ported the LHCb High Level Trigger code to aarch64 and ppc64le. This contribution discusses the status and plans for the porting of the software as well as the LHCb approach for tackling code vectorisation in a platform independent way.
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12

Peña-Fernandez, M., A. Lindoso, L. Entrena, M. Garcia-Valderas, S. Philippe, Y. Morilla, and P. Martin-Holgado. "PTM-based hybrid error-detection architecture for ARM microprocessors." Microelectronics Reliability 88-90 (September 2018): 925–30. http://dx.doi.org/10.1016/j.microrel.2018.07.074.

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13

Shen, Bor-Yeh, Wei-Chung Hsu, and Wuu Yang. "A Retargetable Static Binary Translator for the ARM Architecture." ACM Transactions on Architecture and Code Optimization 11, no. 2 (June 2014): 1–25. http://dx.doi.org/10.1145/2629335.

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14

Moore, Ryan W., José A. Baiocchi, Bruce R. Childers, Jack W. Davidson, and Jason D. Hiser. "Addressing the challenges of DBT for the ARM architecture." ACM SIGPLAN Notices 44, no. 7 (June 28, 2009): 147–56. http://dx.doi.org/10.1145/1543136.1542472.

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15

Nikolaidis, I. "ARM system-on-chip architecture, 2nd edition [Book Review]." IEEE Network 14, no. 6 (November 2000): 4. http://dx.doi.org/10.1109/mnet.2000.885658.

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16

King, Stephen M., and Ramila S. Patel-King. "Functional Architecture of the Outer Arm Dynein Conformational Switch." Journal of Biological Chemistry 287, no. 5 (December 7, 2011): 3108–22. http://dx.doi.org/10.1074/jbc.m111.286211.

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17

Kurasawa, Yasuhiro, and Li-yuan Yu-Lee. "PICH and Cotargeted Plk1 Coordinately Maintain Prometaphase Chromosome Arm Architecture." Molecular Biology of the Cell 21, no. 7 (April 2010): 1188–99. http://dx.doi.org/10.1091/mbc.e09-11-0950.

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To maintain genomic stability, chromosome architecture needs to be tightly regulated as chromosomes undergo condensation during prophase and separation during anaphase, but the mechanisms remain poorly understood. Here, we show that the Plk1-binding protein PICH and Plk1 kinase coordinately maintain chromosome architecture during prometaphase. PICH knockdown results in a loss of Plk1 from the chromosome arm and an increase in highly disorganized “wavy” chromosomes that exhibit an “open” or “X-shaped” configuration, consistent with a loss of chromosome arm cohesion. Such chromosome disorganization occurs with essentially no change in the localization of condensin or cohesin on chromosomes. Interestingly, the chromosome disorganization could be prevented by treatment with a topoisomerase II inhibitor ICRF-193, suggesting that the PICH–Plk1 complex normally maintains chromosome architecture in a manner that involves topoisomerase II activity. PICH knockdown does not affect initial chromosome compaction at prophase but causes anaphase DNA bridge formation and failed abscission. Our studies suggest that the PICH–Plk1 complex plays a critical role in maintaining prometaphase chromosome architecture.
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18

Seo, Hwajeong, Hyunjun Kim, Kyungbae Jang, Hyeokdong Kwon, Minjoo Sim, Gyeongju Song, Siwoo Uhm, and Hyunji Kim. "Secure HIGHT Implementation on ARM Processors." Mathematics 9, no. 9 (May 6, 2021): 1044. http://dx.doi.org/10.3390/math9091044.

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Secure and compact designs of HIGHT block cipher on representative ARM microcontrollers are presented in this paper. We present several optimizations for implementations of the HIGHT block cipher, which exploit different parallel approaches, including task parallelism and data parallelism methods, for high-speed and high-throughput implementations. For the efficient parallel implementation of the HIGHT block cipher, the SIMD instructions of ARM architecture are fully utilized. These instructions support four-way 8-bit operations in the parallel way. The length of primitive operations in the HIGHT block cipher is 8-bit-wise in addition–rotation–exclusive-or operations. In the 32-bit word architecture (i.e., the 32-bit ARM architecture), four 8-bit operations are executed at once with the four-way SIMD instruction. By exploiting the SIMD instruction, three parallel HIGHT implementations are presented, including task-parallel, data-parallel, and task/data-parallel implementations. In terms of the secure implementation, we present a fault injection countermeasure for 32-bit ARM microcontrollers. The implementation ensures the fault detection through the representation of intra-instruction redundancy for the data format. In particular, we proposed two fault detection implementations by using parallel implementations. The two-way task/data-parallel based implementation is secure against fault injection models, including chosen bit pair, random bit, and random byte. The alternative four-way data-parallel-based implementation ensures all security features of the aforementioned secure implementations. Moreover, the instruction skip model is also prevented. The implementation of the HIGHT block cipher is further improved by using the constant value of the counter mode of operation. In particular, the 32-bit nonce value is pre-computed and the intermediate result is directly utilized. Finally, the optimized implementation achieved faster execution timing and security features toward the fault attack than previous works.
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19

Beltran, V., A. F. Skarmeta, and P. M. Ruiz. "An ARM-Compliant Architecture for User Privacy in Smart Cities: SMARTIE—Quality by Design in the IoT." Wireless Communications and Mobile Computing 2017 (2017): 1–13. http://dx.doi.org/10.1155/2017/3859836.

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Much has been said about the benefits that the Internet of Things (IoT) will bring to citizens’ life. Countless smart objects will be soon offering autonomous behavior in smart environments by sensing the physical world around us, collecting information about us, and taking proactive actions (many times without our consent) with the ultimate goal of improving our wellness. Without a strong guarantee on user privacy, the IoT may sound scary for many citizens. Indeed, the IoT-Architecture Reference Model (IoT-ARM) is a European effort for promoting IoT quality aspects such as security and privacy. This paper paves the way to the adoption of reference architectures by describing the application of the IoT-ARM within a European-funded project, SMARTIE. The SMARTIE architecture has been designed to empower citizens to take control of their IoT devices and privacy, while guaranteeing scalability for large deployments in smart cities.
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20

Arnaldi, R., A. Baldit, V. Barret, N. Bastid, G. Blanchard, E. Chiavassa, P. Cortese, et al. "The trigger of the ALICE dimuon arm: Architecture and detectors." Nuclear Physics A 661, no. 1-4 (December 1999): 712–15. http://dx.doi.org/10.1016/s0375-9474(99)85124-0.

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21

Nosikov, M. V. "The Architecture of Human-Controlled Arm Manipulator Operator Training System." Bulletin of the South Ural State University. Ser. Computer Technologies, Automatic Control & Radioelectronics 19, no. 2 (2019): 38–53. http://dx.doi.org/10.14529/ctcr190204.

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22

Zhang, Jianghan, and Shengbing Che. "Key Technologies of Phone Storage Forensics Based on ARM Architecture." IOP Conference Series: Materials Science and Engineering 322 (March 2018): 052008. http://dx.doi.org/10.1088/1757-899x/322/5/052008.

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23

Kikuchi, Yasuhiro. "Comparative Analysis of Muscle Architecture in Primate Arm and Forearm." Anatomia, Histologia, Embryologia 39, no. 2 (April 2010): 93–106. http://dx.doi.org/10.1111/j.1439-0264.2009.00986.x.

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24

Kartik, S. Vijay, Ben Couturier, Marco Clemencic, and Niko Neufeld. "Measurements of the LHCb software stack on the ARM architecture." Journal of Physics: Conference Series 513, no. 5 (June 11, 2014): 052014. http://dx.doi.org/10.1088/1742-6596/513/5/052014.

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25

Tarn, T. J., A. K. Bejczy, Ning Xi, and A. K. Ramadorai. "Distributed control architecture for a sensor-driven dual arm system." Mechatronics 4, no. 5 (August 1994): 481–502. http://dx.doi.org/10.1016/0957-4158(94)90012-4.

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26

Gao, Hongwei, Jinguo Liu, Yangmin Li, Kun Hong, and Yang Zhang. "Dual-layer fuzzy control architecture for the CAS rover arm." International Journal of Control, Automation and Systems 13, no. 5 (May 23, 2015): 1262–71. http://dx.doi.org/10.1007/s12555-013-9413-4.

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27

Cheng, Yaosong, Yujiang Bi, Yaodong Cheng, Haibo Li, Wang Lu, and Minxing Zhang. "Porting the EOS from X86 (Intel) to aarch64 (ARM) architecture." EPJ Web of Conferences 251 (2021): 02040. http://dx.doi.org/10.1051/epjconf/202125102040.

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With the advancement of many large HEP experiments, the amount of data that needs to be processed and stored has increased significantly, so we must upgrade computing resources and improve the performance of storage software. This article discusses porting the EOS software from the x86_64 architecture to the aarch64 architecture, with the aim of finding a more cost-effective storage solution. In the process of porting, the biggest challenge is that many dependent packages do not have aarch64 version and need to be compiled by ourselves, and the assembly part of the software code also needs to be adjusted accordingly. Despite these challenges, we have successfully ported the EOS code to the aarch64. This article discusses the current status and plans for the software port as well as performance testing after porting.
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28

Asghar, Muhammad Nabeel. "A Review of ARM Processor Architecture History, Progress and Applications." Journal of Applied and Emerging Sciences 10, no. 2 (December 18, 2020): 171. http://dx.doi.org/10.36785/jaes.102446.

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29

Gmerek, Artur. "Mechanical and hardware architecture of the semi-exoskeleton arm rehabilitation robot." Archive of Mechanical Engineering 60, no. 4 (December 1, 2013): 557–74. http://dx.doi.org/10.2478/meceng-2013-0034.

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Abstract This paper deals with mechanical and hardware design of a robot, used for the rehabilitation of upper extremities. It has been called ARR-1 (Arm Rehabilitation Robot). The robot has a semi-exoskeleton structure. This means that some parts of the robot fit closely to the human arm (an orthosis), but the weight of the construction does not load patient’s body. The device is used for the whole arm rehabilitation, but active joints are only situated in glenohumeral and elbow joints. The robot is electrically actuated
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30

Zhang, Kai. "Intelligent Video Analysis System Based on ARM Cortex." Applied Mechanics and Materials 556-562 (May 2014): 3216–18. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.3216.

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With the development of the society, security monitoring system more and more get people's attention. Article designs the intelligent video analysis technology based on ARM architecture on the basis of Intelligent Video Surveillance, and discusses the application prospect of intelligent video analysis system.
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31

Qu, Bo, and Zhao Zhi Wu. "Design of ARM Based Embedded Operating System Micro Kernel." Applied Mechanics and Materials 347-350 (August 2013): 1799–803. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1799.

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This paper describes the design and implementation of an ARM based embedded operating system micro kernel developed on Linux platform with GNU tool chain in technical details, including the three-layer architecture of the kernel (boot layer, core layer and task layer), multi-task schedule (priority for real-time and round-robin for time-sharing), IRQ handler, SWI handler, system calls, and inter-task communication based on which the micro-kernel architecture is constructed. On the foundation of this micro kernel, more components essential to a practical operating system, such as file system and TCP/IP processing, can be added in order to form a real and practical multi-task micro-kernel embedded operating system.
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32

Qureshi, Yasir Mahmood, William Andrew Simon, Marina Zapater, Katzalin Olcoz, and David Atienza. "Gem5-X." ACM Transactions on Architecture and Code Optimization 18, no. 4 (December 31, 2021): 1–27. http://dx.doi.org/10.1145/3461662.

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The increasing adoption of smart systems in our daily life has led to the development of new applications with varying performance and energy constraints, and suitable computing architectures need to be developed for these new applications. In this article, we present gem5-X, a system-level simulation framework, based on gem-5, for architectural exploration of heterogeneous many-core systems. To demonstrate the capabilities of gem5-X, real-time video analytics is used as a case-study. It is composed of two kernels, namely, video encoding and image classification using convolutional neural networks (CNNs). First, we explore through gem5-X the benefits of latest 3D high bandwidth memory (HBM2) in different architectural configurations. Then, using a two-step exploration methodology, we develop a new optimized clustered-heterogeneous architecture with HBM2 in gem5-X for video analytics application. In this proposed clustered-heterogeneous architecture, ARMv8 in-order cluster with in-cache computing engine executes the video encoding kernel, giving 20% performance and 54% energy benefits compared to baseline ARM in-order and Out-of-Order systems, respectively. Furthermore, thanks to gem5-X, we conclude that ARM Out-of-Order clusters with HBM2 are the best choice to run visual recognition using CNNs, as they outperform DDR4-based system by up to 30% both in terms of performance and energy savings.
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33

Kang, Ji-Hun, and Jae-Cheol Ryou. "A Base Address Analysis Tool for Static Analysis of ARM Architecture-Based Binary." Journal of the Korea Institute of Information Security and Cryptology 26, no. 5 (October 31, 2016): 1185–89. http://dx.doi.org/10.13089/jkiisc.2016.26.5.1185.

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34

PARK, Sejin, Byungsu PARK, Unsung LEE, and Chanik PARK. "Virtualizing Graphics Architecture of Android Mobile Platforms in KVM/ARM Environment." IEICE Transactions on Information and Systems E100.D, no. 7 (2017): 1403–15. http://dx.doi.org/10.1587/transinf.2016edp7435.

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35

Nakauchi, Yasushi, Youichiro Nishida, and Yasuchika Mori. "The Control of Arm Robot by Using Emergent Behavior Based Architecture." Journal of the Robotics Society of Japan 15, no. 6 (1997): 934–42. http://dx.doi.org/10.7210/jrsj.15.934.

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36

Sathish Kumar, Dumpeti. "The Design and Analysis of Char Driver Model for ARM Architecture." International Journal Of Recent Advances in Engineering & Technology 08, no. 02 (February 29, 2020): 22–27. http://dx.doi.org/10.46564/ijraet.2020.v08i02.004.

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37

Huang, Di-Wei, Rodolphe J. Gentili, Garrett E. Katz, and James A. Reggia. "A limit-cycle self-organizing map architecture for stable arm control." Neural Networks 85 (January 2017): 165–81. http://dx.doi.org/10.1016/j.neunet.2016.10.005.

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38

Manda, V. L. K. Bharadwaj, Voona Kushal, and N. Ramasubramanian. "An Elegant Home Automation System Using GSM and ARM-Based Architecture." IEEE Potentials 37, no. 5 (September 2018): 43–48. http://dx.doi.org/10.1109/mpot.2016.2515644.

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39

Dychka, Ivan A., Denys A. Vinnyk, Yuriy V. Bukhtiyarov, and Vasyl Ya Yurchyshyn. "METHOD OF FAST MATRIX MULTIPLICATION UNDER ARM ARCHITECTURE USING SIMD INSTRUCTIONS." KPI Science News, no. 2 (June 9, 2020): 35–43. http://dx.doi.org/10.20535/kpi-sn.2020.2.205115.

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40

Kabuka, M. R., P. N. Glaskowsky, and J. Miranda. "Microcontroller-based architecture for control of a six joint robot arm." IEEE Transactions on Industrial Electronics 35, no. 2 (May 1988): 217–21. http://dx.doi.org/10.1109/41.192652.

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41

Oyarzun, G., R. Borrell, A. Gorobets, F. Mantovani, and A. Oliva. "Efficient CFD code implementation for the ARM-based Mont-Blanc architecture." Future Generation Computer Systems 79 (February 2018): 786–96. http://dx.doi.org/10.1016/j.future.2017.09.029.

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42

Xu, Sendren Sheng-Dong, and Teng-Chang Chang. "A Feasible Architecture for ARM-Based Microserver Systems Considering Energy Efficiency." IEEE Access 5 (2017): 4611–20. http://dx.doi.org/10.1109/access.2017.2657658.

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43

Zhu, Jin, Dan Dan Yan, and Jie Zhang. "Design of Intelligent Mouse Based on ARM." Applied Mechanics and Materials 427-429 (September 2013): 876–79. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.876.

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Intelligent Mouse is a micro-robot with special wisdom and it is a typical electro-mechanical integration system. This document has detailedly described the facture of mechanical structure, circuit design, software algorithm and other hardware system configurations. For the hardware, the control center of this mouse has used LM3S615 microcontroller which is based on the ARM® CortexTM-M3 v7M architecture developed by Luminary. This document also introduced that, the left/right-hand searching of the mouse, mapping, and calculation of the shortest path.
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44

Wagner, K. "ARM twisting with Sir Robin: An interview with ARM chairman Sir Robin Saxby." IEEE Design & Test of Computers 20, no. 5 (September 2003): 90–93. http://dx.doi.org/10.1109/mdt.2003.1232261.

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45

Koyama, Keisuke, Makoto Shimojo, Aiguo Ming, and Masatoshi Ishikawa. "Integrated control of a multiple-degree-of-freedom hand and arm using a reactive architecture based on high-speed proximity sensing." International Journal of Robotics Research 38, no. 14 (September 25, 2019): 1717–50. http://dx.doi.org/10.1177/0278364919875811.

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We describe integrated control of a multiple-degree-of-freedom hand and arm using a simple reactive architecture based on high-speed proximity sensing. A proximity sensor installed on each fingertip of the hand detects the positions between the sensor and the surface of an object. By feeding back the sensor outputs, the reactive architecture simultaneously controls the position of the arm tip and the vector connecting the grasping position and the origin of the arm tip coordinates, the wrist posture, and the initial finger configurations before grasping. This architecture makes it possible to correct position errors. In addition, since the positions and postures are controlled without contact, there is no danger of damaging the object or the robot. To realize this integrated control using a simple reactive architecture, we designed a high-speed proximity sensor for the fingertips of the hand, and developed an integrated control system for the hand and the arm. We demonstrate high-speed position adjustment motion and grasping for static and moving objects in experiments.
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46

Singh, Gurpreet, and Rajeev Sobti. "SHA-3 Blake Finalist on Hardware Architecture of ARM Cortex A8 Processor." International Journal of Computer Applications 123, no. 13 (August 18, 2015): 22–27. http://dx.doi.org/10.5120/ijca2015905583.

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47

Alessandrini, Michele, Giorgio Biagetti, Paolo Crippa, Laura Falaschetti, Lorenzo Manoni, and Claudio Turchetti. "Singular Value Decomposition in Embedded Systems Based on ARM Cortex-M Architecture." Electronics 10, no. 1 (December 28, 2020): 34. http://dx.doi.org/10.3390/electronics10010034.

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Singular value decomposition (SVD) is a central mathematical tool for several emerging applications in embedded systems, such as multiple-input multiple-output (MIMO) systems, data analytics, sparse representation of signals. Since SVD algorithms reduce to solve an eigenvalue problem, that is computationally expensive, both specific hardware solutions and parallel implementations have been proposed to overcome this bottleneck. However, as those solutions require additional hardware resources that are not in general available in embedded systems, optimized algorithms are demanded in this context. The aim of this paper is to present an efficient implementation of the SVD algorithm on ARM Cortex-M. To this end, we proceed to (i) present a comprehensive treatment of the most common algorithms for SVD, providing a fairly complete and deep overview of these algorithms, with a common notation, (ii) implement them on an ARM Cortex-M4F microcontroller, in order to develop a library suitable for embedded systems without an operating system, (iii) find, through a comparative study of the proposed SVD algorithms, the best implementation suitable for a low-resource bare-metal embedded system, (iv) show a practical application to Kalman filtering of an inertial measurement unit (IMU), as an example of how SVD can improve the accuracy of existing algorithms and of its usefulness on a such low-resources system. All these contributions can be used as guidelines for embedded system designers. Regarding the second point, the chosen algorithms have been implemented on ARM Cortex-M4F microcontrollers with very limited hardware resources with respect to more advanced CPUs. Several experiments have been conducted to select which algorithms guarantee the best performance in terms of speed, accuracy and energy consumption.
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48

Basile, Francesco, Fabrizio Caccavale, Pasquale Chiacchio, Jolanda Coppola, and Alessandro Marino. "A decentralized kinematic control architecture for collaborative and cooperative multi-arm systems." Mechatronics 23, no. 8 (December 2013): 1100–1112. http://dx.doi.org/10.1016/j.mechatronics.2013.08.008.

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49

OOGA, Jun'ichiro, Hideichi NAKAMOTO, Fumio OZAKI, and Takashi YOSHIMI. "1P1-D01 Wire Driven Arm Control based on Open Robot Controller Architecture." Proceedings of JSME annual Conference on Robotics and Mechatronics (Robomec) 2007 (2007): _1P1—D01_1—_1P1—D01_2. http://dx.doi.org/10.1299/jsmermd.2007._1p1-d01_1.

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50

Wood, R. J. "Robotic manipulation using an open-architecture industrial arm: a pedagogical overview [Education]." IEEE Robotics & Automation Magazine 15, no. 3 (September 2008): 17–18. http://dx.doi.org/10.1109/mra.2008.928281.

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