Academic literature on the topic 'Architecture dataflow'
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Journal articles on the topic "Architecture dataflow":
Kavi, K. M., and B. Shirazi. "Dataflow architecture." IEEE Potentials 11, no. 3 (October 1992): 27–30. http://dx.doi.org/10.1109/45.207108.
Veen, Arthur H. "Dataflow machine architecture." ACM Computing Surveys 18, no. 4 (December 11, 1986): 365–96. http://dx.doi.org/10.1145/27633.28055.
Rockey, Mark. "The dataflow architecture." ACM SIGARCH Computer Architecture News 13, no. 4 (September 1985): 8–14. http://dx.doi.org/10.1145/381752.381754.
Šilc, Jurij, and Borut Robič. "Synchronous dataflow-based architecture." Microprocessing and Microprogramming 27, no. 1-5 (August 1989): 315–22. http://dx.doi.org/10.1016/0165-6074(89)90065-3.
Kao, Hsu-Yu, Xin-Jia Chen, and Shih-Hsu Huang. "Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing." Sensors 21, no. 15 (July 27, 2021): 5081. http://dx.doi.org/10.3390/s21155081.
Teifel, J., and R. Manohar. "An asynchronous dataflow FPGA architecture." IEEE Transactions on Computers 53, no. 11 (November 2004): 1376–92. http://dx.doi.org/10.1109/tc.2004.88.
Mihelič, Jurij, and Uroš Čibej. "EXPERIMENTAL COMPARISON OF MATRIX ALGORITHMS FOR DATAFLOW COMPUTER ARCHITECTURE." Acta Electrotechnica et Informatica 18, no. 3 (September 27, 2018): 47–56. http://dx.doi.org/10.15546/aeei-2018-0025.
Fabiani, Erwan. "Experiencing a Problem-Based Learning Approach for Teaching Reconfigurable Architecture Design." International Journal of Reconfigurable Computing 2009 (2009): 1–11. http://dx.doi.org/10.1155/2009/923415.
Guo, Jia Rong, Ran Feng, Zhuo Bi, and Mei Hua Xu. "A Compiler for Ladder Diagram to Multi-Core Dataflow Architecture." Advanced Materials Research 462 (February 2012): 368–74. http://dx.doi.org/10.4028/www.scientific.net/amr.462.368.
Hu, Weiming. "Dataflow architecture for EEG patient monitor." ACM SIGARCH Computer Architecture News 13, no. 2 (June 1985): 3–10. http://dx.doi.org/10.1145/1296935.1296936.
Dissertations / Theses on the topic "Architecture dataflow":
Iannucci, Robert A. "A dataflow/von Neumann hybrid architecture." Thesis, Massachusetts Institute of Technology, 1988. http://hdl.handle.net/1721.1/14778.
Benjamin, Steven I. "Dataflow : overview and simulation /." Online version of thesis, 1988. http://hdl.handle.net/1850/10221.
Narayanaswamy, Ramya Priyadharshini. "Design of a Power-aware Dataflow Processor Architecture." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/34192.
Master of Science
Moser, Nico, Carsten Gremzow, and Matthias Menge. "Interconnection Optimization for Dataflow Architectures." Universitätsbibliothek Chemnitz, 2007. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200700950.
Ruggiero, C. A. "Throttle mechanisms for the Manchester Dataflow Machine." Thesis, University of Manchester, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.382765.
Li, Feng. "Compiling for a multithreaded dataflow architecture : algorithms, tools, and experience." Phd thesis, Université Pierre et Marie Curie - Paris VI, 2014. http://tel.archives-ouvertes.fr/tel-00992753.
Motiwala, Quaeed. "Optimizations for acyclic dataflow graphs for hardware-software codesign." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06302009-040504/.
Savaş, Süleyman. "Linear Algebra for Array Signal Processing on a Massively Parallel Dataflow Architecture." Thesis, Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-2192.
This thesis provides the deliberations about the implementation of Gentleman-Kung systolic array for QR decomposition using Givens Rotations within the context of radar signal
processing. The systolic array of Givens Rotations is implemented and analysed using a massively parallel processor array (MPPA), Ambric Am2045. The tools that are dedicated to the MPPA are tested in terms of engineering efficiency. aDesigner, which is built on eclipse environment, is used for programming, simulating and performance analysing. aDesigner has been produced for Ambric chip family. 2 parallel matrix multiplications have been implemented
to get familiar with the architecture and tools. Moreover different sized systolic arrays are implemented and compared with each other. For programming, ajava and astruct languages are provided. However floating point numbers are not supported by the provided languages.
Thus fixed point arithmetic is used in systolic array implementation of Givens Rotations. Stable and precise numerical results are obtained as outputs of the algorithms. However the analysis
results are not reliable because of the performance analysis tools.
Savaş, Süleyman. "Linear Algebra for Array Signal Processing on a Massively Parallel Dataflow Architecture." Thesis, Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-4137.
This thesis provides the deliberations about the implementation of Gentleman-Kung systolic array for QR decomposition using Givens Rotations within the context of radar signal processing. The systolic array of Givens Rotations is implemented and analysed using a massively parallel processor array (MPPA), Ambric Am2045. The tools that are dedicated to the MPPA are tested in terms of engineering efficiency. aDesigner, which is built on eclipse environment, is used for programming, simulating and performance analysing. aDesigner has been produced for Ambric chip family. 2 parallel matrix multiplications have been implemented to get familiar with the architecture and tools. Moreover different sized systolic arrays are implemented and compared with each other. For programming, ajava and astruct languages are provided. However floating point numbers are not supported by the provided languages. Thus fixed point arithmetic is used in systolic array implementation of Givens Rotations. Stable
and precise numerical results are obtained as outputs of the algorithms. However the analysis results are not reliable because of the performance analysis tools.
Pradal, Christophe. "Architecture de dataflow pour des systèmes modulaires et génériques de simulation de plante." Thesis, Montpellier, 2019. http://www.theses.fr/2019MONTS034.
Biological modeling, particularly of plant growth and functioning, is a rapidly expanding field that is useful in addressing climate change and food security issues at the global level. Modeling and simulation are essential tools for understanding the complex relationships between plant architecture and the processes that influence their growth in a changing environment.For plant modeling, a large number of formalisms have been developed in many disciplines and at different scales of representation.The objective of this thesis is to define a modular architecture that allows to simulate structural-functional plant systems by reusing and assembling different existing models.We will first study the different approaches to software reuse proposed by Krueger, then blackboard systems, and scientific workflow systems.These different approaches are used to cooperate, reuse and assemble software artifacts in a modular manner.Based on the observation that these systems provide the abstractions necessary for the integration of various artifacts, our working hypothesis is that a hybrid architecture, based on blackboard systems with dataflow-driven procedural control, would both achieve modularity while allowing the modeler to maintain control over execution.In Chapter 2, we describe the OpenAlea platform, a platform with software components and a scientific workflow system, allowing the assembly and composition of models through a visual programming interface. In Chapter 3, we propose a data structure for the blackboard, combining a topological representation of plant architecture at different scales, the Multiscale Tree Graph, and its geometric spatialization using the 3D PlantGL library. In chapter 4, we present the lambda-dataflows, an extension of dataflows allowing to couple simulation and analysis.Then, in Chapter 5, we present a first application, which illustrates the use of a generic gramineous leaf model in different plant models. Finally, in Chapter 6, we present all the architectural elements used to develop a generic framework for modelling the development of foliar diseases in an architectural canopy.The architecture presented in this thesis and its implementation in OpenAlea are a first step towards the realization of open integrative modeling platforms, allowing the cooperation of heterogeneous models in biology. The use of scientific workflow formalism in analysis and simulation makes it possible to consider in the short term the development of collaborative and distributed simulation platforms on a large scale
Books on the topic "Architecture dataflow":
Lent, Bogdan. Dataflow architecture for machine control. Taunton: Research Studies Press, 1989.
Lent, Bogdan. Dataflow architecture for machine control. Taunton, Somerset, England: Research Studies Press, 1989.
Kavi, Krishna M. Reliability models for dataflow computer systems. Moffett Field, Calif: National Aeronautics and Space Administration, Ames Research Center, 1985.
Papadopoulos, Gregory Michael. Implementation of a general-purpose dataflow multiprocessor. London: Pitman, 1991.
Gao, Guang R. A code mapping scheme for dataflow software pipelining. Boston: Kluwer Academic Publishers, 1991.
Iannucci, Robert A. Parallel machines: Parallel machine languages : the emergence of hybrid dataflow computer achitectures. Boston: Kluwer Academic Publishers, 1990.
Iannucci, Robert A. Parallel Machines: Parallel Machine Languages: The Emergence of Hybrid Dataflow Computer Architectures. Boston, MA: Springer US, 1990.
Blokdyk, Gerardus. Dataflow architecture: Standard Requirements. CreateSpace Independent Publishing Platform, 2018.
Center, Langley Research, ed. Simulator for heterogeneous dataflow architectures. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1993.
Silc, Jurij, Borut Robic, and Theo Ungerer. Processor Architecture: From Dataflow to Superscalar and Beyond. Springer, 1999.
Book chapters on the topic "Architecture dataflow":
Šilc, Jurij, Borut Robič, and Theo Ungerer. "Dataflow Processors." In Processor Architecture, 55–97. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-642-58589-0_2.
Delgado-Frias, José, Ardsher Ahmed, and Robert Payne. "A Dataflow Architecture for AI." In VLSI for Artificial Intelligence and Neural Networks, 23–32. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3752-6_3.
Gunzinger, A., S. Mathis, and W. Guggenbühl. "The Synchronous Dataflow MAchine: Architecture and performance." In PARLE '89 Parallel Architectures and Languages Europe, 85–99. Berlin, Heidelberg: Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/3540512845_34.
Gao, Guang R., Herbert H. J. Hum, and Jean-Marc Monti. "Towards an efficient hybrid dataflow architecture model." In PARLE '91 Parallel Architectures and Languages Europe, 355–71. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/bfb0035115.
Bonchev, Boyan, and Miroslav Iliev. "A hybrid dataflow architecture with multiple tokens." In Parallel Processing: CONPAR 92—VAPP V, 737–42. Berlin, Heidelberg: Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/3-540-55895-0_477.
Kusakabe, Shigeru, Takahide Hoshide, Rin-ichiro Taniguchi, and Makoto Amamiya. "Parallelism control scheme in a dataflow architecture." In Parallel Processing: CONPAR 92—VAPP V, 743–48. Berlin, Heidelberg: Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/3-540-55895-0_478.
Gao, Guang R., Herbert H. J. Hum, and Jean-Marc Monti. "Towards an Efficient Hybrid Dataflow Architecture Model." In Parle ’91 Parallel Architectures and Languages Europe, 355–71. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-662-25209-3_24.
Ruggiero, Carlos A., and John Sargeant. "Control of parallelism in the Manchester dataflow machine." In Functional Programming Languages and Computer Architecture, 1–15. Berlin, Heidelberg: Springer Berlin Heidelberg, 1987. http://dx.doi.org/10.1007/3-540-18317-5_1.
Giorgi, Roberto, Marco Procaccini, and Amin Sahebi. "DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model." In Architecture of Computing Systems, 84–100. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81682-7_6.
Wu, Xinxin, Yi Li, Yan Ou, Wenming Li, Shibo Sun, Wenxing Xu, and Dongrui Fan. "Accelerating Sparse Convolutional Neural Networks Based on Dataflow Architecture." In Algorithms and Architectures for Parallel Processing, 14–31. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-60239-0_2.
Conference papers on the topic "Architecture dataflow":
Nowatzki, Tony, Vinay Gangadhar, Newsha Ardalani, and Karthikeyan Sankaralingam. "Stream-Dataflow Acceleration." In ISCA '17: The 44th Annual International Symposium on Computer Architecture. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3079856.3080255.
Rau, B. R. "Cydra 5 directed dataflow architecture." In COMPCON Spring 88. IEEE, 1988. http://dx.doi.org/10.1109/cmpcon.1988.4840.
Ekpanyapong, Mongkol, Michael Healy, and Sung Kyu Lim. "Placement for configurable dataflow architecture." In the 2005 conference. New York, New York, USA: ACM Press, 2005. http://dx.doi.org/10.1145/1120725.1120840.
Santiago, Leandro, Leandro A. J. Marzulo, Brunno F. Goldstein, Tiago A. O. Alves, and Felipe M. G. Franca. "Stack-Tagged Dataflow." In 2014 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW). IEEE, 2014. http://dx.doi.org/10.1109/sbac-padw.2014.21.
Yee, J. J., and C. K. Yuen. "BIDDLE: a dataflow architecture for Lisp." In Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences. IEEE, 1992. http://dx.doi.org/10.1109/hicss.1992.183211.
Skoda, P., V. Sruk, and B. Medved Rogina. "Frequency table computation on dataflow architecture." In 2014 37th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO). IEEE, 2014. http://dx.doi.org/10.1109/mipro.2014.6859588.
Arul, Joseph M., Krishna M. Kavi, and Shuaib Hanief. "Cache Performance of Scheduled Dataflow Architecture." In Proceedings of the 4th International Conference. WORLD SCIENTIFIC, 2000. http://dx.doi.org/10.1142/9789812792037_0011.
Vilim, Matthew, Alexander Rucker, and Kunle Olukotun. "Aurochs: An Architecture for Dataflow Threads." In 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2021. http://dx.doi.org/10.1109/isca52012.2021.00039.
Li Wang, Hong An, Yongqing Ren, and Yaobin Wang. "Profile guided optimization for dataflow predication." In 2008 13th Asia-Pacific Computer Systems Architecture Conference (ACSAC). IEEE, 2008. http://dx.doi.org/10.1109/apcsac.2008.4625471.
Lira, Vittor F., Felippe H. Cerreia, Leandro Santiago, Alexandre C. Sena, Maria Clicia S. De Castro, and Leandro A. J. Marzulo. "Dataflow Virtual Machine Profiling." In 2014 IEEE 26th International Symposium on Computer Architecture and High-Performance Computing Workshops (SBAC-PADW). IEEE, 2014. http://dx.doi.org/10.1109/sbac-padw.2014.24.
Reports on the topic "Architecture dataflow":
Iannucci, Robert A. A Dataflow/Von Neumann Hybrid Architecture. Fort Belvoir, VA: Defense Technical Information Center, July 1988. http://dx.doi.org/10.21236/ada200987.
Linn, Cathy J., Joseph L. Linn, Stephen H. Edwards, Michael R. Kappel, and Cy D. Ardoin. A Simple Example of an SADMT (SDI-Strategic Defense Initiative) Architecture Dataflow Modeling Technique) Architecture Specification. Version 1.5. Fort Belvoir, VA: Defense Technical Information Center, April 1988. http://dx.doi.org/10.21236/ada195825.
Kappel, Michael R., Cy D. Ardoin, Cathy J. Linn, Joseph L. Linn, and John Salasin. SAGEN (SADMT (Strategic Defense Initiative Architecture Dataflow Modeling Technique) Generator) User's Guide Version. 1.5. Fort Belvoir, VA: Defense Technical Information Center, April 1988. http://dx.doi.org/10.21236/ada195858.