Relevant bibliographies by topics / Arithmetic and logic structures

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Arithmetic and logic structures'

Author: Grafiati
Published: 4 June 2021
Last updated: 20 February 2023

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Journal articles on the topic "Arithmetic and logic structures"

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Thapen, Neil. "Structures interpretable in models of bounded arithmetic." Annals of Pure and Applied Logic 136, no. 3 (November 2005): 247–66. http://dx.doi.org/10.1016/j.apal.2005.04.005.

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Teichmann, Ph, J. Fischer, F. Chouard, and D. Schmitt-Landsiedel. "Design issues of arithmetic structures in adiabatic logic." Advances in Radio Science 5 (June 13, 2007): 291–95. http://dx.doi.org/10.5194/ars-5-291-2007.

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Abstract. Since adiabatic logic uses a supply that incorporates both supply voltage and clock signal in one line, adiabatic logic systems have a built-in micro-pipelined architecture. Considering this fact, different design constraints have to be observed compared to static CMOS designs. Complex arithmetic building blocks, like multipliers, mainly consist of adders. Therefore, a comparison of adder structures is performed. Based on these results, multipliers and complex systems can be built. A Discrete Cosine Transformation (DCT) is taken as example for an arithmetic system. Comparing an adiabatic logic implementation of a DCT to its static CMOS counterpart, a significant saving factor of more than 10 can be achieved with the adiabatic system.
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Mortensen, Chris. "Inconsistent nonstandard arithmetic." Journal of Symbolic Logic 52, no. 2 (June 1987): 512–18. http://dx.doi.org/10.2307/2274397.

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AbstractThis paper continues the investigation of inconsistent arithmetical structures. In §2 the basic notion of a model with identity is defined, and results needed from elsewhere are cited. In §3 several nonisomorphic inconsistent models with identity which extend the (=, <) theory of the usual classical denumerable nonstandard model of arithmetic are exhibited. In §4 inconsistent nonstandard models of the classical theory of finite rings and fields modulo m, i.e. Zm, are briefly considered. In §5 two models modulo an infinite nonstandard number are considered. In the first, it is shown how to model inconsistently the arithmetic of the rationals with all names included, a strengthening of earlier results. In the second, all inconsistency is confined to the nonstandard integers, and the effects on Fermat's Last Theorem are considered. It is concluded that the prospects for a good inconsistent theory of fields may be limited.
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Montalbán, Antonio. "A fixed point for the jump operator on structures." Journal of Symbolic Logic 78, no. 2 (June 2013): 425–38. http://dx.doi.org/10.2178/jsl.7802050.

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AbstractAssuming that 0# exists, we prove that there is a structure that can effectively interpret its own jump. In particular, we get a structure such thatwhere is the set of Turing degrees which compute a copy of More interesting than the result itself is its unexpected complexity. We prove that higher-order arithmetic, which is the union of full “nth-order arithmetic for all n, cannot prove the existence of such a structure.
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Bès, Alexis, and Denis Richard. "Undecidable extensions of Skolem arithmetic." Journal of Symbolic Logic 63, no. 2 (June 1998): 379–401. http://dx.doi.org/10.2307/2586837.

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AbstractLet be the restriction of usual order relation to integers which are primes or squares of primes, and let ⊥ denote the coprimeness predicate. The elementary theory of is undecidable. Now denote by <π the restriction of order to primary numbers. All arithmetical relations restricted to primary numbers are definable in the structure (ℕ; ⊥, <π). Furthermore, the structures (ℕ; ∣, <π) (ℕ; =, ×, <π) and (ℕ; =, +, ×) are interdefinable.
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Shore, Richard A. "Local Definitions in Degree Structures: The Turing Jump, Hyperdegrees and Beyond." Bulletin of Symbolic Logic 13, no. 2 (June 2007): 226–39. http://dx.doi.org/10.2178/bsl/1185803806.

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AbstractThere are Π5 formulas in the language of the Turing degrees, D, with ≤, ⋁ and ⋀, that define the relations x″ ≤ y″, x″ = y″ and so x ∈ L2(y) = {x ≥ y ∣ x″ = y″} in any jump ideal containing 0(ω). There are also Σ6 & Π6 and Π8 formulas that define the relations w = x″ and w = x′, respectively, in any such ideal I. In the language with just ≤ the quantifier complexity of each of these definitions increases by one. On the other hand, no Π2 or Σ2 formula in the language with just ≤ defines L2 or x ∈ L2(y). Our arguments and constructions are purely degree theoretic without any appeals to absoluteness considerations, set theoretic methods or coding of models of arithmetic. As a corollary, we see that every automorphism of I is fixed on every degree above 0″ and every relation on I that is invariant under double jump or joining with 0″ is definable over I if and only if it is definable in second order arithmetic with set quantification ranging over sets whose degrees are in I. Similar direct coding arguments show that every hyperjump ideal I is rigid and biinterpretable with second order arithmetic with set quantification ranging over sets with hyperdegrees in I. Analogous results hold for various coarser degree structures.
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MCLARTY, COLIN. "THE LARGE STRUCTURES OF GROTHENDIECK FOUNDED ON FINITE-ORDER ARITHMETIC." Review of Symbolic Logic 13, no. 2 (August 2, 2019): 296–325. http://dx.doi.org/10.1017/s1755020319000340.

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AbstractThe large-structure tools of cohomology including toposes and derived categories stay close to arithmetic in practice, yet published foundations for them go beyond ZFC in logical strength. We reduce the gap by founding all the theorems of Grothendieck’s SGA, plus derived categories, at the level of Finite-Order Arithmetic, far below ZFC. This is the weakest possible foundation for the large-structure tools because one elementary topos of sets with infinity is already this strong.
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Bhuvana, B. P., and V. S. Kanchana Bhaaskaran. "Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures." Journal of Circuits, Systems and Computers 29, no. 01 (April 23, 2019): 2050016. http://dx.doi.org/10.1142/s0218126620500164.

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This paper presents the adiabatic logic called 2[Formula: see text]–[Formula: see text]–2[Formula: see text], which can operate with less number of transistors and high energy efficiency than the existing circuit styles. It is a dual rail logic operated by four-phase power clock (PC). The 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic is capable of operating through a wide range of frequency from 100[Formula: see text]MHz to 1[Formula: see text]GHz. Relentless scaling of MOSFETs towards lower technology nodes results in short channel effects in addition to increasing higher leakage current issues. In this scenario, FinFET advantageously replaces MOSFET with its unique features of the elimination of the short channel effects encountered by the MOSFETs with its gate structure that wraps around the channel completely. It incurs that the lower energy consumption and the feasibility of designing energy recovery circuits using FinFETs are analyzed in this paper. Comparatively, the energy efficiency of FinFET-based 2[Formula: see text]–[Formula: see text]–2[Formula: see text] against the [Formula: see text] and Positive Feedback Adiabatic Logic (PFAL) are analyzed. Simulation results also validate the robustness and efficiency of 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic circuit under process parameter variations of FinFET technology. Complex adiabatic adders and multipliers taken as bench mark circuits have been designed using 32-nm FinFET technology node and the results validate the enhanced energy efficiency characteristics of 2[Formula: see text]–[Formula: see text]2[Formula: see text] over [Formula: see text] and PFAL designs.
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Erdélyi-Szabó, Miklós. "Undecidability of the real-algebraic structure of models of intuitionistic elementary analysis." Journal of Symbolic Logic 65, no. 3 (September 2000): 1014–30. http://dx.doi.org/10.2307/2586686.

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AbstractWe show that true first-order arithmetic is interpretable over the real-algebraic structure of models of intuitionistic analysis built upon a certain class of complete Heyting algebras. From this the undecidability of the structures follows. We also show that Scott's model is equivalent to true second-order arithmetic. In the appendix we argue that undecidability on the language of ordered rings follows from intuitionistically plausible properties of the real numbers.
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KAYE, RICHARD. "INTERPRETATIONS BETWEENω-LOGIC AND SECOND-ORDER ARITHMETIC." Journal of Symbolic Logic 79, no. 3 (August 18, 2014): 845–58. http://dx.doi.org/10.1017/jsl.2013.17.

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AbstractThis paper addresses the structures (M, ω) and (ω, SSy(M)), whereMis a nonstandard model of PA andωis the standard cut. It is known that (ω, SSy(M)) is interpretable in (M, ω). Our main technical result is that there is an reverse interpretation of (M, ω) in (ω, SSy(M)) which is ‘local’ in the sense of Visser [11]. We also relate the model theory of (M, ω) to the study of transplendent models of PA [2].This yields a number of model theoretic results concerning theω-models (M, ω) and their standard systems SSy(M, ω), including the following.•$\left( {M,\omega } \right) \prec \left( {K,\omega } \right)$if and only if$M \prec K$and$\left( {\omega ,{\rm{SSy}}\left( M \right)} \right) \prec \left( {\omega ,{\rm{SSy}}\left( K \right)} \right)$.•$\left( {\omega ,{\rm{SSy}}\left( M \right)} \right) \prec \left( {\omega ,{\cal P}\left( \omega \right)} \right)$if and only if$\left( {M,\omega } \right) \prec \left( {{M^{\rm{*}}},\omega } \right)$for someω-saturatedM*.•$M{ \prec _{\rm{e}}}K$implies SSy(M, ω) = SSy(K, ω), but cofinal extensions do not necessarily preserve standard system in this sense.• SSy(M, ω)=SSy(M) if and only if (ω, SSy(M)) satisfies the full comprehension scheme.• If SSy(M, ω) is uniformly defined by a single formula (analogous to aβfunction), then (ω, SSy(M, ω)) satisfies the full comprehension scheme; and there are modelsMfor which SSy(M, ω) is not uniformly defined in this sense.
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Dissertations / Theses on the topic "Arithmetic and logic structures"

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Gilman, Andrew. "Least-squares optimal interpolation for direct image super-resolution : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Engineering at Massey University, Palmerston North, New Zealand." Massey University, 2009. http://hdl.handle.net/10179/893.

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Image super-resolution aims to produce a higher resolution representation of a scene from an ensemble of low-resolution images that may be warped, aliased, blurred and degraded by noise. There are a variety of methods for performing super-resolution described in the literature, and in general they consist of three major steps: image registration, fusion and deblurring. This thesis proposes a novel method of performing the first two of these steps. The ultimate aim of image super-resolution is to produce a higher-quality image that is visually clearer, sharper and contains more detail than the individual input images. Machine algorithms can not assess images qualitatively and typically use a quantitative error criterion, often least-squares. This thesis aims to optimise leastsquares directly using a fast method, in particular one that can be implemented using linear filters; hence, a closed-form solution is required. The concepts of optimal interpolation and resampling are derived and demonstrated in practice. Optimal filters optimised on one image are shown to perform nearoptimally on other images, suggesting that common image features, such as stepedges, can be used to optimise a near-optimal filter without requiring the knowledge of the ground-truth output. This leads to the construction of a pulse model, which is used to derive filters for resampling non-uniformly sampled images that result from the fusion of registered input images. An experimental comparison shows that a 10th order pulse model-based filter outperforms a number of methods common in the literature. The use of optimal interpolation for image registration linearises an otherwise nonlinear problem, resulting in a direct solution. Experimental analysis is used to show that optimal interpolation-based registration outperforms a number of existing methods, both iterative and direct, at a range of noise levels and for both heavily aliased images and images with a limited degree of aliasing. The proposed method offers flexibility in terms of the size of the region of support, offering a good trade-off in terms of computational complexity and accuracy of registration. Together, optimal interpolation-based registration and fusion are shown to perform fast, direct and effective super-resolution.
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Bhupatiraju, Raja D. V. "A comparative study of high speed adders." Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1175891877.

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Chakrapani, Lakshmi Narasimhan. "Probabilistic boolean logic, arithmetic and architectures." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26706.

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Thesis (Ph.D)--Computing, Georgia Institute of Technology, 2009.
Committee Chair: Palem, Krishna V.; Committee Member: Lim, Sung Kyu; Committee Member: Loh, Gabriel H.; Committee Member: Mudge, Trevor; Committee Member: Yalamanchili, Sudhakar. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Wang, Shaoyun. "A CORDIC arithmetic processor /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.

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Hamel, Mariah. "Arithmetic structures in random sets." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/2838.

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We prove various results in additive combinatorics for subsets of random sets. In particular we extend Sarkozy's theorem and a theorem of Green on long arithmetic progressions in sumsets to dense subsets of random sets with asymptotic density 0. Our proofs require a transference argument due to Green and Green-Tao which enables us to apply known results for sets of positive upper density to subsets of random sets which have positive relative density. We also prove a density result which states that if a subset of a random set has positive relative density, then the sumset of the subset must have positive upper density in the integers.
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DUARTE, ALESSANDRO BANDEIRA. "LOGIC AND ARITHMETIC IN FREGE´S PHILOSOPHY OF MATHEMATICS." PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO, 2009. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=13942@1.

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PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO
Nos Fundamentos da Aritmética (parágrafo 68), Frege propõe definir explicitamente o operador-abstração ´o número de...´ por meio de extensões e, a partir desta definição, provar o Princípio de Hume (PH). Contudo, a prova imaginada por Frege depende de uma fórmula (BB) não provável no sistema em 1884. Acreditamos que a distinção entre sentido e referência e a introdução dos valores de verdade como objetos foram motivada para justificar a introdução do Axioma IV, a partir do qual um análogo de (BB) é provável. Com (BB) no sistema, a prova do Princípio de Hume estaria garantida. Concomitantemente, percebemos que uma teoria unificada das extensões só é possível com a distinção entre sentido e referência e a introdução dos valores de verdade como objetos. Caso contrário, Frege teria sido obrigado a introduzir uma série de Axiomas V no seu sistema, o que acarretaria problemas com a identidade (Júlio César). Com base nestas considerações, além do fato de que, em 1882, Frege provara as leis básicas da aritmética (carta a Anton Marty), parece-nos perfeitamente plausível que as estas provas foram executadas adicionando-se o PH ao sistema lógico de Begriffsschrift. Mostramos que, nas provas dos axiomas de Peano a partir de PH dentro da conceitografia, nenhum uso é feito de (BB). Destarte, não é necessária a introdução do Axioma IV no sistema e, por conseguinte, não são necessárias a distinção entre sentido e referência e a introdução dos valores de verdade como objetos. Disto, podemos concluir que, provavelmente, a introdução das extensões nos Fundamentos foi um ato tardio; e que Frege não possuía uma prova formal de PH a partir da sua definição explícita. Estes fatos também explicam a demora na publicação das Leis Básicas da Aritmética e o descarte de um manuscrito quase pronto (provavelmente, o livro mencionado na carta a Marty).
In The Foundations of Arithmetic (paragraph 68), Frege proposes to define explicitly the abstraction operator ´the number of …´ by means of extensions and, from this definition, to prove Hume´s Principle (HP). Nevertheless, the proof imagined by Frege depends on a formula (BB), which is not provable in the system in 1884. we believe that the distinction between sense and reference as well as the introduction of Truth-Values as objects were motivated in order to justify the introduction of Axiom IV, from which an analogous of (BB) is provable. With (BB) in the system, the proof of HP would be guaranteed. At the same time, we realize that a unified theory of extensions is only possible with the distinction between sense and reference and the introduction of Truth-Values as objects. Otherwise, Frege would have been obliged to introduce a series of Axioms V in his system, what cause problems regarding the identity (Julius Caesar). Based on these considerations, besides the fact that in 1882 Frege had proved the basic laws of Arithmetic (letter to Anton Marty), it seems perfectly plausible that these proofs carried out by adding to the Begriffsschrift´s logical system. We show that in the proofs of Peano s axioms from HP within the begriffsschrift, (BB) is not used at all. Thus, the introduction of Axiom IV in the system is not necessary and, consequently, neither the distinction between sense and reference nor the introduction of Truth- Values as objects. From these findings we may conclude that probably the introduction of extensions in The Foundations was a late act; and that Frege did not hold a formal proof of HP from his explicit definition. These facts also explain the delay in the publication of the Basic Laws of Arithmetic and the abandon of a manuscript almost finished (probably the book mentioned in the letter to Marty).
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Labrado, Carson. "Exploration of Majority Logic Based Designs for Arithmetic Circuits." UKnowledge, 2017. http://uknowledge.uky.edu/ece_etds/102.

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Since its inception, Moore's Law has been a reliable predictor of computational power. This steady increase in computational power has been due to the ability to fit increasing numbers of transistors in a single chip. A consequence of increasing the number of transistors is also increasing the power consumption. The physical properties of CMOS technologies will make this powerwall unavoidable and will result in severe restrictions to future progress and applications. A potential solution to the problem of rising power demands is to investigate alternative low power nanotechnologies for implementing logic circuits. The intrinsic properties of these emerging nanotechnologies result in them being low power in nature when compared to current CMOS technologies. This thesis specifically highlights quantum dot celluar automata (QCA) and nanomagnetic logic (NML) as just two possible technologies. Designs in NML and QCA are explored for simple arithmetic units such as full adders and subtractors. A new multilayer 5-input majority gate design is proposed for use in NML. Designs of reversible adders are proposed which are easily testable for unidirectional stuck at faults.
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Spenner, Laura. "Quantum logic implementation of unary arithmetic operations with inheritance." Ann Arbor, Mich. : ProQuest, 2008. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:1452767.

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Thesis (M.S. in Computer Engineering)--S.M.U.
Title from PDF title page (viewed Mar. 16, 2009). Source: Masters Abstracts International, Volume: 46-05, page: 2734. Adviser: Mitchell A. Thornton. Includes bibliographical references.
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Katreepalli, Raghava. "Efficient VLSI Implementation of Arithmetic Units and Logic Circuits." OpenSIUC, 2017. https://opensiuc.lib.siu.edu/dissertations/1471.

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Arithmetic units and logic circuits are critical components of any VLSI system. Thus realizing efficient arithmetic units and logic circuits is required for better performance of a data path unit and therefore microprocessor or digital signal processor (DSP). Adders are basic building blocks of any processor or data path application. For the design of high performance processing units, high-speed adders with low power consumption is a requirement. Carry Select Adder (CSA) is known to be one of the fastest adders used in many data processing applications. This first contribution of the dissertation is the design of a new CSA architecture using Manchester carry chain (MCC) in multioutput domino CMOS logic. It employs a novel MCC blocks in a hierarchical approach in the design of the CSA. The proposed MCC block is also extended in designing a power-delay and area efficient Vedic multiplier based on "Urdhva-Tiryakbhyam”. The simulation results shows that the proposed architecture achieves two fold advantages in terms of power-delay product (PDP) and hardware overhead. Apart from adders and multipliers, counters also play a major role in a data path unit. Counters are basic building blocks in many VLSI applications such as timers, memories, ADCs/DACs, frequency dividers etc. It is observed that design of counters has power overhead because of requirement of high power consumption for the clock signal distribution and undesired activity of flip-flops due to presence of clocks. The second contribution of the dissertation is the power efficient design of synchronous counters that reduces the power consumption due to clock distribution for different flip-flops and offers high reliability. The simulation results shows that the proposed counter design has lower power requirement and power-area product than existing counter architectures. Pipelines can be used for achieving high circuit operating speeds. However, as the operating frequency increases, the number of pipeline stages also increase linearly and so the memory elements. The third contribution of the dissertation is the dynamic memory-less pipeline design based on sinusoidal three-phase clocking scheme that reduces the power required by the clock and offers high circuit operating frequencies. Finally, the dissertation presents a novel tool for Boolean-function realization with minimum number of transistor in series. This tool is based on applying a new functional decomposition algorithms to decompose the initial Boolean-function into a network of smaller sub-functions and subsequently generating the final circuit. The effectiveness of proposed technique is estimated using circuit level simulations as well as using automated tool. The number of levels required using proposed technique is reduced by an average of 70% compared to existing techniques.
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Midde, Bharath Reddy. "Design, analysis, and synthesis of 16 bit arithmetic logic unit using reversible logic gate." Thesis, California State University, Long Beach, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10099864.

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In the modern world, an Arithmetic Logic Unit (ALU) is one of the most crucial component of an embedded system and is used in many devices like calculators, cell phones, computers, and so on. An ALU is a multi-functional circuit that conditionally performs one of several possible functions on two operands A and B depending on control inputs. It is nevertheless the main performer of any computing device. This project proposes the design of programmable reversible logic gate structures, targeted for the ALU implementation and their use in the realization of an efficient reversible ALU. This ALU consists of sixteen operations, the arithmetic operations include addition, subtraction, multiplication and the logical operations includes AND, OR, NOT and XOR. All the modules are being designed using the basic reversible gates.

Using reversible logic gates instead of traditional logic AND/OR gates, a reversible ALU is constructed whose function is the same as traditional ALU. Comparing with the number of input bits and the discarded bits of the traditional ALU, the reversible ALU significantly reduces the use and loss of information bits. The proposed reversible 16-bit ALU reuses the information bits and achieves the goal of lowering delay of logic circuits by 42% approximately. Programmable reversible logic gates are realized in Verilog HDL.

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Books on the topic "Arithmetic and logic structures"

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Kossak, Roman. The structure of models of Peano arithmetic. Oxford: Clarendon, 2006.

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Xu, Weixia. Computer Engineering and Technology: 16th National Conference, NCCET 2012, Shanghai, China, August 17-19, 2012, Revised Selected Papers. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013.

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Artemov, Sergei. Logical Foundations of Computer Science: International Symposium, LFCS 2013, San Diego, CA, USA, January 6-8, 2013. Proceedings. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013.

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Krishnaswamy, Smita. Design, Analysis and Test of Logic Circuits Under Uncertainty. Dordrecht: Springer Netherlands, 2013.

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Jamīl, T̤āriq. Complex Binary Number System: Algorithms and Circuits. India: Springer India, 2013.

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Keller, Rainer. Facing the Multicore-Challenge III: Aspects of New Paradigms and Technologies in Parallel Computing. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013.

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Stenström, Per. Transactions on High-Performance Embedded Architectures and Compilers IV. Berlin, Heidelberg: Springer-Verlag GmbH Berlin Heidelberg, 2011.

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Lu, Mi. Arithmetic and Logic in Computer Systems. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2004. http://dx.doi.org/10.1002/0471728519.

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Lu, Mi. Arithmetic and Logic in Computer Systems. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2004. http://dx.doi.org/10.1002/0471728519.

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Lu, Mi. Arithmetic and Logic in Computer Systems. New York: John Wiley & Sons, Ltd., 2005.

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Book chapters on the topic "Arithmetic and logic structures"

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Teichmann, Philip. "Arithmetic Structures in Adiabatic Logic." In Adiabatic Logic, 113–43. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-2345-0_6.

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Aoki, Takafumi, Naofumi Homma, and Tatsuo Higuchi. "Evolutionary Synthesis of Arithmetic Circuit Structures." In Artificial Intelligence in Logic Design, 39–72. Dordrecht: Springer Netherlands, 2004. http://dx.doi.org/10.1007/978-1-4020-2075-9_3.

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Csirmaz, Laszlo, and Zalán Gyenis. "Arithmetic." In Mathematical Logic, 107–22. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-79010-3_10.

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Trillas, Enric, and Luka Eciolaza. "Fuzzy Arithmetic." In Fuzzy Logic, 141–58. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-14203-6_6.

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Fried, Michael D., and Moshe Jarden. "Nonstandard Structures." In Field Arithmetic, 161–69. Berlin, Heidelberg: Springer Berlin Heidelberg, 1986. http://dx.doi.org/10.1007/978-3-662-07216-5_13.

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LaMeres, Brock J. "Arithmetic Circuits." In Introduction to Logic Circuits & Logic Design with Verilog, 373–402. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-53883-9_12.

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LaMeres, Brock J. "Arithmetic Circuits." In Introduction to Logic Circuits & Logic Design with VHDL, 385–415. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-34195-8_12.

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LaMeres, Brock J. "Arithmetic Circuits." In Introduction to Logic Circuits & Logic Design with Verilog, 397–426. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-13605-5_12.

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LaMeres, Brock J. "Arithmetic Circuits." In Introduction to Logic Circuits & Logic Design with VHDL, 407–37. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-12489-2_12.

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Jones, Robin, and Ian Stewart. "Arithmetic and Logic." In The Art of C Programming, 26–34. New York, NY: Springer US, 1987. http://dx.doi.org/10.1007/978-1-4613-8685-8_4.

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Conference papers on the topic "Arithmetic and logic structures"

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Nykolaychuk, Yaroslav, Natalia Vozna, Alina Davletova, Ihor Pitukh, Oleg Zastavnyy, and Volodymyr Hryha. "Microelectronic Structures of Arithmetic Logic Unit Components." In 2021 11th International Conference on Advanced Computer Information Technologies (ACIT). IEEE, 2021. http://dx.doi.org/10.1109/acit52158.2021.9548512.

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Teichmann, Philip, Jurgen Fischer, Florian R. Chouard, and Doris Schmitt-Landsiedel. "Design of Ultra-Low-Power Arithmetic Structures in Adiabatic Logic." In 2007 International Symposium on Integrated Circuits. IEEE, 2007. http://dx.doi.org/10.1109/isicir.2007.4441874.

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Drabik, Timothy J., and Sing H. Lee. "Parallel algorithms for matrix algebra problems on shift-connected digital optical single-instruction multiple-data arrays." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1986. http://dx.doi.org/10.1364/oam.1986.ml3.

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Shift-connected digital optical single-instruction multiple-data (SIMD) arrays1 comprise a 2-D (N × N) array of 1-bit logic/arithmetic elements with optical inputs and outputs, a memory that stores binary images, and hardware to perform arbitrary, programmable space-invariant shifts on data images as they are brought from memory to the logic array. Results of logic operations are returned to the memory in parallel. Such a shift-connected array can efficiently perform multiples of dense matrices or of sparse matrices possessing a multidiagonal structure from which algorithms for matrix inversion, partial differential equations, and eigenvalue problems can be assembled. Multiplication of an N vector by an N × N dense matrix requires computation time proportional to K2, where K is the number of bits of precision desired, and memory proportional to K. Multiplication of an N 2 vector by an N2 × N2 sparse matrix with multidiagonal structure corresponds to accumulating weighted, shifted versions of an N × N array of numbers. Computation time required is proportional to DK2, where D is the number of nonzero diagonals. Memory required also depends linearly on D. Because shifts across multiple processing elements are available, 2-D shift-connected arrays can easily be programmed to have 3-D or 4-D topologies as well.1 Multiples by sparse matrices arising from the discretization of continuous problems in two to four dimensions can be optimally performed on a processor array with the same dimensionality. The case of implementing these algorithms derives from the 2-D parallelism and global data movement capability of optical systems.
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Syamala, Y., and A. V. N. Tilak. "Reversible Arithmetic Logic Unit." In 2011 3rd International Conference on Electronics Computer Technology (ICECT). IEEE, 2011. http://dx.doi.org/10.1109/icectech.2011.5941987.

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Al Haddad, Mazen, Zaghloul ElSayed, and Magdy Bayoumi. "Green arithmetic logic unit." In 2012 International Conference on Energy Aware Computing (ICEAC). IEEE, 2012. http://dx.doi.org/10.1109/iceac.2012.6471013.

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Yi, Byeong-uk. "Plural Arithmetic." In 14th and 15th Asian Logic Conferences. WORLD SCIENTIFIC, 2019. http://dx.doi.org/10.1142/9789813237551_0014.

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Ghandali, Samaneh, Cunxi Yu, Duo Liu, Walter Brown, and Maciej Ciesielski. "Logic Debugging of Arithmetic Circuits." In 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2015. http://dx.doi.org/10.1109/isvlsi.2015.16.

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Valmari, Antti, and Johanna Rantala. "Arithmetic, Logic, Syntax and MathCheck." In 11th International Conference on Computer Supported Education. SCITEPRESS - Science and Technology Publications, 2019. http://dx.doi.org/10.5220/0007708902920299.

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Roda, Valentin O. "Session 3 - computer arithmetic." In 2010 VI Southern Programmable Logic Conference (SPL). IEEE, 2010. http://dx.doi.org/10.1109/spl.2010.5482997.

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An, Qi, Sebastien Le Beux, Ian O'Connor, Jacques Olivier Klein, and Weisheng Zhao. "Arithmetic Logic Unit based on all-spin logic devices." In 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS). IEEE, 2017. http://dx.doi.org/10.1109/newcas.2017.8010169.

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Reports on the topic "Arithmetic and logic structures"

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Pleszkun, Andrew R. Lithium Niobate Arithmetic Logic Unit. Fort Belvoir, VA: Defense Technical Information Center, March 1991. http://dx.doi.org/10.21236/ada236062.

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Ercegovac, Miloes D., and Tomas Lang. On-Line Arithmetic Algorithms and Structures for VLSI. Fort Belvoir, VA: Defense Technical Information Center, November 1988. http://dx.doi.org/10.21236/ada203421.

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Browne, M. C., E. M. Clarke, and O. Grumberg. Characterizing Kripke Structures in Temporal Logic. Fort Belvoir, VA: Defense Technical Information Center, December 1987. http://dx.doi.org/10.21236/ada188620.

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Coldren, L. A., A. C. Gossard, C. C. Barron, G. Thompson, and M. Whitehead. Efficient Optical Logic, Interconnections and Processing Using Quantum Confined Structures. Fort Belvoir, VA: Defense Technical Information Center, May 1993. http://dx.doi.org/10.21236/ada265734.

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Singhal, Rahul. Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA). Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.196.

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Baader, Franz. Concept Descriptions with Set Constraints and Cardinality Constraints. Technische Universität Dresden, 2017. http://dx.doi.org/10.25368/2022.232.

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We introduce a new description logic that extends the well-known logic ALCQ by allowing the statement of constraints on role successors that are more general than the qualified number restrictions of ALCQ. To formulate these constraints, we use the quantifier-free fragment of Boolean Algebra with Presburger Arithmetic (QFBAPA), in which one can express Boolean combinations of set constraints and numerical constraints on the cardinalities of sets. Though our new logic is considerably more expressive than ALCQ, we are able to show that the complexity of reasoning in it is the same as in ALCQ, both without and with TBoxes.
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Sgurev, Vassil. Inference Rules, Degrees of Truthfulness and Tautologies in Multivalued Hierarchical Logic with One Real and Two Imaginary Logical Structures. "Prof. Marin Drinov" Publishing House of Bulgarian Academy of Sciences, December 2021. http://dx.doi.org/10.7546/crabs.2021.12.10.

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Baader, Franz, and Felix Distel. A finite basis for the set of EL-implications holding in a finite model. Technische Universität Dresden, 2007. http://dx.doi.org/10.25368/2022.160.

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Formal Concept Analysis (FCA) can be used to analyze data given in the form of a formal context. In particular, FCA provides efficient algorithms for computing a minimal basis of the implications holding in the context. In this paper, we extend classical FCA by considering data that are represented by relational structures rather than formal contexts, and by replacing atomic attributes by complex formulae defined in some logic. After generalizing some of the FCA theory to this more general form of contexts, we instantiate the general framework with attributes defined in the Description Logic (DL) EL, and with relational structures over a signature of unary and binary predicates, i.e., models for EL. In this setting, an implication corresponds to a so-called general concept inclusion axiom (GCI) in EL. The main technical result of this report is that, in EL, for any finite model there is a finite set of implications (GCIs) holding in this model from which all implications (GCIs) holding in the model follow.
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Hwa, Yue-Yi, and Lant Pritchett. Teacher Careers in Education Systems That Are Coherent for Learning: Choose and Curate Toward Commitment to Capable and Committed Teachers (5Cs). Research on Improving Systems of Education (RISE), December 2021. http://dx.doi.org/10.35489/bsg-rise-misc_2021/02.

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How can education authorities and organisations develop empowered, highly respected, strongly performance-normed, contextually embedded teaching professionals who cultivate student learning? This challenge is particularly acute in many low- and middle-income education systems that have successfully expanded school enrolment but struggle to help children master even the basics of reading, writing, and arithmetic. In this primer, we synthesise research from a wide range of academic disciplines and country contexts, and we propose a set of principles for guiding the journey toward an empowered, effective teaching profession. We call these principles the 5Cs: choose and curate toward commitment to capable and committed teachers. These principles are rooted in the fact that teachers and their career structures are embedded in multi-level, multi-component systems that interact in complex ways. We also outline five premises for practice, each highlighting an area in which education authorities and organisations can change the typical status quo approach in order to apply the 5Cs and realise the vision of empowered teaching profession.
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Bano, Masooda, and Daniel Dyonisius. Community-Responsive Education Policies and the Question of Optimality: Decentralisation and District-Level Variation in Policy Adoption and Implementation in Indonesia. Research on Improving Systems of Education (RISE), August 2022. http://dx.doi.org/10.35489/bsg-rise-wp_2022/108.

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Decentralisation, or devolving authority to the third tier of government to prioritise specific policy reforms and manage their implementation, is argued to lead to pro-poor development for a number of reasons: local bureaucrats can better gauge the local needs, be responsive to community demands, and, due to physical proximity, can be more easily held accountable by community members. In the education sector, devolving authority to district government has thus been seen as critical to introducing reforms aimed at increasing access and improving learning outcomes. Based on fieldwork with district-level education bureaucracies, schools, and communities in two districts in the state of West Java in Indonesia, this article shows that decentralisation has indeed led to community-responsive policy-development in Indonesia. The district-level education bureaucracies in both districts did appear to prioritise community preferences when choosing to prioritise specific educational reforms from among many introduced by the national government. However, the optimality of these preferences could be questioned. The prioritised policies are reflective of cultural and religious values or immediate employment considerations of the communities in the two districts, rather than being explicitly focused on improving learning outcomes: the urban district prioritised degree completion, while the rural district prioritised moral education. These preferences might appear sub-optimal if the preference is for education bureaucracies to focus directly on improving literacy and numeracy outcomes. Yet, taking into account the socio-economic context of each district, it becomes easy to see the logic dictating these preferences: the communities and the district government officials are consciously prioritising those education policies for which they foresee direct payoffs. Since improving learning outcomes requires long-term commitment, it appears rational to focus on policies promising more immediate gains, especially when they aim, indirectly and implicitly, to improve actual learning outcomes. Thus, more effective community mobilisation campaigns can be developed if the donor agencies funding them recognise that it is not necessarily the lack of information but the nature of the local incentive structures that shapes communities’ expectations of education. Overall, decentralisation is leading to more context-specific educational policy prioritisation in Indonesia, resulting in the possibility of significant district-level variation in outcomes. Further, looking at the school-level variation in each district, the paper shows that public schools ranked as high performing had students from more privileged socio-economic backgrounds and were catering for communities that had more financial resources to support activities in the school, compared with schools ranked as low performing. Thus, there is a gap to bridge within public schools and not just between public and private schools.
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