Dissertations / Theses: 'Arithmetic and logic structures'

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Gilman, Andrew. "Least-squares optimal interpolation for direct image super-resolution : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Engineering at Massey University, Palmerston North, New Zealand." Massey University, 2009. http://hdl.handle.net/10179/893.

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Image super-resolution aims to produce a higher resolution representation of a scene from an ensemble of low-resolution images that may be warped, aliased, blurred and degraded by noise. There are a variety of methods for performing super-resolution described in the literature, and in general they consist of three major steps: image registration, fusion and deblurring. This thesis proposes a novel method of performing the first two of these steps. The ultimate aim of image super-resolution is to produce a higher-quality image that is visually clearer, sharper and contains more detail than the individual input images. Machine algorithms can not assess images qualitatively and typically use a quantitative error criterion, often least-squares. This thesis aims to optimise leastsquares directly using a fast method, in particular one that can be implemented using linear filters; hence, a closed-form solution is required. The concepts of optimal interpolation and resampling are derived and demonstrated in practice. Optimal filters optimised on one image are shown to perform nearoptimally on other images, suggesting that common image features, such as stepedges, can be used to optimise a near-optimal filter without requiring the knowledge of the ground-truth output. This leads to the construction of a pulse model, which is used to derive filters for resampling non-uniformly sampled images that result from the fusion of registered input images. An experimental comparison shows that a 10th order pulse model-based filter outperforms a number of methods common in the literature. The use of optimal interpolation for image registration linearises an otherwise nonlinear problem, resulting in a direct solution. Experimental analysis is used to show that optimal interpolation-based registration outperforms a number of existing methods, both iterative and direct, at a range of noise levels and for both heavily aliased images and images with a limited degree of aliasing. The proposed method offers flexibility in terms of the size of the region of support, offering a good trade-off in terms of computational complexity and accuracy of registration. Together, optimal interpolation-based registration and fusion are shown to perform fast, direct and effective super-resolution.

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Bhupatiraju, Raja D. V. "A comparative study of high speed adders." Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1175891877.

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Chakrapani, Lakshmi Narasimhan. "Probabilistic boolean logic, arithmetic and architectures." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26706.

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Thesis (Ph.D)--Computing, Georgia Institute of Technology, 2009.
Committee Chair: Palem, Krishna V.; Committee Member: Lim, Sung Kyu; Committee Member: Loh, Gabriel H.; Committee Member: Mudge, Trevor; Committee Member: Yalamanchili, Sudhakar. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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Wang, Shaoyun. "A CORDIC arithmetic processor /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.

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Hamel, Mariah. "Arithmetic structures in random sets." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/2838.

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We prove various results in additive combinatorics for subsets of random sets. In particular we extend Sarkozy's theorem and a theorem of Green on long arithmetic progressions in sumsets to dense subsets of random sets with asymptotic density 0. Our proofs require a transference argument due to Green and Green-Tao which enables us to apply known results for sets of positive upper density to subsets of random sets which have positive relative density. We also prove a density result which states that if a subset of a random set has positive relative density, then the sumset of the subset must have positive upper density in the integers.

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DUARTE, ALESSANDRO BANDEIRA. "LOGIC AND ARITHMETIC IN FREGE´S PHILOSOPHY OF MATHEMATICS." PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO, 2009. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=13942@1.

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PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO
Nos Fundamentos da Aritmética (parágrafo 68), Frege propõe definir explicitamente o operador-abstração ´o número de...´ por meio de extensões e, a partir desta definição, provar o Princípio de Hume (PH). Contudo, a prova imaginada por Frege depende de uma fórmula (BB) não provável no sistema em 1884. Acreditamos que a distinção entre sentido e referência e a introdução dos valores de verdade como objetos foram motivada para justificar a introdução do Axioma IV, a partir do qual um análogo de (BB) é provável. Com (BB) no sistema, a prova do Princípio de Hume estaria garantida. Concomitantemente, percebemos que uma teoria unificada das extensões só é possível com a distinção entre sentido e referência e a introdução dos valores de verdade como objetos. Caso contrário, Frege teria sido obrigado a introduzir uma série de Axiomas V no seu sistema, o que acarretaria problemas com a identidade (Júlio César). Com base nestas considerações, além do fato de que, em 1882, Frege provara as leis básicas da aritmética (carta a Anton Marty), parece-nos perfeitamente plausível que as estas provas foram executadas adicionando-se o PH ao sistema lógico de Begriffsschrift. Mostramos que, nas provas dos axiomas de Peano a partir de PH dentro da conceitografia, nenhum uso é feito de (BB). Destarte, não é necessária a introdução do Axioma IV no sistema e, por conseguinte, não são necessárias a distinção entre sentido e referência e a introdução dos valores de verdade como objetos. Disto, podemos concluir que, provavelmente, a introdução das extensões nos Fundamentos foi um ato tardio; e que Frege não possuía uma prova formal de PH a partir da sua definição explícita. Estes fatos também explicam a demora na publicação das Leis Básicas da Aritmética e o descarte de um manuscrito quase pronto (provavelmente, o livro mencionado na carta a Marty).
In The Foundations of Arithmetic (paragraph 68), Frege proposes to define explicitly the abstraction operator ´the number of …´ by means of extensions and, from this definition, to prove Hume´s Principle (HP). Nevertheless, the proof imagined by Frege depends on a formula (BB), which is not provable in the system in 1884. we believe that the distinction between sense and reference as well as the introduction of Truth-Values as objects were motivated in order to justify the introduction of Axiom IV, from which an analogous of (BB) is provable. With (BB) in the system, the proof of HP would be guaranteed. At the same time, we realize that a unified theory of extensions is only possible with the distinction between sense and reference and the introduction of Truth-Values as objects. Otherwise, Frege would have been obliged to introduce a series of Axioms V in his system, what cause problems regarding the identity (Julius Caesar). Based on these considerations, besides the fact that in 1882 Frege had proved the basic laws of Arithmetic (letter to Anton Marty), it seems perfectly plausible that these proofs carried out by adding to the Begriffsschrift´s logical system. We show that in the proofs of Peano s axioms from HP within the begriffsschrift, (BB) is not used at all. Thus, the introduction of Axiom IV in the system is not necessary and, consequently, neither the distinction between sense and reference nor the introduction of Truth- Values as objects. From these findings we may conclude that probably the introduction of extensions in The Foundations was a late act; and that Frege did not hold a formal proof of HP from his explicit definition. These facts also explain the delay in the publication of the Basic Laws of Arithmetic and the abandon of a manuscript almost finished (probably the book mentioned in the letter to Marty).

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Labrado, Carson. "Exploration of Majority Logic Based Designs for Arithmetic Circuits." UKnowledge, 2017. http://uknowledge.uky.edu/ece_etds/102.

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Since its inception, Moore's Law has been a reliable predictor of computational power. This steady increase in computational power has been due to the ability to fit increasing numbers of transistors in a single chip. A consequence of increasing the number of transistors is also increasing the power consumption. The physical properties of CMOS technologies will make this powerwall unavoidable and will result in severe restrictions to future progress and applications. A potential solution to the problem of rising power demands is to investigate alternative low power nanotechnologies for implementing logic circuits. The intrinsic properties of these emerging nanotechnologies result in them being low power in nature when compared to current CMOS technologies. This thesis specifically highlights quantum dot celluar automata (QCA) and nanomagnetic logic (NML) as just two possible technologies. Designs in NML and QCA are explored for simple arithmetic units such as full adders and subtractors. A new multilayer 5-input majority gate design is proposed for use in NML. Designs of reversible adders are proposed which are easily testable for unidirectional stuck at faults.

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Spenner, Laura. "Quantum logic implementation of unary arithmetic operations with inheritance." Ann Arbor, Mich. : ProQuest, 2008. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:1452767.

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Thesis (M.S. in Computer Engineering)--S.M.U.
Title from PDF title page (viewed Mar. 16, 2009). Source: Masters Abstracts International, Volume: 46-05, page: 2734. Adviser: Mitchell A. Thornton. Includes bibliographical references.

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Katreepalli, Raghava. "Efficient VLSI Implementation of Arithmetic Units and Logic Circuits." OpenSIUC, 2017. https://opensiuc.lib.siu.edu/dissertations/1471.

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Arithmetic units and logic circuits are critical components of any VLSI system. Thus realizing efficient arithmetic units and logic circuits is required for better performance of a data path unit and therefore microprocessor or digital signal processor (DSP). Adders are basic building blocks of any processor or data path application. For the design of high performance processing units, high-speed adders with low power consumption is a requirement. Carry Select Adder (CSA) is known to be one of the fastest adders used in many data processing applications. This first contribution of the dissertation is the design of a new CSA architecture using Manchester carry chain (MCC) in multioutput domino CMOS logic. It employs a novel MCC blocks in a hierarchical approach in the design of the CSA. The proposed MCC block is also extended in designing a power-delay and area efficient Vedic multiplier based on "Urdhva-Tiryakbhyam”. The simulation results shows that the proposed architecture achieves two fold advantages in terms of power-delay product (PDP) and hardware overhead. Apart from adders and multipliers, counters also play a major role in a data path unit. Counters are basic building blocks in many VLSI applications such as timers, memories, ADCs/DACs, frequency dividers etc. It is observed that design of counters has power overhead because of requirement of high power consumption for the clock signal distribution and undesired activity of flip-flops due to presence of clocks. The second contribution of the dissertation is the power efficient design of synchronous counters that reduces the power consumption due to clock distribution for different flip-flops and offers high reliability. The simulation results shows that the proposed counter design has lower power requirement and power-area product than existing counter architectures. Pipelines can be used for achieving high circuit operating speeds. However, as the operating frequency increases, the number of pipeline stages also increase linearly and so the memory elements. The third contribution of the dissertation is the dynamic memory-less pipeline design based on sinusoidal three-phase clocking scheme that reduces the power required by the clock and offers high circuit operating frequencies. Finally, the dissertation presents a novel tool for Boolean-function realization with minimum number of transistor in series. This tool is based on applying a new functional decomposition algorithms to decompose the initial Boolean-function into a network of smaller sub-functions and subsequently generating the final circuit. The effectiveness of proposed technique is estimated using circuit level simulations as well as using automated tool. The number of levels required using proposed technique is reduced by an average of 70% compared to existing techniques.

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Midde, Bharath Reddy. "Design, analysis, and synthesis of 16 bit arithmetic logic unit using reversible logic gate." Thesis, California State University, Long Beach, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10099864.

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In the modern world, an Arithmetic Logic Unit (ALU) is one of the most crucial component of an embedded system and is used in many devices like calculators, cell phones, computers, and so on. An ALU is a multi-functional circuit that conditionally performs one of several possible functions on two operands A and B depending on control inputs. It is nevertheless the main performer of any computing device. This project proposes the design of programmable reversible logic gate structures, targeted for the ALU implementation and their use in the realization of an efficient reversible ALU. This ALU consists of sixteen operations, the arithmetic operations include addition, subtraction, multiplication and the logical operations includes AND, OR, NOT and XOR. All the modules are being designed using the basic reversible gates.

Using reversible logic gates instead of traditional logic AND/OR gates, a reversible ALU is constructed whose function is the same as traditional ALU. Comparing with the number of input bits and the discarded bits of the traditional ALU, the reversible ALU significantly reduces the use and loss of information bits. The proposed reversible 16-bit ALU reuses the information bits and achieves the goal of lowering delay of logic circuits by 42% approximately. Programmable reversible logic gates are realized in Verilog HDL.

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Persson, Daniel. "Arithmetic and hyperbolic structures in string theory." Doctoral thesis, Universite Libre de Bruxelles, 2009. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/210323.

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Résumé anglais:

This thesis consists of an introductory text followed by two separate parts which may be read independently of each other. In Part I we analyze certain hyperbolic structures arising when studying gravity in the vicinity of spacelike singularities (the BKL-limit). In this limit, spatial points decouple and the dynamics exhibits ultralocal behaviour which may be mapped to an auxiliary problem given in terms of a (possibly chaotic) hyperbolic billiard. In all supergravities arising as low-energy limits of string theory or M-theory, the billiard dynamics takes place within the fundamental Weyl chambers of certain hyperbolic Kac-Moody algebras, suggesting that these algebras generate hidden infinite-dimensional symmetries of gravity. We investigate the modification of the billiard dynamics when the original gravitational theory is formulated on a compact spatial manifold of arbitrary topology, revealing fascinating mathematical structures known as galleries. We further use the conjectured hyperbolic symmetry E10 to generate and classify certain cosmological (S-brane) solutions in eleven-dimensional supergravity. Finally, we show in detail that eleven-dimensional supergravity and massive type IIA supergravity are dynamically unified within the framework of a geodesic sigma model for a particle moving on the infinite-dimensional coset space E10/K(E10).

Part II of the thesis is devoted to a study of how (U-)dualities in string theory provide powerful constraints on perturbative and non-perturbative quantum corrections. These dualities are typically given by certain arithmetic groups G(Z) which are conjectured to be preserved in the effective action. The exact couplings are given by moduli-dependent functions which are manifestly invariant under G(Z), known as automorphic forms. We discuss in detail various methods of constructing automorphic forms, with particular emphasis on a special class of functions known as (non-holomorphic) Eisenstein series. We provide detailed examples for the physically relevant cases of SL(2,Z) and SL(3,Z), for which we construct their respective Eisenstein series and compute their (non-abelian) Fourier expansions. We also discuss the possibility that certain generalized Eisenstein series, which are covariant under the maximal compact subgroup K(G), could play a role in determining the exact effective action for toroidally compactified higher derivative corrections. Finally, we propose that in the case of rigid Calabi-Yau compactifications in type IIA string theory, the exact universal hypermultiplet moduli space exhibits a quantum duality group given by the emph{Picard modular group} SU(2,1;Z[i]). To verify this proposal we construct an SU(2,1;Z[i])-invariant Eisenstein series, and we present preliminary results for its Fourier expansion which reveals the expected contributions from D2-brane and NS5-brane instantons.

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Résumé francais:

Cette thèse est composée d'une introduction suivie de deux parties qui peuvent être lues indépendemment. Dans la première partie, nous analysons des structures hyperboliques apparaissant dans l'étude de la gravité au voisinage d'une singularité de type espace (la limite BKL). Dans cette limite, les points spatiaux se découplent et la dynamique suit un comportement ultralocal qui peut être reformulé en termes d'un billiard hyperbolique (qui peut être chaotique). Dans toutes les supergravités qui sont des limites de basse énergie de théories de cordes ou de la théorie M, la dynamique du billiard prend place à l'intérieur des chambres de Weyl fondamentales de certaines algèbres de Kac-Moody hyperboliques, ce qui suggère que ces algèbres correspondent à des symétries cachées de dimension infinie de la gravité. Nous examinons comment la dynamique du billard est modifiée quand la théorie de gravité originale est formulée sur une variété spatiale compacte de topologie arbitraire, révélant ainsi de fascinantes structures mathématiques appelées galleries. De plus, dans le cadre de la supergravité à onze dimensions, nous utilisons la symétrie hyperbolique conjecturée E10 pour engendrer et classifier certaines solutions cosmologiques (S-branes). Finalement, nous montrons en détail que la supergravité à onze dimensions et la supergravité de type IIA massive sont dynamiquement unifiées dans le contexte d'un modèle sigma géodesique pour une particule se déplaçant sur l'espace quotient de dimension infinie E10/K(E10).

La deuxième partie de cette thèse est consacrée à étudier comment les dualités U en théorie des cordes fournissent des contraintes puissantes sur les corrections quantiques perturbatives et non perturbatives. Ces dualités sont typiquement données par des groupes arithmétiques G(Z) dont il est conjecturé qu'ils préservent l'action effective. Les couplages exacts sont donnés par des fonctions des moduli qui sont manifestement invariantes sous G(Z), et qu'on appelle des formes automorphiques. Nous discutons en détail différentes méthodes de construction de ces formes automorphiques, en insistant particulièrement sur une classe spéciale de fonctions appelées séries d'Eisenstein (non holomorphiques). Nous présentons comme exemples les cas de SL(2,Z) et SL(3,Z), qui sont physiquement pertinents. Nous construisons les séries d'Eisenstein correspondantes et leurs expansions de Fourier (non abéliennes). Nous discutons également la possibilité que certaines séries d'Eisenstein généralisées, qui sont covariantes sous le sous-groupe compact maximal, pourraient jouer un rôle dans la détermination des actions effectives exactes pour les théories incluant des corrections de dérivées supérieures compactifiées sur des tores.

Doctorat en Sciences
info:eu-repo/semantics/nonPublished

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Rajagopalan, Kamal. "An FPGA architecture for improved arithmetic performance /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16460.pdf.

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Manickavasagam, SenthilKumar. ""a+b" arithmetic theory and implementation." Ohio : Ohio University, 1996. http://www.ohiolink.edu/etd/view.cgi?ohiou1178051605.

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Hanss, Michael. "Applied fuzzy arithmetic : an introduction with engineering applications /." Berlin [u.a.] : Springer, 2005. http://www.loc.gov/catdir/enhancements/fy0662/2004117177-d.html.

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Dittrich, Jonathan Georg [Verfasser], and Hannes [Akademischer Betreuer] Leitgeb. "Paradox, arithmetic and nontransitive logic / Jonathan Georg Dittrich ; Betreuer: Hannes Leitgeb." München : Universitätsbibliothek der Ludwig-Maximilians-Universität, 2020. http://d-nb.info/1218466782/34.

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Plazas, Jorge. "Arithmetic structures on noncommutative tori with real multiplication." [S.l.] : [s.n.], 2006. http://deposit.ddb.de/cgi-bin/dokserv?idn=982902220.

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Carnovale, Marc. "Arithmetic Structures in Small Subsets of Euclidean Space." The Ohio State University, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1555657038785892.

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Kabiri, Chimeh Mozhgan. "Data structures for SIMD logic simulation." Thesis, University of Glasgow, 2016. http://theses.gla.ac.uk/7521/.

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Due to the growth of design size and complexity, design verification is an important aspect of the Logic Circuit development process. The purpose of verification is to validate that the design meets the system requirements and specification. This is done by either functional or formal verification. The most popular approach to functional verification is the use of simulation based techniques. Using models to replicate the behaviour of an actual system is called simulation. In this thesis, a software/data structure architecture without explicit locks is proposed to accelerate logic gate circuit simulation. We call thus system ZSIM. The ZSIM software architecture simulator targets low cost SIMD multi-core machines. Its performance is evaluated on the Intel Xeon Phi and 2 other machines (Intel Xeon and AMD Opteron). The aim of these experiments is to: • Verify that the data structure used allows SIMD acceleration, particularly on machines with gather instructions ( section 5.3.1). • Verify that, on sufficiently large circuits, substantial gains could be made from multicore parallelism ( section 5.3.2 ). • Show that a simulator using this approach out-performs an existing commercial simulator on a standard workstation ( section 5.3.3 ). • Show that the performance on a cheap Xeon Phi card is competitive with results reported elsewhere on much more expensive super-computers ( section 5.3.5 ). To evaluate the ZSIM, two types of test circuits were used: 1. Circuits from the IWLS benchmark suit [1] which allow direct comparison with other published studies of parallel simulators.2. Circuits generated by a parametrised circuit synthesizer. The synthesizer used an algorithm that has been shown to generate circuits that are statistically representative of real logic circuits. The synthesizer allowed testing of a range of very large circuits, larger than the ones for which it was possible to obtain open source files. The experimental results show that with SIMD acceleration and multicore, ZSIM gained a peak parallelisation factor of 300 on Intel Xeon Phi and 11 on Intel Xeon. With only SIMD enabled, ZSIM achieved a maximum parallelistion gain of 10 on Intel Xeon Phi and 4 on Intel Xeon. Furthermore, it was shown that this software architecture simulator running on a SIMD machine is much faster than, and can handle much bigger circuits than a widely used commercial simulator (Xilinx) running on a workstation. The performance achieved by ZSIM was also compared with similar pre-existing work on logic simulation targeting GPUs and supercomputers. It was shown that ZSIM simulator running on a Xeon Phi machine gives comparable simulation performance to the IBM Blue Gene supercomputer at very much lower cost. The experimental results have shown that the Xeon Phi is competitive with simulation on GPUs and allows the handling of much larger circuits than have been reported for GPU simulation. When targeting Xeon Phi architecture, the automatic cache management of the Xeon Phi, handles and manages the on-chip local store without any explicit mention of the local store being made in the architecture of the simulator itself. However, targeting GPUs, explicit cache management in program increases the complexity of the software architecture. Furthermore, one of the strongest points of the ZSIM simulator is its portability. Note that the same code was tested on both AMD and Xeon Phi machines. The same architecture that efficiently performs on Xeon Phi, was ported into a 64 core NUMA AMD Opteron. To conclude, the two main achievements are restated as following: The primary achievement of this work was proving that the ZSIM architecture was faster than previously published logic simulators on low cost platforms. The secondary achievement was the development of a synthetic testing suite that went beyond the scale range that was previously publicly available, based on prior work that showed the synthesis technique is valid.

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Kannan, Balaji Navalpakkam. "The design of an IC half precision floating point Arithmetic Logic Unit." Connect to this title online, 2009. http://etd.lib.clemson.edu/documents/1263396747/.

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Choi, Jae Hun. "High speed and low area techniques for computer arithmetic operations /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004236.

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King, Tim. "Effective Algorithms for the Satisfiability of Quantifier-Free Formulas Over Linear Real and Integer Arithmetic." Thesis, New York University, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3665163.

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A core technique of modern tools for formally reasoning about computing systems is generating and dispatching queries to automated theorem provers, including Satisfiability Modulo Theories (SMT) provers. SMT provers aim at the tight integration of decision procedures for propositional satisfiability and decision procedures for fixed first-order theories – known as theory solvers. This thesis presents several advancements in the design and implementation of theory solvers for quantifier-free linear real, integer, and mixed integer and real arithmetic. These are implemented within the SMT system CVC4. We begin by formally describing the Satisfiability Modulo Theories problem and the role of theory solvers within CVC4. We discuss known techniques for building solvers for quantifier-free linear real, integer, and mixed integer and real arithmetic around the Simplex for SMT algorithm. We give several small improvements to theory solvers using this algorithm and describe the implementation and theory of this algorithm in detail. To extend the class of problems that the theory solver can robustly support, we borrow and adapt several techniques from linear programming (LP) and mixed integer programming (MIP) solvers which come from the tradition of optimization. We propose a new decision procedure for quantifier-free linear real arithmetic that replaces the Simplex for SMT algorithm with a variant of the Simplex algorithm that performs a form of optimization – minimizing the sum of infeasibilties. In this thesis, we additionally describe techniques for leveraging LP and MIP solvers to improve the performance of SMT solvers without compromising correctness. Previous efforts to leverage such solvers in the context of SMT have concluded that in addition to being potentially unsound, such solvers are too heavyweight to compete in the context of SMT. We present an empirical comparison against other state-of-the-art SMT tools to demonstrate the effectiveness of the proposed solutions.

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Matsuura, Akihiro. "Combinatorial Structures in Finite Automata, CNF Satisfiability and Arithmetic Computation." 京都大学 (Kyoto University), 2002. http://hdl.handle.net/2433/149387.

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Guo, Xinyu. "A high-throughput divider based on output prediction logic /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/15462.

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Martinez-Mascarua, Carlos Mario. "Syntactic and semantic structures in COCOLOG logic control." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0017/NQ44512.pdf.

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Martínez-Mascarúa, Carlos Mario. "Syntactic and semantic structures in cocolog logic control." Thesis, McGill University, 1997. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=34757.

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The research presented in this thesis is formulated within the Conditional Observer and Controller Logic (COCOLOG) framework. COCOLOG is a family of first order languages and associated theories for the design and implementation of controllers for discrete event systems (DESs).
The opening part of this thesis presents a high level formulation of COCOLOG called Macro COCOLOG. First, we present the theory of Macro COCOLOG languages, a framework for the enhancement of the original COCOLOG language via definitional constructions. Second, we present the theory of Macro COCOLOG actions, a framework for the enhancement of COCOLOG allowing the utilisation of hierarchically aggregated control actions.
In this thesis Macro COCOLOG is applied to a pair of examples: the control of the motion of a mobile robot and the flow of water through a tank.
The next question addressed in the thesis is the possibility of expanding the original COCOLOG theories in various ways concerning the fundamental issues of the arithmetic system and the notion of reachability in DESs as expressed in COCOLOG. Specifically, the fundamental nature of the reachability predicate, Rbl(·,·,·), is explored, and found to be completely determined by notions axiomatised in subtheories of the original COCOLOG theory. This result effectively reduces the complexity of the proofs originally involving Rbl(·,·,·).
Following this line of thought, two sets of Macro languages and associated theories are developed which are shown to be as powerful (in terms of expressiveness and deductive scope) as the original COCOLOG theories and hence, necessarily, as powerful as Markovian fragment COCOLOG theories.
A final result along these lines is that the control law itself (originally expressed in a set of extra logical Conditional Control Rules) can be incorporated into the COCOLOG theories via function symbol definition.
The efficient implementation of COCOLOG controllers serves as a motivation for the final two chapters of the thesis. A basic result in this chapter is that a COCOLOG controller may itself be realized as a DES since, for any COCOLOG controller, it is shown that one may generate a finite state machine realizing that controller. This realization can then be used for real time (i.e. reactive) control. (Abstract shortened by UMI.)

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Das, Shamik 1977. "Design and implementation of three-dimensional logic structures." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/9078.

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Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
Includes bibliographical references (leaves 89-91).
In this thesis, a computer-aided-design (CAD) system is developed that assists in the design of novel three-dimensional integrated circuits. The software tools allow for the specification of a multilayer transistor circuit by means that are readily accessible to those familiar with two-dimensional CMOS VLSI design. This software system provides desirable features such as SPICE circuit extraction and the ability to produce the design formats necessary for automated fabrication (e.g. mask specifications for lithography or Gerber data for inkjet printing). Finally, in this thesis, the software tools are used to design a ring oscillator, a 3-D static RAM, and a 3-D cellular automata machine.
by Shamik Das.
S.B.and M.Eng.

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27

Knapp, Greg. "Minkowski's Linear Forms Theorem in Elementary Function Arithmetic." Case Western Reserve University School of Graduate Studies / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=case1495545998803274.

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28

Ratan, Amrita. "Hardware Modules for Safe Integer and Floating-Point Arithmetic." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316.

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29

Straßburger, Lutz. "Linear Logic and Noncommutativity in the Calculus of Structures." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2003. http://nbn-resolving.de/urn:nbn:de:swb:14-1063208959250-72937.

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In this thesis I study several deductive systems for linear logic, its fragments, and some noncommutative extensions. All systems will be designed within the calculus of structures, which is a proof theoretical formalism for specifying logical systems, in the tradition of Hilbert's formalism, natural deduction, and the sequent calculus. Systems in the calculus of structures are based on two simple principles: deep inference and top-down symmetry. Together they have remarkable consequences for the properties of the logical systems. For example, for linear logic it is possible to design a deductive system, in which all rules are local. In particular, the contraction rule is reduced to an atomic version, and there is no global promotion rule. I will also show an extension of multiplicative exponential linear logic by a noncommutative, self-dual connective which is not representable in the sequent calculus. All systems enjoy the cut elimination property. Moreover, this can be proved independently from the sequent calculus via techniques that are based on the new top-down symmetry. Furthermore, for all systems, I will present several decomposition theorems which constitute a new type of normal form for derivations.

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30

St, Clair Ralf. "Practical logic, curriculum structures in an adult education program." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape3/PQDD_0015/NQ48719.pdf.

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31

Porter, Harry H. "A logic-based grammar formalism incorporating feature-structures and inheritance /." Full text open access at:, 1988. http://content.ohsu.edu/u?/etd,181.

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32

Melnyk, Oleksandr, Viktoriia Kozarevych, Олександр Степанович Мельник, and Вікторія Олександрівна Козаревич. "Nanoschemes with configurated structures." Thesis, National Aviation University, 2021. https://er.nau.edu.ua/handle/NAU/50240.

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Пакулов Н. Н. Мажоритарный принцип построения надежных узлов и устройств ЦВМ. – М.: Сов.радио, 1974. – 184 с. 2. Melnyk O.S, Kozarevych V.O, Sobchenko А. Synthesis of nanoelectronic devices with programmable structures. // Вісник Київського національного університету ім. Тараса Шевченка. Сер.: Радіофізика та електроніка. – Київ: Вид-во Київського держ. ун-ту ім. Т.Г. Шевченка, 2014. – № 21. – С. 78-81..
The contradictions between specialization and universality can be eliminated by developing nanoschemas with configured structures (NSKS), the algorithms of which can be changed at the request of the developer of specific computer equipment, ie by creating arithmetic-logic circuits with programmable logic. The development of the theory and practice of the majority principle is currently an urgent problem, because the nanoelectronic design of computer systems with configured structures significantly reduces their cost and greatly simplifies the stage of automated systems design. One programmable nanoscheme replaces from 30 to 150 integrated circuits of average degree of integration.
Протиріччя між спеціалізацією та універсальністю можна усунути шляхом розробки наносхем із налаштованими структурами (NSKS), алгоритмами які можуть бути змінені за бажанням розробника конкретного комп'ютерного обладнання, тобто шляхом створення арифметико-логічних схем із програмованою логікою. Розвитком теорії та практики принципу більшості є. В даний час актуальна проблема, оскільки наноелектронне проектування комп'ютерних систем з налаштованими структурами значно знижує їх вартість і значно спрощує етап проектування автоматизованих систем. Одна програмована наносхема замінює з 30 до 150 інтегральних схем середнього ступеня інтеграції.

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33

Aranibar, Luis Alfonso Quiroga. "Learning fuzzy logic from examples." Ohio : Ohio University, 1994. http://www.ohiolink.edu/etd/view.cgi?ohiou1176495652.

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34

Rönchen, Philipp. "Constraints of Binary Simple Homogeneous Structures." Thesis, Uppsala universitet, Algebra och geometri, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-361217.

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35

Morrison, Matthew Arthur. "Design of a Reversible ALU Based on Novel Reversible Logic Structures." Scholar Commons, 2012. http://scholarcommons.usf.edu/etd/4175.

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Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to the previous Swap gate is presented. Next, a novel 3*3 programmable UPG gate capable of calculating the fundamental logic calculations is presented and verified, and its advantages over the Toffoli and Peres gates are discussed. The UPG is then implemented in a reduced design for calculating n-bit AND, n-bit OR and n-bit ZERO calculations. Then, two 3*3 RMUX gates capable of multiplexing two input values with reduced quantum cost and delay compared to the previously existing Fredkin gate is presented and verified. Next, 4*4 reversible gate is presented and verified which is capable of producing the calculations necessary for two-bit comparisons. The UPG and RC are implemented in the design of novel sequential and tree-based comparators. Then, two novel 4*4 reversible logic gates (MRG and PAOG) are proposed with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. A 5*5 structure (MG) is proposed that extends the capabilities of both the MRG and PAOG. The comparator designs are verified and its advantages to previous designs are discussed. Then, reversible implementations of ripple-carry, carry-select and Kogge-Stone carry look-ahead adders are analyzed and compared. Next, implementations of the Kogge-Stone adder with sparsity-4, 8 and 16 were designed, verified and compared. The enhanced sparsity-4 Kogge-Stone adder with ripple-carry adders was selected as the best design, and its implemented in the design of a 32-bit arithmetic logic unit is demonstrated. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed.

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Singhal, Rahul. "Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA)." PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/196.

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Semiconductor industry seems to approach a wall where physical geometry and power density issues could possibly render the device fabrication infeasible. Quantum-dot Cellular Automata (QCA) is a new nanotechnology that claims to offer the potential of manufacturing even denser integrated circuits, which can operate at high frequencies and low power consumption. In QCA technology, the signal propagation occurs as a result of electrostatic interaction among the electrons as opposed to flow to the electrons in a wire. The basic building block of QCA technology is a QCA cell which encodes binary information with the relative position of electrons in it. A QCA cell can be used either as a wire or as logic. In QCA, the directionality of the signal flow is controlled by phase-shifted electric field generated on a separate layer than QCA cell layer. This process is called clocking of QCA circuits. The logic realization using regular structures such as PLAs have played a significant role in the semiconductor field due to their manufacturability, behavioral predictability and the ease of logic mapping. Along with these benefits, regular structures in QCA's would allow for uniform QCA clocking structure. The clocking structure is important because the pioneers of QCA technology propose it to be fabricated in CMOS technology. This thesis presents a detailed design implementation and a comparative analysis of logic realization using regular structures, namely Shannon-Lattices and PLAs for QCAs. A software tool was developed as a part of this research, which automatically generates complete QCA-Shannon-Lattice and QCA-PLA layouts for single-output Boolean functions based on an input macro-cell library. The equations for latency and throughput for the new QCA-PLA and QCA-Shannon-Lattice design implementations were also formulated. The correctness of the equations was verified by performing simulations of the tool-generate layouts with QCADesigner. A brief design trade-off analysis between the tool-generated regular structure implementation and the unstructured custom layout in QCA is presented for the full-adder circuit.

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37

Engström, Adam. "Computations in Prime Fields using Gaussian Integers." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7007.

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In this thesis it is investigated if representing a field Zp, p = 1 (mod 4) prime, by another field Z[i]/ < a + bi > over the gaussian integers, with p = a2 + b2, results in arithmetic architectures using a smaller number of logic gates. Only bit parallell architectures are considered and the programs Espresso and SIS are used for boolean minimization of the architectures. When counting gates only NAND, NOR and inverters are used.

Two arithmetic operations are investigated, addition and multiplication. For addition the architecture over Z[i]/ < a+bi > uses a significantly greater number of gates compared with an architecture over Zp. For multiplication the architecture using gaussian integers uses a few less gates than the architecture over Zp for p = 5 and for p = 17 and only a few more gates when p = 13. Only the values 5, 13, 17 have been compared for multiplication. For addition 12 values, ranging from 5 to 525313, have been compared.

It is also shown that using a blif model as input architecture to SIS yields much better performance, compared to a truth table architecture, when minimizing.

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38

Edalath, Sanooj Sadique. "Fuzzy Logic Seismic Vibration Control of Buildings." University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1335462916.

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39

Malca, Edgar Omar Otiniano. "Some aspects of introductory continuous logic." reponame:Repositório Institucional da UFABC, 2015.

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Orientador: Prof. Dr. Vinicius Cifú Lopes
Dissertação (mestrado) - Universidade Federal do ABC, Programa de Pós-Graduação em Matemática , 2015.
We study metric structures by examining their model-theoretic properties under the view of continuous logic. Also, we compare three of those structures by ultraproduct techniques. In particular, we give characteristics of Urysohn¿s space among separable metric spaces.

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40

Huang, Walter. "Implementation of adaptive digital FIR and reprogrammable mixed-signal filters using distributed arithmetic." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31653.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Anderson, David V.; Committee Member: Ferri, Bonnie H.; Committee Member: Hasler, Paul E.; Committee Member: Kang, Sung Ha; Committee Member: McClellan, James H.; Committee Member: Wolf, Wayne H. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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41

Aratake, Hisashi. "Sheaves of Structures, Heyting-Valued Structures, and a Generalization of Łoś's Theorem." Doctoral thesis, Kyoto University, 2021. http://hdl.handle.net/2433/265174.

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42

Voigt, Marco [Verfasser], and Christoph [Akademischer Betreuer] Weidenbach. "Decidable fragments of first-order logic and of first-order linear arithmetic with uninterpreted predicates / Marco Voigt ; Betreuer: Christoph Weidenbach." Saarbrücken : Saarländische Universitäts- und Landesbibliothek, 2019. http://d-nb.info/1194928390/34.

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43

Orlando, Gerardo. "Efficient elliptic curve processor architectures for field programmable logic." Link to electronic thesis, 2002. http://www.wpi.edu/Pubs/ETD/Available/etd-0327102-103635.

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44

Ghahremani, Azghandi Nargess. "Petri nets, probability and event structures." Thesis, University of Edinburgh, 2014. http://hdl.handle.net/1842/9936.

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Models of true concurrency have gained a lot of interest over the last decades as models of concurrent or distributed systems which avoid the well-known problem of state space explosion of the interleaving models. In this thesis, we study such models from two perspectives. Firstly, we study the relation between Petri nets and stable event structures. Petri nets can be considered as one of the most general and perhaps wide-spread models of true concurrency. Event structures on the other hand, are simpler models of true concurrency with explicit causality and conflict relations. Stable event structures expand the class of event structures by allowing events to be enabled in more than one way. While the relation between Petri nets and event structures is well understood, the relation between Petri nets and stable event structures has not been studied explicitly. We define a new and more compact unfoldings of safe Petri nets which is directly translatable to stable event structures. In addition, the notion of complete finite prefix is defined for compact unfoldings, making the existing model checking algorithms applicable to them. We present algorithms for constructing the compact unfoldings and their complete finite prefix. Secondly, we study probabilistic models of true concurrency. We extend the definition of probabilistic event structures as defined by Abbes and Benveniste to a newly defined class of stable event structures, namely, jump-free stable event structures arising from Petri nets (characterised and referred to as net-driven). This requires defining the fundamental concept of branching cells in probabilistic event structures, for jump-free net-driven stable event structures, and by proving the existence of an isomorphism among the branching cells of these systems, we show that the latter benefit from the related results of the former models. We then move on to defining a probabilistic logic over probabilistic event structures (PESL). To our best knowledge, this is the first probabilistic logic of true concurrency. We show examples of expressivity achieved by PESL, which in particular include properties related to synchronisation in the system. This is followed by the model checking algorithm for PESL for finite event structures. Finally, we present a logic over stable event structures (SEL) along with an account of its expressivity and its model checking algorithm for finite stable event structures.

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45

Hessel, Günther, Frank-Peter Weiß, and Wilfried Schmitt. "Acoustic Leak Detection at Complicated Geometrical Structures Using Fuzzy Logic and Neural Networks." Forschungszentrum Dresden, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:d120-qucosa-32699.

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Methods of acoustic leak monitoring are of great practical interest for the safety of pressure vessels and pipe lines not only at the primary circuit of nuclear power plants. In this report some aspects of acoustic leak localization at complicated three-dimensional topologies for the case of leakage monitoring at the reactor vessel head of a VVER-440 are discussed. An acoustic method based on pattern recognition is being developed. During the learning phase, the localization classifier is trained with sound patterns that are generated with simulated leaks at all locations endangered by leak. After training unknown leak positions can be recognized through comparison with the training patterns. The sound patterns of the simulated leaks are simultaneously detected with an AE-sensor array and with high frequency microphones measuring structureborne sound and airborne noise, respectively. The initial results show the used classifiers principally to be capable of detecting and locating leaks, but they also show that further investigations are necessary to develop a reliable method.

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46

Hessel, Günther, Frank-Peter Weiß, and Wilfried Schmitt. "Acoustic Leak Detection at Complicated Geometrical Structures Using Fuzzy Logic and Neural Networks." Forschungszentrum Rossendorf, 1993. https://hzdr.qucosa.de/id/qucosa%3A22096.

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Methods of acoustic leak monitoring are of great practical interest for the safety of pressure vessels and pipe lines not only at the primary circuit of nuclear power plants. In this report some aspects of acoustic leak localization at complicated three-dimensional topologies for the case of leakage monitoring at the reactor vessel head of a VVER-440 are discussed. An acoustic method based on pattern recognition is being developed. During the learning phase, the localization classifier is trained with sound patterns that are generated with simulated leaks at all locations endangered by leak. After training unknown leak positions can be recognized through comparison with the training patterns. The sound patterns of the simulated leaks are simultaneously detected with an AE-sensor array and with high frequency microphones measuring structureborne sound and airborne noise, respectively. The initial results show the used classifiers principally to be capable of detecting and locating leaks, but they also show that further investigations are necessary to develop a reliable method.

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47

Blot, Valentin. "Game semantics and realizability for classical logic." Thesis, Lyon, École normale supérieure, 2014. http://www.theses.fr/2014ENSL0945/document.

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Cette thèse étudie deux modèles de réalisabilité pour la logique classique construits sur la sémantique des jeux HO, interprétant la logique, l'arithmétique et l'analyse classiques directement par des programmes manipulant un espace de stockage d'ordre supérieur.La non-innocence en jeux HO autorise les références d'ordre supérieur, et le non parenthésage révèle la CPS des jeux HO et fournit une catégorie de continuations dans laquelle interpréter le lambda-mu calcul de Parigot. Deux modèles de réalisabilité sont construits sur cette interprétation calculatoire directe des preuves classiques.Le premier repose sur l'orthogonalité, comme celui de Krivine, mais il est simplement typé et au premier ordre. En l'absence de codage de l'absurdité au second ordre, une mu-variable libre dans les réaliseurs permet l'extraction. Nous définissons un bar-récurseur et prouvons qu'il réalise l'axiome du choix dépendant, utilisant deux conséquences de la structure de CPO du modèle de jeux: toute fonction sur les entiers (même non calculable) existe dans le modèle, et toute fonctionnelle sur des séquences est Scott-continue. La bar-récursion est habituellement utilisée pour réaliser intuitionnistiquement le « double negation shift » et en déduire la traduction négative de l'axiome du choix. Ici, nous réalisons directement l'axiome du choix dans un cadre classique.Le second, très spécifique au modèle de jeux, repose sur des conditions de gain: des ensembles de positions d'un jeu munis de propriétés de cohérence. Un réaliseur est alors une stratégie dont les positions sont toutes gagnantes
This thesis investigates two realizability models for classical logic built on HO game semantics. The main motivation is to have a direct computational interpretation of classical logic, arithmetic and analysis with programs manipulating a higher-order store.Relaxing the innocence condition in HO games provides higher-order references, and dropping the well-bracketing of strategies reveals the CPS of HO games and gives a category of continuations in which we can interpret Parigot's lambda-mu calculus. This permits a direct computational interpretation of classical proofs from which we build two realizability models.The first model is orthogonality-based, as the one of Krivine. However, it is simply-typed and first-order. This means that we do not use a second-order coding of falsity, and extraction is handled by considering realizers with a free mu-variable. We provide a bar-recursor in this model and prove that it realizes the axiom of dependent choice, relying on two consequences of the CPO structure of the games model: every function on natural numbers (possibly non computable) exists in the model, and every functional on sequences is Scott-continuous. Usually, bar-recursion is used to intuitionistically realize the double negation shift and consequently the negative translation of the axiom of choice. Here, we directly realize the axiom of choice in a classical setting.The second model relies on winning conditions and is very specific to the games model. A winning condition is a set of positions in a game which satisfies some coherence properties, and a realizer of a formula is then a strategy which positions are all winning

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48

Sekercioglu, Ahmet, and ahmet@hyperion ctie monash edu au. "Fuzzy logic control techniques and structures for Asynchronous Transfer Mode (ATM) based multimedia networks." Swinburne University of Technology, 1999. http://adt.lib.swin.edu.au./public/adt-VSWT20050411.130014.

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The research presented in this thesis aims to demonstrate that fuzzy logic is a useful tool for developing mechanisms for controlling traffc flow in ATM based multimedia networks to maintain quality of service (QoS) requirements and maximize resource utilization. The study first proposes a hierarchical, multilevel control structure for ATM networks to exploit the reported strengths of fuzzy logic at various control levels. Then, an extensive development and evaluation is presented for a subset of the proposed control architecture at the congestion control level. An ATM based multimedia network must have quite sophisticated traffc control capabilities to effectively handle the requirements of a dynamically varying mixture of voice, video and data services while meeting the required levels of performance. Feedback control techniques have an essential role for the effective and efficient management of the resources of ATM networks. However, development of conventional feedback control techniques relies on the availability of analytical system models. The characteristics of ATM networks and the complexity of service requirements cause the analytical modeling to be very difficult, if not impossible. The lack of realistic dynamic explicit models leads to substantial problems in developing control solutions for B-ISDN networks. This limits the ability of conventional techniques to directly address the control objectives for ATM networks. In the literature, several connection admission and congestion control methods for B-ISDN networks have been reported, and these have achieved mixed success. Usually they either assume heavily simplified models, or they are too complicated to implement, mainly derived using probabilistic (steady-state) models. Fuzzy logic controllers, on the other hand, have been applied successfully to the task of controlling systems for which analytical models are not easily obtainable. Fuzzy logic control is a knowledge-based control strategy that can be utilized when an explicit model of a system is not available or, the model itself, if available, is highly complex and nonlinear. In this case, the problem of control system design is based on qualitative and/or empirically acquired knowledge regarding the operation of the system. Representation of qualitative or empirically acquired knowledge in a fuzzy logic controller is achieved by linguistic expressions in the form of fuzzy relational equations. By using fuzzy relational equations, classifications related to system parameters can be derived without explicit description. The thesis presents a new predictive congestion control scheme, Fuzzy Explicit Rate Marking (FERM), which aims to avoid congestion, and by doing so minimize the cell losses, attain high server utilization, and maintain the fair use of links. The performance of the FERM scheme is extremely competitive with that of control schemes developed using traditional methods over a considerable period of time. The results of the study demonstrate that fuzzy logic control is a highly effective design tool for this type of problems, relative to the traditional methods. When controlled systems are highly nonlinear and complex, it keeps the human insight alive and accessible at the lower levels of the control hierarchy, and so higher levels can be built on this understanding. Additionally, the FERM scheme has been extended to adaptively tune (A-FERM) so that continuous automatic tuning of the parameters can be achieved, and thus be more adaptive to system changes leading to better utilization of network bandwidth. This achieves a level of robustness that is not exhibited by other congestion control schemes reported in the literature. In this work, the focus is on ATM networks rather than IP based networks. For historical reasons, and due to fundamental philosophical differences in the (earlier) approach to congestion control, the research for control of TCP/IP and ATM based networks proceeded separately. However, some convergence between them has recently become evident. In the TCP/IP literature proposals have appeared on active queue management in routers, and Explicit Congestion Notication (ECN) for IP. It is reasonably expected that, the algorithms developed in this study will be applicable to IP based multimedia networks as well.

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49

Kaplan, Elliot. "Initial Embeddings in the Surreal Number Tree." Ohio University Honors Tutorial College / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ouhonors1429615758.

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50

Conroy, Justin Anderson. "Analysis of adaptive neuro-fuzzy network structures." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/19684.

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Dissertations / Theses on the topic 'Arithmetic and logic structures'

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