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1
Thapen, Neil. "Structures interpretable in models of bounded arithmetic." Annals of Pure and Applied Logic 136, no. 3 (November 2005): 247–66. http://dx.doi.org/10.1016/j.apal.2005.04.005.
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Teichmann, Ph, J. Fischer, F. Chouard, and D. Schmitt-Landsiedel. "Design issues of arithmetic structures in adiabatic logic." Advances in Radio Science 5 (June 13, 2007): 291–95. http://dx.doi.org/10.5194/ars-5-291-2007.
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Abstract. Since adiabatic logic uses a supply that incorporates both supply voltage and clock signal in one line, adiabatic logic systems have a built-in micro-pipelined architecture. Considering this fact, different design constraints have to be observed compared to static CMOS designs. Complex arithmetic building blocks, like multipliers, mainly consist of adders. Therefore, a comparison of adder structures is performed. Based on these results, multipliers and complex systems can be built. A Discrete Cosine Transformation (DCT) is taken as example for an arithmetic system. Comparing an adiabatic logic implementation of a DCT to its static CMOS counterpart, a significant saving factor of more than 10 can be achieved with the adiabatic system.
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Mortensen, Chris. "Inconsistent nonstandard arithmetic." Journal of Symbolic Logic 52, no. 2 (June 1987): 512–18. http://dx.doi.org/10.2307/2274397.
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AbstractThis paper continues the investigation of inconsistent arithmetical structures. In §2 the basic notion of a model with identity is defined, and results needed from elsewhere are cited. In §3 several nonisomorphic inconsistent models with identity which extend the (=, <) theory of the usual classical denumerable nonstandard model of arithmetic are exhibited. In §4 inconsistent nonstandard models of the classical theory of finite rings and fields modulo m, i.e. Zm, are briefly considered. In §5 two models modulo an infinite nonstandard number are considered. In the first, it is shown how to model inconsistently the arithmetic of the rationals with all names included, a strengthening of earlier results. In the second, all inconsistency is confined to the nonstandard integers, and the effects on Fermat's Last Theorem are considered. It is concluded that the prospects for a good inconsistent theory of fields may be limited.
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Montalbán, Antonio. "A fixed point for the jump operator on structures." Journal of Symbolic Logic 78, no. 2 (June 2013): 425–38. http://dx.doi.org/10.2178/jsl.7802050.
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AbstractAssuming that 0# exists, we prove that there is a structure that can effectively interpret its own jump. In particular, we get a structure such thatwhere is the set of Turing degrees which compute a copy of More interesting than the result itself is its unexpected complexity. We prove that higher-order arithmetic, which is the union of full “nth-order arithmetic for all n, cannot prove the existence of such a structure.
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Bès, Alexis, and Denis Richard. "Undecidable extensions of Skolem arithmetic." Journal of Symbolic Logic 63, no. 2 (June 1998): 379–401. http://dx.doi.org/10.2307/2586837.
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AbstractLet be the restriction of usual order relation to integers which are primes or squares of primes, and let ⊥ denote the coprimeness predicate. The elementary theory of is undecidable. Now denote by <π the restriction of order to primary numbers. All arithmetical relations restricted to primary numbers are definable in the structure (ℕ; ⊥, <π). Furthermore, the structures (ℕ; ∣, <π) (ℕ; =, ×, <π) and (ℕ; =, +, ×) are interdefinable.
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Shore, Richard A. "Local Definitions in Degree Structures: The Turing Jump, Hyperdegrees and Beyond." Bulletin of Symbolic Logic 13, no. 2 (June 2007): 226–39. http://dx.doi.org/10.2178/bsl/1185803806.
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AbstractThere are Π5 formulas in the language of the Turing degrees, D, with ≤, ⋁ and ⋀, that define the relations x″ ≤ y″, x″ = y″ and so x ∈ L2(y) = {x ≥ y ∣ x″ = y″} in any jump ideal containing 0(ω). There are also Σ6 & Π6 and Π8 formulas that define the relations w = x″ and w = x′, respectively, in any such ideal I. In the language with just ≤ the quantifier complexity of each of these definitions increases by one. On the other hand, no Π2 or Σ2 formula in the language with just ≤ defines L2 or x ∈ L2(y). Our arguments and constructions are purely degree theoretic without any appeals to absoluteness considerations, set theoretic methods or coding of models of arithmetic. As a corollary, we see that every automorphism of I is fixed on every degree above 0″ and every relation on I that is invariant under double jump or joining with 0″ is definable over I if and only if it is definable in second order arithmetic with set quantification ranging over sets whose degrees are in I. Similar direct coding arguments show that every hyperjump ideal I is rigid and biinterpretable with second order arithmetic with set quantification ranging over sets with hyperdegrees in I. Analogous results hold for various coarser degree structures.
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MCLARTY, COLIN. "THE LARGE STRUCTURES OF GROTHENDIECK FOUNDED ON FINITE-ORDER ARITHMETIC." Review of Symbolic Logic 13, no. 2 (August 2, 2019): 296–325. http://dx.doi.org/10.1017/s1755020319000340.
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AbstractThe large-structure tools of cohomology including toposes and derived categories stay close to arithmetic in practice, yet published foundations for them go beyond ZFC in logical strength. We reduce the gap by founding all the theorems of Grothendieck’s SGA, plus derived categories, at the level of Finite-Order Arithmetic, far below ZFC. This is the weakest possible foundation for the large-structure tools because one elementary topos of sets with infinity is already this strong.
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Bhuvana, B. P., and V. S. Kanchana Bhaaskaran. "Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures." Journal of Circuits, Systems and Computers 29, no. 01 (April 23, 2019): 2050016. http://dx.doi.org/10.1142/s0218126620500164.
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This paper presents the adiabatic logic called 2[Formula: see text]–[Formula: see text]–2[Formula: see text], which can operate with less number of transistors and high energy efficiency than the existing circuit styles. It is a dual rail logic operated by four-phase power clock (PC). The 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic is capable of operating through a wide range of frequency from 100[Formula: see text]MHz to 1[Formula: see text]GHz. Relentless scaling of MOSFETs towards lower technology nodes results in short channel effects in addition to increasing higher leakage current issues. In this scenario, FinFET advantageously replaces MOSFET with its unique features of the elimination of the short channel effects encountered by the MOSFETs with its gate structure that wraps around the channel completely. It incurs that the lower energy consumption and the feasibility of designing energy recovery circuits using FinFETs are analyzed in this paper. Comparatively, the energy efficiency of FinFET-based 2[Formula: see text]–[Formula: see text]–2[Formula: see text] against the [Formula: see text] and Positive Feedback Adiabatic Logic (PFAL) are analyzed. Simulation results also validate the robustness and efficiency of 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic circuit under process parameter variations of FinFET technology. Complex adiabatic adders and multipliers taken as bench mark circuits have been designed using 32-nm FinFET technology node and the results validate the enhanced energy efficiency characteristics of 2[Formula: see text]–[Formula: see text]2[Formula: see text] over [Formula: see text] and PFAL designs.
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Erdélyi-Szabó, Miklós. "Undecidability of the real-algebraic structure of models of intuitionistic elementary analysis." Journal of Symbolic Logic 65, no. 3 (September 2000): 1014–30. http://dx.doi.org/10.2307/2586686.
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AbstractWe show that true first-order arithmetic is interpretable over the real-algebraic structure of models of intuitionistic analysis built upon a certain class of complete Heyting algebras. From this the undecidability of the structures follows. We also show that Scott's model is equivalent to true second-order arithmetic. In the appendix we argue that undecidability on the language of ordered rings follows from intuitionistically plausible properties of the real numbers.
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KAYE, RICHARD. "INTERPRETATIONS BETWEENω-LOGIC AND SECOND-ORDER ARITHMETIC." Journal of Symbolic Logic 79, no. 3 (August 18, 2014): 845–58. http://dx.doi.org/10.1017/jsl.2013.17.
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AbstractThis paper addresses the structures (M, ω) and (ω, SSy(M)), whereMis a nonstandard model of PA andωis the standard cut. It is known that (ω, SSy(M)) is interpretable in (M, ω). Our main technical result is that there is an reverse interpretation of (M, ω) in (ω, SSy(M)) which is ‘local’ in the sense of Visser [11]. We also relate the model theory of (M, ω) to the study of transplendent models of PA [2].This yields a number of model theoretic results concerning theω-models (M, ω) and their standard systems SSy(M, ω), including the following.•$\left( {M,\omega } \right) \prec \left( {K,\omega } \right)$if and only if$M \prec K$and$\left( {\omega ,{\rm{SSy}}\left( M \right)} \right) \prec \left( {\omega ,{\rm{SSy}}\left( K \right)} \right)$.•$\left( {\omega ,{\rm{SSy}}\left( M \right)} \right) \prec \left( {\omega ,{\cal P}\left( \omega \right)} \right)$if and only if$\left( {M,\omega } \right) \prec \left( {{M^{\rm{*}}},\omega } \right)$for someω-saturatedM*.•$M{ \prec _{\rm{e}}}K$implies SSy(M, ω) = SSy(K, ω), but cofinal extensions do not necessarily preserve standard system in this sense.• SSy(M, ω)=SSy(M) if and only if (ω, SSy(M)) satisfies the full comprehension scheme.• If SSy(M, ω) is uniformly defined by a single formula (analogous to aβfunction), then (ω, SSy(M, ω)) satisfies the full comprehension scheme; and there are modelsMfor which SSy(M, ω) is not uniformly defined in this sense.
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Nurkhaidarov, Ermek S. "Automorphism groups of arithmetically saturated models." Journal of Symbolic Logic 71, no. 1 (March 2006): 203–16. http://dx.doi.org/10.2178/jsl/1140641169.
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In this paper we study the automorphism groups of countable arithmetically saturated models of Peano Arithmetic. The automorphism groups of such structures form a rich class of permutation groups. When studying the automorphism group of a model, one is interested to what extent a model is recoverable from its automorphism group. Kossak-Schmerl [12] show that if M is a countable, arithmetically saturated model of Peano Arithmetic, then Aut(M) codes SSy(M). Using that result they prove:Let M1. M2 be countable arithmetically saturated models of Peano Arithmetic such that Aut(M1) ≅ Aut(M2). Then SSy(M1) = SSy(M2).We show that if M is a countable arithmetically saturated of Peano Arithmetic, then Aut(M) can recognize if some maximal open subgroup is a stabilizer of a nonstandard element, which is smaller than any nonstandard definable element. That fact is used to show the main theorem:Let M1, M2be countable arithmetically saturated models of Peano Arithmetic such that Aut(M1) ≅ Aut(M2). Then for every n < ωHere RT2n is Infinite Ramsey's Theorem stating that every 2-coloring of [ω]n has an infinite homogeneous set. Theorem 0.2 shows that for models of a false arithmetic the converse of Kossak-Schmerl Theorem 0.1 is not true. Using the results of Reverse Mathematics we obtain the following corollary:There exist four countable arithmetically saturated models of Peano Arithmetic such that they have the same standard system but their automorphism groups are pairwise non-isomorphic.
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Chiari, Mario, and Jan Krajíček. "Witnessing functions in bounded arithmetic and search problems." Journal of Symbolic Logic 63, no. 3 (September 1998): 1095–115. http://dx.doi.org/10.2307/2586729.
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AbstractWe investigate the possibility to characterize (multi)functions that are-definable with smalli(i= 1, 2, 3) in fragments of bounded arithmeticT2in terms of natural search problems defined over polynomial-time structures. We obtain the following results:(1) A reformulation of known characterizations of (multi)functions that areand-definable in the theoriesand.(2) New characterizations of (multi)functions that areand-definable in the theory.(3) A new non-conservation result: the theoryis not-conservative over the theory.To prove that the theoryis not-conservative over the theory, we present two examples of a-principle separating the two theories:(a) the weak pigeonhole principle WPHP(a2,f, g) formalizing that no functionfis a bijection betweena2andawith the inverseg,(b) the iteration principle Iter(a, R, f) formalizing that no functionfdefined on a strict partial order ({0,…, a},R) can have increasing iterates.
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Linn, Eike, and Heidemarie Schmidt. "Advancing in-memory Arithmetic Based on CMOS-integrable Memristive Crossbar Structures." PROOF 1 (November 27, 2021): 80–89. http://dx.doi.org/10.37394/232020.2021.1.12.
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Memristive computing will be advantageous in large-scale, highly parallel mixed-mode processing architectures because processing can be performed directly within memristive memory architectures and intrachip communication can be implemented by a memristive crossbar structure with reconfigurable logic gates. Here we report on the development of a new concept for in-memory adders, using XOR functionality. Exploited memristive crossbar structures are based on memristive complementary resistive switches, e.g. TaOx, and BiFeO3.
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CONANT, GABRIEL. "THERE ARE NO INTERMEDIATE STRUCTURES BETWEEN THE GROUP OF INTEGERS AND PRESBURGER ARITHMETIC." Journal of Symbolic Logic 83, no. 1 (March 2018): 187–207. http://dx.doi.org/10.1017/jsl.2017.62.
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AbstractWe show that if a first-order structure ${\cal M}$, with universe ℤ, is an expansion of (ℤ,+,0) and a reduct of (ℤ,+,<,0), then ${\cal M}$ must be interdefinable with (ℤ ,+,0) or (ℤ ,+,<,0).
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Staworko, Michał, and Mariusz Rawski. "Modeling the Arithmetic Decomposition of DA-LUT Block for Heterogeneous FPGA Structures." International Journal of Electronics and Telecommunications 58, no. 4 (December 1, 2012): 335–44. http://dx.doi.org/10.2478/v10177-012-0046-y.
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Abstract Distributed arithmetic is well known technique of designing FIR filters in FPGA devices. The quality of such filter implementation strongly depends on synthesis results of the DALUT block. Heterogeneity of modern FPGA structures introduces new possibilities into implementation process, that may lead to better results, but also makes it more complicated. This paper presents the simple mathematical model for estimating the necessary FPGA resources to implement DA-LUT using decomposition-based approach. The model takes into account the type of logic cells or memory blocks used for decomposition process. The proposed model is helpful to determinate the DALUT decomposition strategy for further automation of modified distributed arithmetic decomposition method
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Wilmers, George. "Bounded existential induction." Journal of Symbolic Logic 50, no. 1 (March 1985): 72–90. http://dx.doi.org/10.2307/2273790.
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The present work may perhaps be seen as a point of convergence of two historically distinct sequences of results. One sequence of results started with the work of Tennenbaum [59] who showed that there could be no nonstandard recursive model of the system PA of first order Peano arithmetic. Shepherdson [65] on the other hand showed that the system of arithmetic with open induction was sufficiently weak to allow the construction of nonstandard recursive models. Between these two results there remained for many years a large gap occasioned by a general lack of interest in weak systems of arithmetic. However Dana Scott observed that the addition alone of a nonstandard model of PA could not be recursive, while more recently McAloon [82] improved these results by showing that even for the weaker system of arithmetic with only bounded induction, neither the addition nor the multiplication of a nonstandard model could be recursive.Another sequence of results starts with the work of Lessan [78], and independently Jensen and Ehrenfeucht [76], who showed that the structures which may be obtained as the reducts to addition of countable nonstandard models of PA are exactly the countable recursively saturated models of Presburger arithmetic. More recently, Cegielski, McAloon and the author [81] showed that the above result holds true if PA is replaced by the much weaker system of bounded induction.However in both the case of the Tennenbaum phenomenon and in that of the recursive saturation of addition the problem remained open as to how strong a system was really necessary to generate the required phenomenon. All that was clear a priori was that open induction was too weak to produce either result.
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PASTEN, HECTOR. "NOTES ON THE DPRM PROPERTY FOR LISTABLE STRUCTURES." Journal of Symbolic Logic 87, no. 1 (November 23, 2021): 273–312. http://dx.doi.org/10.1017/jsl.2021.97.
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AbstractA celebrated result by Davis, Putnam, Robinson, and Matiyasevich shows that a set of integers is listable if and only if it is positive existentially definable in the language of arithmetic. We investigate analogues of this result over structures endowed with a listable presentation. When such an analogue holds, the structure is said to have the DPRM property. We prove several results addressing foundational aspects around this problem, such as uniqueness of the listable presentation, transference of the DPRM property under interpretation, and its relation with positive existential bi-interpretability. A first application of our results is the rigorous proof of (strong versions of) several folklore facts regarding transference of the DPRM property. Another application of the theory we develop is that it will allow us to link various Diophantine conjectures to the question of whether the DPRM property holds for global fields. This last topic includes a study of the number of existential quantifiers needed to define a Diophantine set.
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Jaberipur, Ghassem, Behrooz Parhami, and Dariush Abedi. "Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies." IEEE Transactions on Sustainable Computing 3, no. 4 (October 1, 2018): 262–73. http://dx.doi.org/10.1109/tsusc.2018.2811181.
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Vahabi, Mohsen, Pavel Lyakhov, Ali Newaz Bahar, and Khan A. Wahid. "Design and Implementation of New Coplanar FA Circuits without NOT Gate and Based on Quantum-Dot Cellular Automata Technology." Applied Sciences 11, no. 24 (December 20, 2021): 12157. http://dx.doi.org/10.3390/app112412157.
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The miniaturization of electronic devices and the inefficiency of CMOS technology due to the development of integrated circuits and its lack of responsiveness at the nanoscale have led to the acquisition of nanoscale technologies. Among these technologies, quantum-dot cellular automata (QCA) is considered one of the possible replacements for CMOS technology because of its extraordinary advantages, such as higher speed, smaller area, and ultra-low power consumption. In arithmetic and comparative circuits, XOR logic is widely used. The construction of arithmetic logic circuits using AND, OR, and NOT logic gates has a higher design complexity. However, XOR gate design has a lower design complexity. Hence, the efficient and optimized XOR logic gate is very important. In this article, we proposed a new XOR gate based on cell-level methodology, with the expected output achieved by the influence of the cells on each other; this design method caused less delay. However, this design was implemented without the use of inverter gates and crossovers, as well as rotating cells. Using the proposed XOR gate, two new full adder (FA) circuits were designed. The simulation results indicate the advantage of the proposed designs compared with previous structures.
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Kanovei, V. "Uniqueness, collection, and external collapse of cardinals in IST and models of Peano arithmetic." Journal of Symbolic Logic 60, no. 1 (March 1995): 318–24. http://dx.doi.org/10.2307/2275523.
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AbstractWe prove that in IST, Nelson's internal set theory, the Uniqueness and Collection principles, hold for all (including external) formulas. A corollary of the Collection theorem shows that in IST there are no definable mappings of a set X onto a set Y of greater (not equal) cardinality unless both sets are finite and #(Y) ≤ n #(X) for some standard n. Proofs are based on a rather general technique which may be applied to other nonstandard structures. In particular we prove that in a nonstandard model of PA, Peano arithmetic, every hyperinteger uniquely definable by a formula of the PA language extended by the predicate of standardness, can be defined also by a pure PA formula.
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UTRERAS, JAVIER. "INTERPRETING ARITHMETIC IN THE FIRST-ORDER THEORY OF ADDITION AND COPRIMALITY OF POLYNOMIAL RINGS." Journal of Symbolic Logic 84, no. 3 (May 9, 2019): 1194–214. http://dx.doi.org/10.1017/jsl.2019.21.
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AbstractWe study the first-order theory of polynomial rings over a GCD domain and of the ring of formal entire functions over a non-Archimedean field in the language $\{ 1, + , \bot \}$. We show that these structures interpret the first-order theory of the semi-ring of natural numbers. Moreover, this interpretation depends only on the characteristic of the original ring, and thus we obtain uniform undecidability results for these polynomial and entire functions rings of a fixed characteristic. This work enhances results of Raphael Robinson on essential undecidability of some polynomial or formal power series rings in languages that contain no symbols related to the polynomial or power series ring structure itself.
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Pfänder, O. A., R. Nopper, H. J. Pfleiderer, S. Zhou, and A. Bermak. "Comparison of reconfigurable structures for flexible word-length multiplication." Advances in Radio Science 6 (May 26, 2008): 113–18. http://dx.doi.org/10.5194/ars-6-113-2008.
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Abstract. Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.
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Glebsky, L. Yu, E. I. Gordon, and C. Ward Henson. "On finite approximations of topological algebraic systems." Journal of Symbolic Logic 72, no. 1 (March 2007): 1–25. http://dx.doi.org/10.2178/jsl/1174668381.
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AbstractWe introduce and discuss a concept of approximation of a topological algebraic system A by finite algebraic systems from a given class . If A is discrete, this concept agrees with the familiar notion of a local embedding of A in a class of algebraic systems. One characterization of this concept states that A is locally embedded in iff it is a subsystem of an ultraproduct of systems from . In this paper we obtain a similar characterization of approximability of a locally compact system A by systems from using the language of nonstandard analysis.In the signature of A we introduce positive bounded formulas and their approximations; these are similar to those introduced by Henson [14] for Banach space structures (see also [15, 16]). We prove that a positive bounded formula φ holds in A if and only if all precise enough approximations of φ hold in all precise enough approximations of A.We also prove that a locally compact field cannot be approximated arbitrarily closely by finite (associative) rings (even if the rings are allowed to be non-commutative). Finite approximations of the field ℝ can be considered as possible computer systems for real arithmetic. Thus, our results show that there do not exist arbitrarily accurate computer arithmetics for the reals that are associative rings.
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Limón-Priego, Yensen, Ismael Everardo Bárcenas-Patiño, Edgard Iván Benítez-Guerrero, Guillermo Gilberto Molero-Castillo, and Alejandro Velazquez-Mena. "Mu-Calculus Satisfiability with Arithmetic Constraints." Proceedings of the Institute for System Programming of the RAS 33, no. 2 (2021): 191–200. http://dx.doi.org/10.15514/ispras-2021-33(2)-12.
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The propositional modal μ-calculus is a well-known specification language for labeled transition systems. In this work, we study an extension of this logic with converse modalities and Presburger arithmetic constraints, interpreted over tree models. We describe a satisfiability algorithm based on breadth-first construction of Fischer-Lardner models. An implementation together several experiments are also reported. Furthermore, we also describe an application of the algorithm to solve static analysis problems over semi-structured data.
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Schwartz, David I., and Stuart S. Chen. "A constraint-based approach for qualitative matrix structural analysis." Artificial Intelligence for Engineering Design, Analysis and Manufacturing 9, no. 1 (January 1995): 23–36. http://dx.doi.org/10.1017/s0890060400002067.
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AbstractQualitative physics, a subfield of artificial intelligence, adapts intuitive and non-numerical reasoning for descriptive analysis of physical systems. The application of a set-based qualitative algebra to matrix analysis (QMA) allows for the development of a qualitative matrix stiffness methodology for linear elastic structural analysis. The unavoidable introduction of arithmetic ambiguity requires the reinforcement of physical constraints complementary to standard matrix operations. The overall analysis technique incorporates such constraints within the set-based framework with logic programming. Truss, beam, and frame structures demonstrate constraint relationships, which prune spurious solutions resulting from qualitative arithmetic relations. Though QMA is not a panacea for all structural applications, it provides greater insight into new notions of physical analysis.
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Ash, C. J. "Stability of recursive structures in arithmetical degrees." Annals of Pure and Applied Logic 32 (1986): 113–35. http://dx.doi.org/10.1016/0168-0072(86)90048-5.
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Бондарев, А. В., and В. Н. Ефанов. "Investigation of Robustness of Nanoelectronic Structures Based on Resonant Tunneling Elements." Proceedings of Universities. Electronics 26, no. 6 (December 2021): 491–507. http://dx.doi.org/10.24151/1561-5405-2021-26-6-491-507.
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Multi-input logic gates based on two-level logic cells MOBILE have short (picosecond) switching times and higher functionality due to the ability to implement logic functions with fewer gates. This creates good prospects for the development of ultra-high-speed FPGAs with a high degree of integration, which are required for organizing high-performance computing. However, the extremely high sensitivity of resonant tunneling elements to changes in the energies of quantum states requires an assessment of the stability of such structures to external influences in real operation. In this work, the problem of assessing the stability of nanoelectronic structures that include resonant tunneling elements is considered. The method for studying the robustness of logic cells MOBILE based on a resonant tunneling diode and an НВТ transistor was proposed, making it possible to find an external interval estimate of the output voltage of the device under study for given interval models of the initial components. The technique is based on the use of systems of topological and parametric equations written in finite increments. It was shown that the proposed decomposition principle for the initial interval model ensures the algorithmic solvability of the problem posed. A computational algorithm for calculating processes in a two-level logical cell MOBILE has been developed. The algorithm provides for step-by-step integration of interval differential equations and solution of interval nonlinear algebraic equations at each step of integration using Kaucher interval arithmetic. The obtained results of the study of processes in a two-level logic cell MOBILE create prerequisites for expanding the field of application of resonant tunneling devices in high-speed monolithic integrated circuits.
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Stanković, Radomir S., Milena Stanković, and Reiner Creutzburg. "Foundations for Applications of Gibbs Derivatives in Logic Design and VLSI." VLSI Design 14, no. 1 (January 1, 2002): 65–81. http://dx.doi.org/10.1080/10655140290009819.
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New technologies and increased requirements for performances of digital systems require new mathematical theories and tools as a basis for future VLSI CAD systems. New or alternative mathematical approaches and concepts must be suitable to solve some concrete problems in VLSI and efficient algorithms for their efficient application should be provided. This paper is an attempt in this direction and relates with the recently renewed interest in arithmetic expressions for switching functions, instead representations in Boolean structures, and spectral techniques and differential operators in switching theory and applications. Logic derivatives are efficiently used in solving different tasks in logic design, as for example, fault detection, functional decomposition, detection of symmetries and co-symmetries of logic functions, etc. Their application is based on the property that by differential operators, we can measure the rate of change of a logic function. However, by logic derivatives, we can hardly distinguish the direction of the change of the function, since they are defined in finite algebraic structures. Gibbs derivatives are a class of differential operators on groups, which applied to logic functions, permit to overcome this disadvantage of logic derivatives. Therefore, they may be useful in logic design in the same areas where the logic derivatives have been already using. For such applications, it is important to provide fast algorithms for calculation of Gibbs derivatives on finite groups efficiently in terms of space and time. In this paper, we discuss the methods for efficient calculation of Gibbs derivatives. These methods should represent a basis for further applications of these and related operators in VLSI CAD systems.
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Bryan, Michael J., Srinivas Devadas, and Kurt Keutzer. "Analysis and Design of Regular Structures for Robust Dynamic Fault Testability." VLSI Design 1, no. 1 (January 1, 1993): 45–60. http://dx.doi.org/10.1155/1993/38536.
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Recent methods of synthesizing logic that is fully and robustly testable for dynamic faults, namely path delay, transistor stuck-open and gate delay faults, rely almost exclusively on flattening given logic expressions into sum-of-products form, minimizing the cover to obtain a fully dynamic-fault testable two-level representation of the functions, and performing structural transformations to resynthesize the circuit into a multilevel network, while also maintaining full dynamic-fault testability. While this technique will work well for random or control logic, it is not practical for many regular structures.To deal with the synthesis of regular structures for dynamic-fault testability, we present a method that involves the development of a library of cells for these regular structures such that the cells are all fully path-delay-fault, transistor stuck-open fault or gate-delay-fault testable. These cells can then be utilized whenever one of these standard functions is encountered.We analyze various regular structures such as adders, arithmetic logic units, comparators, multipliers, and parity generators to determine if they are testable for dynamic faults, or how they can be modified to be testable for dynamic faults while still maintaining good area and performance characteristics. In addition to minimizing the area and delay, another key consideration is to get designs which can be scaled to an arbitrary number of bits while still maintaining complete testability. In each case, the emphasis is on obtaining circuits which are fully path-delay-fault testable. In the process of design modification to produce fully robustly testable structures, we have derived a number of new composition rules that allow cascading individual modules while maintaining robust testability under dynamic fault models.
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ZHao, Hong-Quan, and Seiya Kasai. "WPG-Controlled Quantum BDD Circuits with BDD Architecture on GaAs-Based Hexagonal Nanowire Network Structure." Journal of Nanomaterials 2012 (2012): 1–6. http://dx.doi.org/10.1155/2012/726860.
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One-dimensional nanowire quantum devices and basic quantum logic AND and OR unit on hexagonal nanowire units controlled by wrap gate (WPG) were designed and fabricated on GaAs-based one-dimensional electron gas (1-DEG) regular nanowire network with hexagonal topology. These basic quantum logic units worked correctly at 35 K, and clear quantum conductance was achieved on the node device, logic AND circuit unit, and logic OR circuit unit. Binary-decision-diagram- (BDD-) based arithmetic logic unit (ALU) is realized on GaAs-based regular nanowire network with hexagonal topology by the same fabrication method as that of the quantum devices and basic circuits. This BDD-based ALU circuit worked correctly at room temperature. Since these quantum devices and circuits are basic units of the BDD ALU combinational circuit, the possibility of integrating these quantum devices and basic quantum circuits into the BDD-based quantum circuit with more complicated structures was discussed. We are prospecting the realization of quantum BDD combinational circuitries with very small of energy consumption and very high density of integration.
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CVS, Chaitanya, Sundaresan C, P. R Venkateswaran, and Keerthana Prasad. "Design of modified booth based multiplier with carry pre-computation." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 3 (March 1, 2019): 1048. http://dx.doi.org/10.11591/ijeecs.v13.i3.pp1048-1055.
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Arithmetic unit is the most important component of modern embedded computer systems. Arithmetic unit generally includes floating point and fixed-point arithmetic operations and trigonometric functions. Multipliers units are the most important hardware structures in a complex arithmetic unit. With increase in chip frequency, the designer must be able to find the best set of trade-offs. The ability for faster computation is essential to achieve high performance in many DSP and Graphic processing algorithms and is why there is at least one dedicated Multiplier unit in all of the modern commercial DSP processors. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. A novel modified booth multiplier design for high speed VLSI applications using pre-computation logic has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.
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Jónsson, Bjarni. "The contributions of Alfred Tarski to general algebra." Journal of Symbolic Logic 51, no. 4 (December 1986): 883–89. http://dx.doi.org/10.2307/2273901.
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A distinctive feature of modern mathematics is the interaction between its various branches and the blurring of the boundaries between different areas. This is strikingly illustrated in the work of Alfred Tarski. He was a logician first and an algebraist second. His contributions to algebra can be divided into three (ill-defined and overlapping) categories, general algebra, the study of various algebraic structures arising from problems outside algebra, mostly in logic and set theory, and the use of concepts and techniques from logic in the study of algebraic structures. Even more roughly, these three categories could be labeled as pure algebra, applications of algebra to logic, and applications of logic to algebra.Before Tarski came to the United States in 1939, he had written a series of papers on both the axiomatic and the structural aspects of Boolean algebras, and his inclination to algebraize mathematical problems is well illustrated by his paper [38g], Algebraische Fassung des Massproblems. Many of his later investigations of various types of algebraic structures are inspired by work done in this earlier period. However, beginning around 1940 there is a much greater emphasis on the study of algebra in its various aspects.The paper [41], On the calculus of relations, is a landmark event in this respect. The object here was to find an axiomatic basis for the arithmetic of binary relations. The axioms that he chose are simple and natural (see Monk [1986]).
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Otto, Martin. "The expressive power of fixed-point logic with counting." Journal of Symbolic Logic 61, no. 1 (March 1996): 147–76. http://dx.doi.org/10.2307/2275602.
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AbstractWe study the expressive power in the finite of the logic Fixed-Point+Counting, the extension of first-order logic which is obtained through adding both the fixed-point constructor and the ability to count.To this end an isomorphism preserving (‘generic’) model of computation is introduced whose PTime restriction exactly corresponds to this level of expressive power, while its PSpace restriction corresponds to While+Counting. From this model we obtain a normal form which shows a rather clear separation of the relational vs. the arithmetical side of the algorithms involved.In parallel, we study the relations of Fixed-Point+Counting with the infinitary logics and the corresponding pebble games.The main result, however, involves the concept of an arithmetical invariant. By this we mean a functor taking every finite relational structure to an expansion of (an initial segment of) the standard arithmetical structure. In particular its values are linearly ordered structures. We establish the existence of a family of arithmetical invariants with the following properties:• The invariants themselves can be evaluated in polynomial time.• A class of finite relational structures is definable in Fixed-Point+Counting if and only if membership can be decided in polynomial time on the basis of the values of one of the invariants.• The invariant r classifies all finite relational structures exactly up to equivalence with respect to the logic We also give a characterization of Fixed-Point+Counting in terms of sequences of formulae in the : It corresponds exactly to the polynomial time computable families (φn)n ∈ ω in these logics.Towards a positive assessment of the expressive power of Fixed-Point+Counting, it is shown that the natural extension of fixed-point logic by Lindström quantifiers, which capture all the PTime computable properties of cardinalities of definable predicates, is strictly weaker than what we get here. This implies in particular that every extension of fixed-point logic by means of monadic Lindström quantifiers, which stays within PTime, must be strictly contained in Fixed-Point+Counting.
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KNIGHT, J. F., and J. MILLAR. "COMPUTABLE STRUCTURES OF RANK $\omega_{1}^{{\rm CK}}$." Journal of Mathematical Logic 10, no. 01n02 (June 2010): 31–43. http://dx.doi.org/10.1142/s0219061310000912.
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For countable structure, "Scott rank" provides a measure of internal, model-theoretic complexity. For a computable structure, the Scott rank is at most [Formula: see text]. There are familiar examples of computable structures of various computable ranks, and there is an old example of rank [Formula: see text]. In the present paper, we show that there is a computable structure of Scott rank [Formula: see text]. We give two different constructions. The first starts with an arithmetical example due to Makkai, and codes it into a computable structure. The second re-works Makkai's construction, incorporating an idea of Sacks.
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Deptuła, A., and R. Kh Kurmaev. "Application of decision logic trees and game-tree structures in analysis of automatic transmission gearboxes." Trudy NAMI, no. 3 (October 6, 2021): 6–21. http://dx.doi.org/10.51187/0135-3152-2021-3-6-21.
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Introduction (problem statement and relevance). The graphs, logic and game-tree structures methods have been used in mechanics. The purpose of modeling an automatic gearbox with graphs can be versatile, namely: determining the transmission ratio of individual gears, analyzing the speed and acceleration of individual rotating elements.The purpose of the study. The article presents the application of decision trees in the analysis of automatic gearboxes modeled with the Hsu graph.Methodology and research methods. The paper presents a method of generating game tree structures that allow to change the values of decision parameters in the issues of decision making and knowledge generation. Specifying the rank of importance, in which order you should change individual items to active, allows you to detect the so-called redundant or temporarily redundant components for a given gear currently under consideration.Scientific novelty and results. At each stage of optimization, a tree is generated, selecting the optimal decisions. Then, vertices can be added to the tree that represent the optimal responses of the system to changes in arithmetic construction parameters.Practical significance. The most important in this regard will be the selection of the optimal programming environment with the possibility of installing the program in laboratory
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Melnyk, Oleksandr, and Viktoriia Kozarevych. "SIMULATION OF PROGRAMMABLE SINGLE-ELECTRON NANOCIRCUITS." Bulletin of the National Technical University "KhPI". Series: Mathematical modeling in engineering and technologies, no. 1 (March 5, 2021): 64–68. http://dx.doi.org/10.20998/2222-0631.2020.01.05.
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The speed and specializations of large-scale integrated circuits always contradict their versatility, which expands their range and causes the rise in price of electronic devices. It is possible to eliminate the contradictions between universality and specialization by developing programmable nanoelectronic devices, the algorithms of which are changed at the request of computer hardware developers, i.e. by creating arithmetic circuits with programmable characteristics. The development of issues of theory and practice of the majority principle is now an urgent problem, since the nanoelectronic execution of computer systems with programmable structures will significantly reduce their cost and significantly simplify the design stage of automated systems. Today there is an important problem of developing principles for building reliable computer equipment. The use of mathematical and circuit modeling along with computer-aided design systems (CAD) can significantly increase the reliability of the designed devices. The authors prove the advantages of creating programmable nanodevices to overcome the physical limitations of micro-rominiatization. This continuity contributes to the accelerated introduction of mathematical modeling based on programmable nanoelectronics devices. The simulation and computer-aided design of reliable programmable nanoelectronic devices based on the technology of quantum automata is described. While constructing single-electron nanocircuits of combinational and sequential types the theory of majority logic is used. The order of construction and programming of various types of arithmetic-logic units is analyzed.
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MASON, IAN, and CAROLYN TALCOTT. "REASONING ABOUT OBJECT SYSTEMS IN VTLoE." International Journal of Foundations of Computer Science 06, no. 03 (September 1995): 265–98. http://dx.doi.org/10.1142/s0129054195000160.
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VTLoE (Variable Type Logic of Effects) is a logic for reasoning about imperative functional programs inspired by the variable type systems of Feferman. The underlying programming language, λ mk , extends the call-by-value lambda calculus with primitives for arithmetic, pairing, branching, and reference cells (mutable data). In VTLoE one can reason about program equivalence and termination, input/output relations, program contexts, and inductively (and co-inductively) define data structures. In this paper we present a refinement of VTLoE. We then introduce a notion of object specification and establish formal principles for reasoning about object systems within VTLoE. Objects are self-contained entities with local state. The local state of an object can only be changed by action of that object in response to a message. In λ mk objects are represented as closures with mutable data bound to local variables. A semantic principle called simulation induction was introduced in our earlier work as a means of establishing equivalence relations between streams, object behaviors, and other potentially infinite structures. These are formulated in VTLoE using the class apparatus. The use of these principles is illustrated by validating a variety of basic tranformation rules.
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Lin, Rong. "A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits." VLSI Design 12, no. 3 (January 1, 2001): 377–90. http://dx.doi.org/10.1155/2001/97598.
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A highly regular parallel multiplier architecture along with the novel low-power, high-performance CMOS implementation circuits is presented. The superiority is achieved through utilizing a unique scheme for recursive decomposition of partial product matrices and a recently proposed non-binary arithmetic logic as well as the complementary shift switch logic circuits.The proposed 64×64-b parallel multiplier possesses the following distinct features: (1) generating 64 8×8-b partial product matrices instead of a single large one; (2) comprising only four stages of bit reductions: first, by 8×8-b small parallel multipliers, then, by small parallel counters in each of the remaining three stages. A family of shift switch parallel counters, including non-binary (6, 3)∗ and complementary (k, 2) for 2 ≤ k ≤ 8, are proposed for the efficient bit reductions; (3) using a simple final adder.The non-binary logic operates 4-bit state signals (representing integers ranging from (0 to 3), where no more than half of the signal bits are subject to value-change at any logic stage. This and others including minimum transistor counts, fewer inverters, and low-leakage logic structure, significantly reduce circuit power dissipation.
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Greenberg, Noam. "The Role of True Finiteness in the Admissible Recursively Enumerable Degrees." Bulletin of Symbolic Logic 11, no. 3 (September 2005): 398–410. http://dx.doi.org/10.2178/bsl/1122038994.
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AbstractWhen attempting to generalize recursion theory to admissible ordinals, it may seem as if all classical priority constructions can be lifted to any admissible ordinal satisfying a sufficiently strong fragment of the replacement scheme. We show, however, that this is not always the case. In fact, there are some constructions which make an essential use of the notion of finiteness which cannot be replaced by the generalized notion of α-finiteness. As examples we discuss both codings of models of arithmetic into the recursively enumerable degrees, and non-distributive lattice embeddings into these degrees. We show that if an admissible ordinal α is effectively close to ω (where this closeness can be measured by size or by cofinality) then such constructions may be performed in the α-r.e. degrees, but otherwise they fail. The results of these constructions can be expressed in the first-order language of partially ordered sets, and so these results also show that there are natural elementary differences between the structures of α-r.e. degrees for various classes of admissible ordinals α. Together with coding work which shows that for some α, the theory of the α-r.e. degrees is complicated, we get that for every admissible ordinal α, the α-r.e. degrees and the classical r.e. degrees are not elementarily equivalent.
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Rupsa Roy, Swarup Sarkar,. "QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology." Psychology and Education Journal 58, no. 2 (February 10, 2021): 813–23. http://dx.doi.org/10.17762/pae.v58i2.1916.
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An important arithmetic component of “Arithmetic and Logic Unit” or ALU is reconfigured in this paper, known as “Full-Adder-Subtractor”, where an advance low-power, high-speed nano technology “QCA” with electro-spin criterion is used with reversibility and the advancement of multilayer 3D circuitry. In this modern digital world, this selected nano-sized technology is an effective alternative of widely used “CMOS Technology” because all the limitations, mainly limitation due to the presence of high power dissipation at the time of device-density increment in a “CMOS” based integrated circuit, can be optimized by “QCA” nano technology with electro-spin criterion and this technology also supports reversible logic in multilayer 3D platform with less complexity. This paper, primarily presents two novel “QCA” based 3-layered “Adder-Subtractor” designs using the collaboration of multilayer inverter gates, reversible modified 3-input Feynman-Gate and 3-input MG (Majority Gate) with very less cell-complexity, area-occupation, delay and energy-dissipation and high output-strength, temperature-tolerance and accuracy. A clear parametric investigation on presented designs are shown clearly in this paper through a comparative manner with some previous published related structures. Additionally, another parametric-experiment on a novel multibit reversible multilayer “QCA” based “Full-Adder-Subtractor” circuitry using the working phenomenon of “Ripple Carry Adder” (RCA) and multibit subtractor (“ripple borrow subtractor” or RBS) is presented in this proposed work in a proper way and this combination of RCA and multibit subtraction operation converts the proposed circuitry into a hybrid form, which is more effective compare to some other advanced adders in parametric-optimization field.
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Yagain, Deepa, Vijaya Krishna A, and Akansha Baliga. "Design of High-Speed Adders for Efficient Digital Design Blocks." ISRN Electronics 2012 (September 26, 2012): 1–9. http://dx.doi.org/10.5402/2012/253742.
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The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65 nm CMOS design library.
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Cheng, Harry H. "Scientific Computing in the CHProgramming Language." Scientific Programming 2, no. 3 (1993): 49–75. http://dx.doi.org/10.1155/1993/261875.
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We have developed a general-purpose block-structured interpretive programming Ianguage. The syntax and semantics of this language called CHare similar to C. CHretains most features of C from the scientific computing point of view. In this paper, the extension of C to CHfor numerical computation of real numbers will be described. Metanumbers of −0.0, 0.0, Inf, −Inf, and NaN are introduced in CH. Through these metanumbers, the power of the IEEE 754 arithmetic standard is easily available to the programmer. These metanumbers are extended to commonly used mathematical functions in the spirit of the IEEE 754 standard and ANSI C. The definitions for manipulation of these metanumbers in I/O; arithmetic, relational, and logic operations; and built-in polymorphic mathematical functions are defined. The capabilities of bitwise, assignment, address and indirection, increment and decrement, as well as type conversion operations in ANSI C are extended in CH. In this paper, mainly new linguistic features of CHin comparison to C will be described. Example programs programmed in CHwith metanumbers and polymorphic mathematical functions will demonstrate capabilities of CHin scientific computing.
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Mares, Edwin D., and Robert Goldblatt. "An alternative semantics for quantified relevant logic." Journal of Symbolic Logic 71, no. 1 (March 2006): 163–87. http://dx.doi.org/10.2178/jsl/1140641167.
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AbstractThe quantified relevant logic RQ is given a new semantics in which a formula ∀xA is true when there is some true proposition that implies all x-instantiations of A. Formulae are modelled as functions from variable-assignments to propositions, where a proposition is a set of worlds in a relevant model structure. A completeness proof is given for a basic quantificational system QR from which RQ is obtained by adding the axiom EC of ‘extensional confinement’: ∀x(A ⋁ B) → (A ⋁ ∀xB), with x not free in A. Validity of EC requires an additional model condition involving the boolean difference of propositions. A QR-model falsifying EC is constructed by forming the disjoint union of two natural arithmetical structures in which negation is interpreted by the minus operation.
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Weiss, Yale. "A Note on the Relevance of Semilattice Relevance Logic." Australasian Journal of Logic 16, no. 6 (October 15, 2019): 177. http://dx.doi.org/10.26686/ajl.v16i6.5416.
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A propositional logic has the variable sharing property if φ → ψ is a theorem only if φ and ψ share some propositional variable(s). In this note, I prove that positive semilattice relevance logic (R+u) and its extension with an involution negation (R¬u) have the variable sharing property (as these systems are not subsystems of R, these results are not automatically entailed by the fact that R satisfies the variable sharing property). Typical proofs of the variable sharing property rely on ad hoc, if clever, matrices. However, in this note, I exploit the properties of rather more intuitive arithmetical structures to establish the variable sharing property for the systems discussed.
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Kumabe, Masahiro. "Minimal upper bounds for arithmetical degrees." Journal of Symbolic Logic 59, no. 2 (June 1994): 516–28. http://dx.doi.org/10.2307/2275404.
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This paper was inspired by Lerman [14] in which he proved various properties of upper bounds for the arithmetical degrees. The degrees which are upper bounds for the arithmetical degrees were first studied by Hodes [5] and Enderton and Putnam [5]. Enderton and Putnam [5] showed that if a is an upper bound for the arithmetical degrees, then a(2) ≥ 0(ω). This area was further studied by Hodes [5], Knight, Lachlan and Soare [12], Jockusch and Simpson [12], and Sacks [17].Enderton and Putnam [5] and Sacks [17] have combined to show that 0(ω) is the least degree in {a(2): a is an upper bound for the arithmetical degrees}. So there seem to be some analogies between the degrees of upper bounds for the arithmetical degrees and the degrees below 0(2). But Sacks [17] showed an important difference between these two structures; namely, the Turing jumps of upper bounds for the arithmetical degrees have no least element. In Lerman [14], a systematic investigation of properties of the jumps of upper bounds for the arithmetical degrees was suggested, which could lead to a definition of the jump operator over the elementary theory of the partial ordering of the degrees. Although Cooper [5] found a degree-theoretic definition of the jump operator, Lerman's plan is still interesting.We say a degree a is generic if there is a representative A of a such that A is Cohen generic for the arithmetical sentences. By Jockusch [5], the statement that A is Cohen generic for the arithmetical sentences is equivalent to saying that for any arithmetical set S of binary strings, there is a σ extended by A such that σ is in S or no extension of σ is in S. First, we investigate the relation between generic degrees and upper bounds for the arithmetical degrees. In the case D(≤ 0′), the set of degrees below 0′, it is well known that any nonrecursive r.e. degree bounds a 1-generic degree (Cohen generic for Σ1 sentences). Jockusch and Ponser [12] showed that any degree a with a″ >T (a ∪ 0′)′ bounds a 1-generic degree.
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FABER, WOLFGANG, GERALD PFEIFER, NICOLA LEONE, TINA DELL'ARMI, and GIUSEPPE IELPA. "Design and implementation of aggregate functions in the DLV system." Theory and Practice of Logic Programming 8, no. 5-6 (November 2008): 545–80. http://dx.doi.org/10.1017/s1471068408003323.
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AbstractDisjunctive logic programming (DLP) is a very expressive formalism. It allows for expressing every property of finite structures that is decidable in the complexity class ΣP2(=NPNP). Despite this high expressiveness, there are some simple properties, often arising in real-world applications, which cannot be encoded in a simple and natural manner. Especially properties that require the use of arithmetic operators (like sum, times, or count) on a set or multiset of elements, which satisfy some conditions, cannot be naturally expressed in classic DLP. To overcome this deficiency, we extend DLP by aggregate functions in a conservative way. In particular, we avoid the introduction of constructs with disputed semantics, by requiring aggregates to be stratified. We formally define the semantics of the extended language (called ), and illustrate how it can be profitably used for representing knowledge. Furthermore, we analyze the computational complexity of , showing that the addition of aggregates does not bring a higher cost in that respect. Finally, we provide an implementation of in DLV—a state-of-the-art DLP system—and report on experiments which confirm the usefulness of the proposed extension also for the efficiency of computation.
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Knight, Julia F. "Nonarithmetical ℵ0-categorical theories with recursive models." Journal of Symbolic Logic 59, no. 1 (March 1994): 106–12. http://dx.doi.org/10.2307/2275253.
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In what follows, L is a recursive language. The structures to be considered are L-structures with universe named by constants from ω. A structure is recursive A if the open diagram D() is recursive. Lerman and Schmerl [L-S] proved the following result.Let T be an ℵ0-categorical elementary first-order theory. Suppose that for all n, , and T is arithmetical. Then T has a recursive model.The aim of this paper is to extend Theorem 0.1. Stating the extension requires some terminology. Consider finitary formulas with symbols from L and sometimes extra constants from ω. For each n ∈ ω, the Σn and Πn formulas are as usual. Then Bnformulas are Boolean combinations of Σn formulas. For an L-structure , Dn() denotes the set of Bn sentences in the complete diagram Dc(). A complete Σn theory is a maximal consistent set of ΣnL-sentences. We may write φ(x), or Γ(x), to indicate that the free variables of the formula φ, or the set Γ, are among those in x. A complete Bn type for x is a maximal consistent set Γ(x) of Bn formulas with just the free variables x.If T is ℵ0-categorical, then for each x only finitely many complete types Γ(x) are consistent with T. While Lerman and Schmerl stated their result just for ℵ0-categorical theories, essentially the same proof yields the following.Theorem 0.2. Let T be a consistent, complete theory such that for all n andx, only finitely many complete Bn types Γ(x) are consistent with T.
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Chete, Fidelis, and Obinna Ikeh. "Towards the Design and Implementation of a Programming Language (Beex)." International Journal of Software Engineering and Computer Systems 8, no. 2 (July 1, 2022): 51–66. http://dx.doi.org/10.15282/ijsecs.8.2.2022.6.0103.
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Software Engineers, Computer Scientists, and Software Experts alike are faced to decide which programming language is best suited for a certain purpose as the use of programming languages grows. When we consider the various types of programming languages available today, such as Domain Specific Languages (DSL), General Purpose Languages (GPL), Functional Programming Languages (FPL), Imperative Programming Languages (IPL), amongst others, this becomes complicated. In this study, we introduce BeeX, an interpreted language, with the aim of showing the process and principles involved in language design and consider various choices faced by language designers of various programming languages. BeeX was created with simplicity in mind, thus the study focused on architectural design options. We look at the implementation standpoint and try to figure out what the basic building parts of most programming languages are, such as lexical analysis, syntax analysis, and evaluation phase. To achieve this, we created an interactive command interface that evaluated various BeeX language constructs(conditional logic statements, arithmetic expressions, loop constructs etc.) which allowed students to easily experiment with the proposed language. The results of the tests showed that students and programmers alike can use the BeeX programming language to create a variety of code structures that are simple to use.
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Arunabala, Dr C. "Design of a 4 bit Arithmetic and Logical unit with Low Power and High Speed." International Journal of Innovative Technology and Exploring Engineering 10, no. 5 (March 30, 2021): 87–92. http://dx.doi.org/10.35940/ijitee.e8660.0310521.
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In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using the different modules. The Various modules are AND gate & OR gate designed with six transistors, While the XOR modules is designed with both eight transistors & six transistors. The six transistor XOR module gives optimized results. Another one is the four by one multiplexer designed with eight transistors implemented using Pass transistor logic (PTL) style. The full adder module is designed by using 18 transistors implemented through PTL style. Here because of PTL style the number of transistor count optimized such that the constraints get optimized results. By using the AND, OR, XOR, 4X1 MUX and full adder modules with reduced transistor count we designed the one bit ALU. With one bit ALU we designed 4 bit ALU and compared the outcomes with conventional 4 bit ALU design so that the proposed 4 bit ALU design has optimized transistor count, area, power, delay and power delay product (PDP). Simulations are verified through 130nm mentor graphics tool.
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Kormin, Nikolai Aleksandrovich. "Thinking in colors." Культура и искусство, no. 2 (February 2021): 12–38. http://dx.doi.org/10.7256/2454-0625.2021.2.34996.
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This article reveals the philosophical grounds of the aesthetics of color, analyzes the correlation between the structures of philosophical and artistic comprehension of coloristics. Interaction of philosophy and art as the forms of cultural identity manifests in the sphere of intellectual understanding of the perception of color and its semantics in painting. In the hidden logic of contemplation of color, can be traced the outlines of the problematic of transcendental and intelligible in art conditions for the aesthetic approach towards chromatic space. Color creates the visual beauty, thus it is apparent why the aesthetic knowledge seeks to clarify to which extent we can assess the experience of color – the result of coloration of light. The art itself creates the so-called color ontology of the world. First the first time, the beauty of color and its perception are analyzed in the context of correlation between art and transcendental traditions of philosophizing (Descartes, Kant, early Husserl – his work “The Philosophy of Arithmetic”) that allows matching the key to a new interpretation of the tradition of color. Determination of its meaning requires comparing history and structure of the philosophical and artistic metaphor of color. It is demonstrated that the phenomenon of color is of crucial significance for the aesthetics, as it implies not only comprehension of the problem of correlation between nature and art, but also cognition of the beauty of color, its universal value for all forms of art, profound structures of perception of coloristic phenomena, picturesque unveiling of the color harmony of the painting.