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Journal articles on the topic 'Arithmetic and Logic Unit (ALU)'

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Published: 2 June 2025

Last updated: 31 July 2025

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1

Akansha, Singh, and B. Ramesh K. "Arithmetic and Logic Unit." Journal of Advances in Computational Intelligence Theory 5, no. 3 (2023): 1–6. https://doi.org/10.5281/zenodo.8009911.

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<em>This research paper explores the fundamental digital circuit known as the Arithmetic and Logic Unit (ALU). The ALU is an essential component of any central processing unit (CPU) and is responsible for executing arithmetic and logical instructions within a computer's architecture. The paper examines the ALU's function in detail, focusing on its ability to process data by executing mathematical and logical operations such as addition, subtraction, multiplication, division, logical AND, OR, NOT, and XOR. The paper also explores analyzing the internal structure and operation of an ALU,

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2

Yakunin, A. N., Aung Myo San, and Khant Win. "Improving Performance of a Multi-Bit Arithmetic Logic Unit." Proceedings of Universities. Electronics 26, no. 1 (2021): 40–53. http://dx.doi.org/10.24151/1561-5405-2021-26-1-40-53.

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In modern microprocessors to reduce the time resources the arithmetic-logic units (ALU) with an increased organization of arithmetic carry, characterized by high speed, compared to ALU with sequential organization of the arithmetic carry, are commonly used. However, while increasing the bit number of the input operands, the operating time of ALU of ALU with the accelerated arithmetic carry increases linearly depending on the number of bits. Therefore, the development of ALU, providing higher performance than the existing known solutions, is an actual task. In this work the analysis of ALU with

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3

Eshan, Kumar Sao, and B. Ramesh K. "Design and Implementation of ALU Chip Using D3l Logic." Journal of Control System and its Recent Developments 5, no. 1 (2022): 1–5. https://doi.org/10.5281/zenodo.6387932.

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<em>Central Processing Unit (CPU) is the heart of Computer, which converts data into information and set of electronic circuitry that executes stored data instructions. Central Processing Unit includes Arithmetic Logic Unit (ALU), Control Unit (CU) and Memory Unit (MU).Arithmetic Logic Unit (ALU) is the integral part of computer processor, that perform arithmetic and logical operations. A Proposed new logic family of low power dynamic logic called Data Driven Dynamic logic (D3L). It is based on 16 Sutras which are discovered by Sri Bharti Krishna. We implement a 64-bit ALU chip design Vedic mu

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Thakral, Shaveta, and Dipali Bansal. "High functionality reversible arithmetic logic unit." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (2020): 2329. http://dx.doi.org/10.11591/ijece.v10i3.pp2329-2335.

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Energy loss is a big challenge in digital logic design primarily due to impending end of Moore’s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are

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Shaveta, Thakral, and Bansal Dipali. "High functionality reversible arithmetic logic unit." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (2020): 2329–35. https://doi.org/10.11591/ijece.v10i3.pp2329-2335.

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Energy loss is a big challenge in digital logic design primarily due to impending end of Moore"s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are

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Vikesh, Ukande* Ankit Pandit. "HIGH SPEED LOW POWER 32 BIT ALU IMPLEMENTATION." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 10 (2016): 64–69. https://doi.org/10.5281/zenodo.159286.

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The main objective of project is to design and verify different operations of Arithmetic and Logical Unit (ALU). We have designed an 32 bit ALU which accepts two 32 bits numbers and the code corresponding to the operation which it has to perform from the user. The ALU performs the desired operation and generates the result accordingly. The different operations are arithmetical, the coding was written in VHDL and verified in I-Sim. The waveforms were obtained successfully. After the coding was done, the synthesis of the code was performed using Xilinx-ISE.

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7

Pradnya, Kshirsagar. "ENERGY EFFICIENT IMPROVED 4-Bit ALU DESIGN." International Scientific Journal of Engineering and Management 04, no. 04 (2025): 1–9. https://doi.org/10.55041/isjem02789.

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The 4-bit Arithmetic Logic Unit (ALU) is a fundamental component in digital systems, responsible for executing a range of arithmetic and logic operations on 4-bit binary inputs. This ALU design methodology outlines the construction of a 4-bit ALU capable of per- forming operations such as addition, subtraction, bitwise AND, OR, XOR, and bit-shifting (left and right). The architecture utilizes a 4-bit adder/subtractor for arithmetic operations, implementing two’s complement for subtraction. Logic operations are handled through standard logic gates (AND, OR, XOR), while shifting operations are f

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Liu, Yuguo, Chenyang Zhang, and Haoyi Zhang. "The Mechanism of The Arithmetic Logic Unit." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 97–108. http://dx.doi.org/10.54097/qzqpap16.

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The Arithmetic Logic Unit is widely used in electrical components nowadays such as the CPU in computers. The traditional research is based on the theory of a combination of multiple logic units, the results are not performed intuitional. This paper provides an introduction to the Arithmetic Logic Unit and its mechanisms, which consist of multiple logic gates to perform binary operations and send commands to the computer. The article discusses binary operations using logic gates, starting from the simplest one-bit half-adder to the more complex four-bit ALU, encompassing functions like addition

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Rakshith, Saligram1 Shrihari Shridhar Hegde1 Shashidhar A. Kulkarni1 H.R.Bhagyalakshmi1 and M.K. Venkatesha. "DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC LOGIC UNIT." International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013 4, no. 3 (2019): 01–16. https://doi.org/10.5281/zenodo.3342584.

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Reversible Logic is gaining significant consideration as the potential logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the outputs. Significant contributions have been made in the literature towards the design of fault tolerant reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is th

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Prahlada, P. Udupa, and B. Ramesh K. "VLSI Design and Verification of a Multi-Function Arithmetic Logic Unit." Journal of VLSI Design and its Advancement 7, no. 3 (2024): 37–47. https://doi.org/10.5281/zenodo.13709349.

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<em>Exploring an ALU Design in the VLSI Domain - Within modern processors like CPUs, FPUs, and GPUs, the Arithmetic Logic Unit (ALU) serves as a critical building block. In this review paper, we delve into the Very Large Scale Integration (VLSI) design of an ALU, exploring its functionality through meticulous simulation and testing. Leveraging the Xilinx ISE design suite 14.7, the study validates the proposed ALU's gate-level and chip-level implementation, ensuring its ability to execute nine essential operations: addition, subtraction, multiplication, shifting, comparison, AND, OR, NOT, and X

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Alharbi, Mohammed, Gerard Edwards, and Richard Stocker. "Reversible Quantum-Dot Cellular Automata-Based Arithmetic Logic Unit." Nanomaterials 13, no. 17 (2023): 2445. http://dx.doi.org/10.3390/nano13172445.

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Quantum-dot cellular automata (QCA) are a promising nanoscale computing technology that exploits the quantum mechanical tunneling of electrons between quantum dots in a cell and electrostatic interaction between dots in neighboring cells. QCA can achieve higher speed, lower power, and smaller areas than conventional, complementary metal-oxide semiconductor (CMOS) technology. Developing QCA circuits in a logically and physically reversible manner can provide exceptional reductions in energy dissipation. The main challenge is to maintain reversibility down to the physical level. A crucial compon

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Mrs. Leena Rathi. "Ancient Vedic Multiplication Based Optimized High Speed Arithmetic Logic." International Journal of New Practices in Management and Engineering 3, no. 03 (2014): 01–06. http://dx.doi.org/10.17762/ijnpme.v3i03.29.

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Here, we deal with most effective Vedic multiplication method dependent 4*4 bit arithmetic logic unit having high speed. In this paper, we will perform ALU operations. ALU is a development of research work that has been done for years so we have chosen this topic. Normally ALU is a heart of digital processor, central processing unit, microprocessor and micro controller. Every digital domain based technology has to depend on the performance of ALU. Hence, there is a necessity of ALU which generates high speeds which depends on the speed of multiplier. Therefore, we go for designing a 4-bit mult

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13

Kumar, Dasari Mahesh. "Single Bit Alu Using Reversible Logic Gates." INTERNATIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 06 (2025): 1–9. https://doi.org/10.55041/ijsrem49514.

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Abstract— In this digital world, technology depends on the operations of A.L.U to decide the system performance. The need for an Arithmetic Logic Unit (ALU) is as important as the computer, simply because ALU forms the fundamental part of any Central Processing Unit (CPU). And so the encryption of an ALU is highly mandatory for the safety of the device as there are hardly any device without an ALU. This paper deals with the design of an single-bit ALU using a hardware description language, HDL that is structurally modelled. The results are verified and synthesized through Xilinx. Keywords- ALU

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Ramakrishna, M. "N-Bit ALU Design Using Vedic Mathematics." INTERNATIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 05 (2025): 1–9. https://doi.org/10.55041/ijsrem48997.

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Abstract - The Arithmetic and Logic Unit (ALU) is a central component in modern computing systems, responsible for performing core arithmetic and logical operations. This paper proposes an N-bit ALU designed using Vedic mathematical principles to achieve improved speed and reduced power consumption. Leveraging the Urdhva Tiryakbhyam principle from Vedic mathematics, the ALU integrates an efficient multiplier along with high-performance arithmetic and logic units. The architecture, developed using Verilog HDL and synthesized through Xilinx Vivado, exhibits lower delay and efficient hardware usa

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Aparna, Gupta*1 Dr. Rita Jain2 &. Dr. R. P. Singh3. "PHYSICAL DESIGN, LAYOUT AND SIMULATION USING C5 PROCESS TECHNOLOGY OF 8 BIT ARITHMETIC AND LOGIC UNIT." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 5, no. 7 (2018): 510–21. https://doi.org/10.5281/zenodo.1325039.

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A critical component of the microprocessor, the core component of central processing unit, Arithmetic and Logical Unit  (ALU) comprises of the combinational logic that implements logic operations such as AND and OR, and arithmetic operations such as addition, subtraction, and multiplication. In this proposed work, a 8-bit ALU is designed, implemented and simulated using the Electric CAD and SPICE software. The proposed design is a 8-bit ALU that can perform operations like: A AND B, A OR B, A + B (addition), and A - B (subtraction) and all possible arithmetic and logical operations. Physi

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Anand, Krishnan S., and B. Ramesh K. "4-BIT Arithmetic Logic Unit (ALU) using Full Swing GDI Technique." Journal of Advancement in Electronics Design 4, no. 3 (2022): 1–8. https://doi.org/10.5281/zenodo.6344301.

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<em>This paper presents a layout of a 4-bit mathematic logic unit (ALU) via taking vantage of the idea of gate diffusion input (GDI) technique. ALU is the maximum crucial and middle element of vital processing unit as well as of numbers of embedded machine and microprocessors. In this, ALU consists of 4x1 multiplexer, 2x1 multiplexer and occasional power complete adder designed to implements logic operations. Complete swing GDI cells are used inside the design of multiplexers and full adder that are the related to comprehend ALU. The simulation is carried out DSCH3.5 and mircowind3.five simula

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Sasamal, Trailokya Nath, Anand Mohan, and Ashutosh Kumar Singh. "Efficient Design of Reversible Logic ALU Using Coplanar Quantum-Dot Cellular Automata." Journal of Circuits, Systems and Computers 27, no. 02 (2017): 1850021. http://dx.doi.org/10.1142/s0218126618500214.

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Quantum-dot Cellular Automata (QCA) based reversible logic is the utmost necessity to achieve an architecture at nano-scale, which promises extremely low power consumption with high device density and faster computation. This paper emphasises on the design of an efficient reversible Arithmetic Logical Unit (ALU) block in QCA technology. We have considered [Formula: see text] RUG (Reversible Universal Gate) as the basic unit, and also report a HDLQ model for RUG with 52.2% fault tolerance capability. Further, the reversible ALU has synthesized with reversible logic unit (RLU) and reversible ari

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18

D. R. V. A. Sharath Kumar. "Low Power-Area Implementation of 4-Bit ALU in Cadence Virtuoso Platform." Journal of Electrical Systems 20, no. 3 (2024): 4126–34. http://dx.doi.org/10.52783/jes.5441.

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The 4-bit ALU designed using Cadence is a arithmetic logic unit capable of performing various operations on 4-bit binary numbers. It takes in two 4-bit inputs, A and B, and producesa4-bitoutput, F, along with carry-out and overflow flags. The design incorporates a combination of combinatorial and sequential logic circuits to achieve the desired functionality. The ALU supports basic arithmetic operations like addition and subtraction, as well as logical operations such as AND, OR, XNOR and XOR. It utilizes multiplexers, adders, Code Converters and logic gates to perform the different operations

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Vinyas, K. S., and K.B.Ramesh. "Design and Implementation of Arithmetic Unit using Vedic Multiplier." Journal of Optoelectronics and Communication 6, no. 2 (2024): 39–46. https://doi.org/10.5281/zenodo.11632356.

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<em>The Arithmetic Logic Unit (ALU) is an essential part of digital computing that performs arithmetic and logical operations. The goal of this study is to improve computational efficiency, especially in multiplication operations, by investigating the integration of dedicated multiplier circuits inside the ALU architecture. The design and implementation of a logic unit utilizing Vedic multiplier principles offer a promising avenue for advancing the efficiency and performance of digital circuits. By harnessing ancient mathematical wisdom in modern computing applications, this research contribut

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Likitha, S., and B. Ramesh K. "Design and Implementation of Arithmetic and Logic Unit (ALU) using Novel Reversible Gates in Quantum Cellular Automata." Journal of VLSI Design and its Advancement 5, no. 1 (2022): 1–15. https://doi.org/10.5281/zenodo.6375786.

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<em>In the contemporary scenario, power consumption, speed, size and heat dissipation are the huge challenge in the semiconductor industries. The conceivable arrangement for these two issues is the Reversible Logic and Quantum Cellular Automata (QCA). In this paper Novel Reversible Gates are proposed with Reversibility and Universality. The Arithmetic and Logic Unit (ALU) is designed with the proposed Reversible Gates in Reversible Logic. The Arithmetic and Logic Unit is designed by setting the control inputs for each unit. The parameters taken into consideration are Quantum Cost (QC), Garbage

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Fei, Xiang. "Optimized Design and Applications of Arithmetic Logic Units: Addressing Power Efficiency and Performance in Diverse Computing Applications." Applied and Computational Engineering 128, no. 1 (2025): 132–37. https://doi.org/10.54254/2755-2721/2025.20216.

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In modern computer systems, the Arithmetic Logic Unit (ALU) is the core component of the central processing Unit (CPU) and performs basic tasks such as arithmetic operations, logic operations, and data transmission. With the development of information technology, the demand for computing is growing, the requirements for computing accuracy, speed and energy consumption are becoming more stringent. The design and optimization of ALU is directly related to the overall performance and energy efficiency of the system, so it becomes the focus of research and the key to technological breakthroughs. T

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Shaveta, Thakral, and Bansal Dipali. "Novel high functionality fault tolerant ALU." TELKOMNIKA Telecommunication, Computing, Electronics and Control 18, no. 1 (2020): 234–39. https://doi.org/10.12928/TELKOMNIKA.v18i1.12645.

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Miniaturization, cost, functionality, complexity and power dissipation are important and necessary design traits which need attention in circuit designing. There is a trade off between miniaturization and power dissipation. Smart technology is always searching for new paradigms to continue improve power dissipation. Reversible logic is one of smart computing deployed to avoid power dissipation. Researchers have proposed many reversible logic-based arithmetic and logic units (ALU). However, the research in the area of fault tolerant ALU is still under progress. The aim of this paper is to bridg

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Rakshan, Ravindra Kulkarni, and B. Ramesh K. "Design and Implementation of a Low Powered Self-Testable ALU." Journals of Advancement in Electronics Design 5, no. 1 (2022): 1–9. https://doi.org/10.5281/zenodo.6384174.

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<em>Arithmetic logic unit (ALU) is an important part of the CPU as it performs all arithmetic and logic operations and calculations required by all processes running inside the CPU. Being such an important part within the processor it requires more power and therefore would be efficient and feasible if it could run at low power and test for faults in the circuit itself. This document focuses entirely on building a low-power ALU with the implementation of a built-in self-test (BIST) mechanism for efficient arithmetic and logical operations. The design uses energy-efficient circuits such as Wall

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Gadim, Mahya Rahimpour, and Nima Jafari Navimipour. "Quantum-Dot Cellular Automata in Designing the Arithmetic and Logic Unit: Systematic Literature Review, Classification and Current Trends." Journal of Circuits, Systems and Computers 27, no. 10 (2018): 1830005. http://dx.doi.org/10.1142/s0218126618300052.

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Quantum-dot Cellular Automata (QCA) presents a new model at Nano-scale for possible substitution of conventional Complementary Metal–Oxide–Semiconductor (CMOS) technology. On the other hand, an Arithmetic Logic Unit (ALU) is a digital electronic circuit which performs arithmetic and bitwise logical operations on integer binary numbers. Therefore, QCA-based ALU is an important part of the processor in order to develop a full capability processor. Although the QCA has become very important, there is not any comprehensive and systematic work on studying and analyzing its important techniques in t

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Alshortan, Hammad H., Yasser Almalaq, and Muhammad Imran Khan. "Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit." International Journal of ADVANCED AND APPLIED SCIENCES 10, no. 9 (2023): 68–74. http://dx.doi.org/10.21833/ijaas.2023.09.008.

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This research paper investigates the influence of different initial design techniques on the area, timing, and power aspects of technology-mapped designs. As a practical case study, we undertake the design and analysis of a 32-bit arithmetic logic unit (ALU) utilizing two distinct adder approaches. The ALU, a fundamental component of all processors, comprises three major units: the Adder responsible for signed and unsigned number addition and subtraction, the Logic unit which handles bitwise logical operations, and the Shifter unit facilitates arithmetic and logical shift operations. The two a

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Shukla, Vandana, O. P. Singh, G. R. Mishra, and R. K. Tiwari. "A Novel Approach to Design 2-bit Binary Arithmetic Logic Unit (ALU) Circuit Using Optimized 8:1 Multiplexer with Reversible logic." Journal of Communications Software and Systems 11, no. 2 (2015): 104. http://dx.doi.org/10.24138/jcomss.v11i2.109.

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Reversible circuit designing is the area where researchers are focussing more and more for the generation of low loss digital system designs. Researchers are using the concept of Reversible Logic in many areas such as Nanotechnology, low loss computing, optical computing, low power CMOS design etc. Here we have proposed a novel design approach for a 2-bit binary Arithmetic Logic Unit (ALU) using optimized 8:1 multiplexer circuit with reversible logic concept [1]. This ALU circuit can perform complement, transfer, addition, subtraction, multiplication, OR, XOR, NAND functions on given values. T

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Divij, Joshi, and Ramesh K.B. "Design of an ALU using a Hybrid Synchronous Counter." Journal of Advancement in Electronics Design 7, no. 3 (2024): 34–39. https://doi.org/10.5281/zenodo.13729431.

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<em>In computing, an arithmetic logic unit is a combined digital circuit that performs bitwise and mathematical operations on integers and binary integers. The aim of this paper is to design an ALU using 8-bit. Programmable synchronous counter, that is a combination of straight and twisted ring counters. It performs ALU operations on two 4-bit binary values and outputs the result. An ALU performs the arithmetic and logical operations on two 4- bit numbers. These operations include addition, subtraction, logical AND, OR, XNOR, LEFT SHIFT AND RIGHT SHIFT. Multiple ALU outputs are possible based

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ZHao, Hong-Quan, and Seiya Kasai. "WPG-Controlled Quantum BDD Circuits with BDD Architecture on GaAs-Based Hexagonal Nanowire Network Structure." Journal of Nanomaterials 2012 (2012): 1–6. http://dx.doi.org/10.1155/2012/726860.

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One-dimensional nanowire quantum devices and basic quantum logic AND and OR unit on hexagonal nanowire units controlled by wrap gate (WPG) were designed and fabricated on GaAs-based one-dimensional electron gas (1-DEG) regular nanowire network with hexagonal topology. These basic quantum logic units worked correctly at 35 K, and clear quantum conductance was achieved on the node device, logic AND circuit unit, and logic OR circuit unit. Binary-decision-diagram- (BDD-) based arithmetic logic unit (ALU) is realized on GaAs-based regular nanowire network with hexagonal topology by the same fabric

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Karthik, M. Ram, and B. Ramesh K. "Evaluation of Performance Enhancement by Splitting ALU." Journal of VLSI Design and its Advancement 5, no. 1 (2022): 1–5. https://doi.org/10.5281/zenodo.6376027.

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<em>Microprocessors usually have a single module that performs arithmetic operations on integer values. The reason is that because many of the different arithmetic and logical operations can be performed using similar hardware. The component that performs these operations is known as the <strong>Arithmetic Logic Unit </strong>(ALU). Performance enhancement has been a primary design goal for designers for a long time. Modern automation technology demands for reliable low-cost controllers, required for specific applications. The restricted resources limit the number of functional units out there

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Kumar, A. Hemanth. "Design and Implementation of a 3-bit ALU with Integrated 7-Segment Display on FPGA." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 11 (2024): 1–6. http://dx.doi.org/10.55041/ijsrem38905.

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This paper describes the design and implementation of a 3-bit Arithmetic Logic Unit (ALU) with integrated 7-segment display output, deployed on an FPGA platform. The objective of this project is to efficiently perform and display basic arithmetic and logic operations, including addition, subtraction, AND, OR, XOR, and NOT, with an FPGA-based ALU. A control signal selects the operation, and the ALU's 3-bit result is decoded and displayed on a 7-segment interface for clear output visualization. The ALU design is coded in Verilog and includes logic to manage carry and overflow in arithmetic funct

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Hameed, Ahmed Lateef, Maan Hameed, and Raed Abdulkareem Hasan. "A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU Design." Iraqi Journal of Industrial Research 9, no. 3 (2022): 12–22. http://dx.doi.org/10.53523/ijoirvol9i3id279.

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Clock gating is an effective way to decrease dissipated power in synchronous design. The most effective way to do this is by masking the clock that turns toward the unused part of design. In this paper, a comparative evaluation of power consumption in existing clock gating techniques in Arithmetic Logical Unit (ALU) design was achieved. an innovative signal clock gating method offers extra immunity in the direction of the present issue in an accessible mechanism. A Gated Clock Generation designs using a tri-state connection and logic gate, generated by the set of bubbled input with NAND gate,

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Patel, Mr Chandrashekhar, and Prof Abhay Saxena. "Design SSTL based Arithmetic Logic Unit for Internet of Things Based Processor." International Journal of Engineering and Advanced Technology 11, no. 4 (2022): 142–45. http://dx.doi.org/10.35940/ijeat.d3477.0411422.

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Now days in area of computer science Green computing is creating revolution by bringing some new digital component with less power consumption. Our research work is created on this idea. In this paper our objective is to come up with High Performance ALU design for IOT based processor by reducing the power consumption. For calculating total power consumption of FPGA based ALU we used five different voltage (0.95,1.0,1.05,1.10,1.15,1.20) and calculated IOs, Leakage power at four different IOs standard (SSTL18_II, SSTL15, SSTL135, SSTL15_R). In experiment we found the best result with SSTL15_R I

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Mr., Chandrashekhar Patel, and Abhay Saxena Prof. "Design SSTL based Arithmetic Logic Unit for Internet of Things Based Processor." International Journal of Engineering and Advanced Technology (IJEAT) 12, no. 4 (2022): 142–45. https://doi.org/10.35940/ijeat.D3477.0411422.

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<strong>Abstract: </strong>Now days in area of computer science Green computing is creating revolution by bringing some new digital component with less power consumption. Our research work is created on this idea. In this paper our objective is to come up with High Performance ALU design for IOT based processor by reducing the power consumption. For calculating total power consumption of FPGA based ALU we used five different voltage (0.95,1.0,1.05,1.10,1.15,1.20) and calculated IOs, Leakage power at four different IOs standard (SSTL18_II, SSTL15, SSTL135, SSTL15_R). In experiment we found the

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Sumari, Arwin Datumaya Wahyudi, Sukriya Hijriana, and Denny Dermawan. "Design and Implementation of 12-Bit Arithmetic Logic Unit with 8 Operation Codes to Field Programmable Gate Array." ELKHA 15, no. 2 (2023): 98. http://dx.doi.org/10.26418/elkha.v15i2.64041.

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Digital system has been a part of human life since the invention of the computer with a microprocessor as the central brain. At the heart of a processor is an Arithmetic Logic Unit (ALU) that handles arithmetic and logic operations. The need for high-speed computation to handle complex computations demands microprocessors with higher performance. The existing 4-opcode 8-bit ALU cannot handle multiplication operations, so a solution is needed. In this research, while raising the appeal of beginners, a 12-bit ALU with eight operation codes (opcode) was designed and implemented in Xilinx’s Field

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Aditya, Srinivas, and Ramesh K.B. "Design and Implementation of an Optimized ALU using a Square Root Carry Select Adder." Journal of Optoelectronics and Communication 6, no. 3 (2024): 18–26. https://doi.org/10.5281/zenodo.12720733.

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<em>Arithmetic logic units (ALUs) are strong combinational circuits in digital computers that carry out arithmetic and logical operations. The Parallel Adder embedded within the Arithmetic Logic Unit (ALU) holds significance, yet the time-consuming nature of carry propagation (CP) during addition demands consideration. To cater to the requirements of low-power and area-efficient applications, the paper suggests an ALU design that integrates a modified Square Root Carry Select Adder (SQRT CSLA). Additionally, for applications necessitating enhanced speed, an alternative ALU design is introduced

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Ayush, Bhardwaj, and B. Ramesh K. "Designing a Graphics Processing Unit with advanced Arithmetic Logic Unit Resulting Improved Performance." Research and Applications: Emerging Technologies 6, no. 3 (2024): 38–46. https://doi.org/10.5281/zenodo.12720907.

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<em>This paper explores microprocessor intricacies, particularly the central processing unit (CPU) and the graphics processing unit (GPU). The CPU, dubbed a computer's brain, features critical components like the Control Unit (CU), Arithmetic Logic Unit (ALU), and Memory Unit (MU), orchestrating instruction execution and system resource management. Contrarily, GPUs, initially for graphics rendering, now excel in parallel processing, aiding tasks beyond graphics. It compares CPU and GPU architectures, emphasizing their parallel processing and memory hierarchy. The graphics rendering pipeline's

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Md, Khairul Islam, and Nath Biswas Satyendra. "Comparative Study of a Low-Power High-Speed Arithmetic Logic Unit Design Techniques." Journal of VLSI Design and its Advancement 7, no. 2 (2024): 19–30. https://doi.org/10.5281/zenodo.11260037.

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<em>The Arithmetic Logic Unit is the most important unit of a microprocessor. It performs complex operations for the processing unit and is considered as the fundamental building block of a CPU. Because of its importance in the VLSI industry, it is always a major challenge to make it high-speed, low-power consuming, robust, and compact. In this paper five different techniques, CMOS, GDI, MGDI, TGL, and PTL are used to design a 1-bit ALU with 8 different logical and arithmetic operations. The results are compared with respect to three different parameters, Transistor count, Power dissipation, a

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MOHAN, Sri C. MURALI, and T. SWATHI. "64-Bit ALU Design Using Reversible Gates." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 04 (2025): 1–9. https://doi.org/10.55041/ijsrem44380.

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The implementation of reversible gates to build a 64-bit Arithmetic Logic Unit (ALU) is a promising contribution to the area of quantum computing as well as low-power digital circuit design. Reversible logic gates provide the benefit of not losing information throughout the process of computation (unlike traditional irreversible gates), which leads to energy being dissipated less frequently. The purpose of designing reversible logic is to decrease the power consumption and heat dissipation challenges present in modern Very Large Scale Integration (VLSI) design. The 64-bit ALU architecture has

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Sayyam, Jain, and Ramesh K.B. "Optimized Single Precision Floating-Point ALU Design and Implementation for RISC Processors on FPGA." Recent Trends in Analog Design and Digital Devices 7, no. 2 (2024): 29–35. https://doi.org/10.5281/zenodo.11609206.

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<em>Single Precision Floating-Point Arithmetic Logic Units (FPALUs) play a crucial role in the performance and functionality of Reduced Instruction Set Computer (RISC) processors. This paper presents the design and implementation of an FPALU tailored for a RISC processor on a Field-Programmable Gate Array (FPGA). The FPALU is optimized for single precision floating-point arithmetic operations, including addition, subtraction, multiplication, and division. The design methodology encompasses the development of essential logic blocks, such as the op code decoder, arithmetic block, logical block,

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Zahoor, Furqan, Fawnizu Azmadi Hussin, Farooq Ahmad Khanday, Mohamad Radzi Ahmad, and Illani Mohd Nawi. "Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM)." Micromachines 12, no. 11 (2021): 1288. http://dx.doi.org/10.3390/mi12111288.

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Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated. Ternary logic circuit implementation with carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) integration is considered as a possible technology option. CNTFETs are currently being preferred for implementing ternary circuits due to their desirable multiple threshold voltage and geometry-dependent properties, whereas the RRAM is used due to its multilevel cell capability which enables storage of mult

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Arunabala, Dr C. "Design of a 4 bit Arithmetic and Logical unit with Low Power and High Speed." International Journal of Innovative Technology and Exploring Engineering 10, no. 5 (2021): 87–92. http://dx.doi.org/10.35940/ijitee.e8660.0310521.

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In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using the different modules. The Various modules are AND gate & OR gate designed with six transistors, While the XOR modules is designed with both eight transistors & six transistors. The six transistor XOR module gives optimized results. Another one is the four by one multiplexer designed with eight transistors implemented using Pass transistor logic (PTL) style. The full adder module is designed by using 18 transistors implemented through PTL style. Here because of PTL style the number of transistor

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Dr.C.Arunabala*, Ch.Jyothirmayi, N. S. V. Sreeja.T D, Burra Hrithika Suma, Udumula Reddy, and I.R.AnushaDevi. "Design of a 4 bit Arithmetic and Logical unit with Low Power and High Speed." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 10, no. 5 (2021): 87–92. https://doi.org/10.35940/ijitee.E8660.0310521.

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In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using the different modules. The Various modules are AND gate & OR gate designed with six transistors, While the XOR modules is designed with both eight transistors & six transistors. The six transistor XOR module gives optimized results. Another one is the four by one multiplexer designed with eight transistors implemented using Pass transistor logic (PTL) style. The full adder module is designed by using 18 transistors implemented through PTL style. Here because of PTL style the number of transistor

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Jain, Meeth, and KB Ramesh. "Adders implemented on VLSI for high-speed ALU." International Journal for Research in Applied Science and Engineering Technology 10, no. 3 (2022): 46–50. http://dx.doi.org/10.22214/ijraset.2022.40523.

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Abstract: This study focuses on the development of high-speed adder circuits utilising the Hardware Description Language (HDL) within the Xilinx ISE 9.2i platform, as well as their implementation on Field Programmable Gate Arrays (FPGAs) to analyse planning parameters. The main building component of the Arithmetic Logic Unit (ALU) is the adder, and hence the performance of the Control Processing Unit is determined by it (CPU). The ALU and the register file are the two primary components of processors. The carry-chain extra operation could be one of the important channels within an ALU. In this

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Oliveira, Alexandre M. De, Jorge R. B. Garay, A. C. Lins Rodrigues, João F. Justo, and Sergio T. Kofuji. "A Teaching Methodology Based On The ALU 8bit RISC Design VLSI Full Custom for Classes on Computer Architecture and Digital Electronic." International Journal of Computer Architecture Education 2, no. 1 (2013): 25–28. https://doi.org/10.5753/ijcae.2013.4948.

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This work presents a teaching methodology for the design and simulation of digital circuits, focusing on an 8-bit Arithmetic Logic Unit (ALU) using IBM 7WL SiGe BiCMOS 180nm VLSI Full-Custom technology and the LTSpice 4 tool, under GNU license. The ALU was designed to perform arithmetic operations such as addition, subtraction, and greater than, less than, and equality comparisons, as well as logical operations like AND and OR bitwise. Simulation results showed the functionality of the proposed architecture, with a maximum response delay of about 1ns. The methodology was successfully implement

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Chakma, Clinton, Fairuza Laila, and Ismat Rahman. "Design and Implementation of a 2-input Arithmetic and Logic Unit using Quantum-dot Cellular Automata." Dhaka University Journal of Applied Science and Engineering 8, no. 1 (2024): 26–31. http://dx.doi.org/10.3329/dujase.v8i1.72987.

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Quantum-Dot-Cellular Automata (QCA), an emerging nanotechnology rooted in Coulomb repulsion, holds the ability to supplant orthodox complementary metal-oxide semiconductor (CMOS) technology. Its distinctive advantages lie in ultra-low power consumption, fast switching speed, and high-density structures. This study conducts an extensive literature review to introduce an Arithmetic and Logic Unit (ALU) based on QCA principles. The proposed QCA-based ALU incorporates fundamental logic gates, adders, and subtractors, leveraging the latest XOR gate. Utilizing simulation via QCA Designer 2.0.3, an i

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Huang, Zhouhao. "Design and implementation of an 8-bit ALU based on verilog HDL." Theoretical and Natural Science 14, no. 1 (2023): 180–85. http://dx.doi.org/10.54254/2753-8818/14/20240939.

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Many modern processors incorporate an Arithmetic Logic Unit (ALU) as an integral component. The ALU plays a pivotal role in arithmetic and logical operations, making it a fundamental block in processor architecture. Utilizing software tools like Quartus II and ModelSim, one can seamlessly design, implement, and simulate an 8-bit ALU. This research focuses on creating an ALU that can perform a broad range of operations, including Addition, Subtraction, Multiplication, Division, Shifting, Rotation, AND, OR, XOR, NOR, NAND, XNOR, and Comparison. With these 16 operations in mind, the ALUs circuitr

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Rao, Dr G. Anantha, and Gopi Kommuju. "A NOVEL LOW POWER ALU DESIGNED BY USING HYBRID STT-MTJ/CMOS CIRCUIT." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 07, no. 12 (2023): 1–13. http://dx.doi.org/10.55041/ijsrem27641.

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The rise in power dissipation when the technology descends into the deep submicron zone is one of the main issues for CMOS technology due to its non-volatility, high speed, high endurance, CMOS compatibility, and primarily the low power dissipation. magnetic tunnel junction (MTJ) working on Spin transfer torque (STT). Switching mechanism is recognized as one of the most promising spintronic devices for post-CMOS era. This device can provide solutions for the issues posed by existing CMOS technology. We have put out a brand-new hybrid STT- MTJ/CMOS circuit-based logic-in-memory (LIM) P- magneti

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Nagarjuna, Bathula. "Design and Synthesis of Optimized RISC-Based Arithmetic Logic Unit (ALU) using Cadence Genus." International Journal for Research in Applied Science and Engineering Technology 13, no. 6 (2025): 697–703. https://doi.org/10.22214/ijraset.2025.72208.

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This work presents the design and optimization of a RISC-based Arithmetic Logic Unit (ALU), a critical component in modern computing architectures that require efficient computation with minimal power consumption and reduced silicon area. Through a systematic approach that incorporates architectural modeling, RTL implementation, and synthesis using Cadence Genus, the study emphasizes the transformation of high-level designs into optimized silicon realizations capable of meeting stringent performance, area, and power constraints. The design leverages the principles of Reduced Instruction Set Co

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Harini, G. Iyar, and B. Ramesh K. "Design and Implementation of Quantum-Inspired ALU: A High-Performance Approach." Journal of Advancement in Electronics Design 7, no. 2 (2024): 16–27. https://doi.org/10.5281/zenodo.10996471.

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<em>This paper introduces a Quantum-Inspired Arithmetic Logic Unit (ALU) for high-performance processors, focusing on overcoming classical ALU limitations by leveraging quantum principles. The architectural design meticulously arranges quantum gates, including the Hadamard gate and CNOT gate, within the ALU framework. These gates play vital roles in quantum computation, necessitating precise placement for efficient data processing. Coherence optimization strategies, crucial for stability, ensure accurate quantum gate performance. Quantum parallelism, facilitated by coherence, enhances computat

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Dudhane, Tanaji M., and T. Ravi. "Design and Implementation of Extended 16 Bit Co-Operative Arithmetic and Logic Unit (CALU) for 16 Bit Instructions." Journal of Low Power Electronics 15, no. 3 (2019): 309–14. http://dx.doi.org/10.1166/jolpe.2019.1613.

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CPU architecture has experienced great innovation in its architecture, from 8 bit to 64 bit, CISC to RISC, Single core to multi-core and single pipelined logic to deep multi-pipelined system. Today in an era of 64 bit architectures, 8 bits are still very relevant and has not lost its position and being used in many applications. Hence this research work deals with 8 bit CPU architecture and its features enhancement to make the 8 bit case very relevant in an era of 64 bit. The co-operative ALU, as name suggests, works in tandem with existing ALU and performs 16 bits operations. The specially de

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