Relevant bibliographies by topics / ASIC - Application Specific Integrated Circuit - Processor

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'ASIC - Application Specific Integrated Circuit - Processor'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'ASIC - Application Specific Integrated Circuit - Processor.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "ASIC - Application Specific Integrated Circuit - Processor"

1

FIJALKOWSKI, BOGDAN T., and JAN W. KROSNICKI. "CONCEPTS OF ELECTRONICALLY-CONTROLLED ELECTROMECHANICAL/MECHANOELECTRICAL STEER-, AUTODRIVE- AND AUTOABSORBABLE WHEELS FOR ENVIRONMENTALLY-FRIENDLY TRI-MODE SUPERCARS." Journal of Circuits, Systems and Computers 04, no. 04 (December 1994): 501–16. http://dx.doi.org/10.1142/s0218126694000296.

Full text
Abstract:
Concepts of the electronically-controlled electromechanical/mechanoelectrical Steer-, Autodrive- and Autoabsorbable Wheels (SA2W) with their brushless Alternating Current-to-Alternating Current (AC-AC), Alternating Current-to-Direct Current-Alternating Current (AC-DC-AC) and/or Direct Current-to-Alternating Current (DC-AC)/Alternating Current-to-Direct Current (AC-DC) macroelectronic converter commutator (macro-commutator) wheel-hub motors/generators with the Application Specific Integrated Matrixer (ASIM) macroelectronic converter commutators (ASIM macrocommutators) and Application Specific Integrated Circuit (ASIC) microelectronic Neuro-Fuzzy (NF) computer (processor) controllers (ASIC NF microcontrollers) for environmentally-friendly tri-mode supercars (advanced ultralight hybrids) have been conceived by the first author and designed by both authors with the Cracow University of Technology’s Automotive Mechatronics Research and Development (R&D) Team. These electromechanical/mechanoelectrical wheel-hub motors/generators, respectively, for instance, can be composed of the outer rotor with the Interior Permanent Magnet (IPM) poles and the inner stator that has the three-phase armature winding. The macroelectronic converter commutator establishes the AC-AC cycloconverter, AC-DC rectifier-DC-AC inverter and/or DC-AC inverter/AC-DC rectifier ASIM macrocommutator. The microelectronic NF computer (processor) controller establishes the ASIC microcomputer-based NF microcontroller. By adopting continuous semiconductor bipolar electrical valves in the high-power ASIM, it has been able to increase the commutation (switching) frequency and reduce harmonic losses of the electromechanical/mechanoelectrical wheel-hub motors/generators, respectively.
APA, Harvard, Vancouver, ISO, and other styles
2

Lee, Jae-Eun, Ji-Won Kang, Woo-Suk Kim, Jin-Kyum Kim, Young-Ho Seo, and Dong-Wook Kim. "Digital Image Watermarking Processor Based on Deep Learning." Electronics 10, no. 10 (May 15, 2021): 1183. http://dx.doi.org/10.3390/electronics10101183.

Full text
Abstract:
Much research and development have been made to implement deep neural networks for various purposes with hardware. We implement the deep learning algorithm with a dedicated processor. Watermarking technology for ultra-high resolution digital images and videos needs to be implemented in hardware for real-time or high-speed operation. We propose an optimization methodology to implement a deep learning-based watermarking algorithm in hardware. The proposed optimization methodology includes algorithm and memory optimization. Next, we analyze a fixed-point number system suitable for implementing neural networks as hardware for watermarking. Using these, a hardware structure of a dedicated processor for watermarking based on deep learning technology is proposed and implemented as an application-specific integrated circuit (ASIC).
APA, Harvard, Vancouver, ISO, and other styles
3

Majerus, Steve J. A., Daniel T. Goff, and Walter Merrill. "A 200 °C Motor Control ASIC." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000159–64. http://dx.doi.org/10.4071/hitec-wa15.

Full text
Abstract:
A custom application-specific integrated circuit (ASIC) has been designed for positional control of brushless DC or servo motors in high-temperature (>200 °C) environments. Applications would include valve and position control for aerospace and industrial systems. Patented high-temperature circuit design techniques facilitate hightemperature operation from a conventional, low-cost, 0.5-micron bulk CMOS foundry process. The ASIC is highly integrated to enable software- and processor-free local control of motor position, and uses external power MOSFETs for motor commutation. Motor position can be controlled in open- or closed-loop modes with an integrated rotational variable displacement transformer (RVDT) direct digital synthesis (DDS) waveform generator, rail-to-rail op-amp driver and demodulation circuit. The ASIC can accept both analog (0–10 V) or digital (SPI bus) position setpoint commands from an external controller. Motor position is indicated by both analog and digital output signals. The full-scale displacement of the controlled motor is programmable from 5 to 8 bits of resolution, permitting 32–256 positions of control. Safety features such as a 500-ms power-on delay, overtemperature and motor overcurrent detection, and control signal undervoltage lockout were included to minimize the need for external control. ASIC bench-test results confirmed circuit functionality at ambient temperatures up to 225 °C using room-temperature power MOSFETs and motor load. ASIC performance at the 8-bit level was demonstrated, although the clock oscillator frequency shifted by about 15% over the full temperature range. Control of the motor at 200 °C was also demonstrated, although moderate loss of motor holding torque was observed due to internal heat generation in the motor. The ASIC was combined with commercially-available off-the-shelf high-temperature components on a printed wiring board (PWB) to form a compact (4 × 3.5 inch) motor control demonstration system capable of prolonged operation at temperatures beyond 200 °C. Environmental and long-term testing of the PWB is planned to demonstrate system reliability.
APA, Harvard, Vancouver, ISO, and other styles
4

Gao, Zhenyi, Bin Zhou, Yang Li, Lei Yang, Xiang Li, Qi Wei, Hongyang Chu, and Rong Zhang. "Design and Implementation of an On-Chip Low-Power and High-Flexibility System for Data Acquisition and Processing of an Inertial Measurement Unit." Sensors 20, no. 2 (January 14, 2020): 462. http://dx.doi.org/10.3390/s20020462.

Full text
Abstract:
For signal processing of a Micro-Electro-Mechanical System (MEMS) Inertial Measurement Unit (IMU), a digital-analog hybrid system-on-chip (SoC) with small area and low power consumption was designed and implemented in this paper. To increase the flexibility of the processing circuit, the designed SoC integrates a low-power processor and supports three startup or debugging modes for different application scenarios. An application-specific computing module and communication interface are designed in the circuit to meet the requirements of IMU signal processing. The configurable clock allows users to dynamically balance computing speed and power consumption in their applications. The chip was taped out under SMIC 180 nm CMOS technology and tested for performance. The results show that the chip’s maximum running frequency is 105 MHz. The total area is 33.94 mm 2 . The dynamic and static power consumption are 0.65 mW/MHz and 0.30 mW/MHz, respectively. When the system clock is 25 MHz, the dynamic and static power consumption of the chip is 76 mW and 66 mW, and the dynamic and static power consumption of the FPGA level are 634 mW and 520 mW. The results verify the superiority of the application specific integrated circuit (ASIC) solution in terms of integration and low power consumption.
APA, Harvard, Vancouver, ISO, and other styles
5

Ibrahim, Atef, and Fayez Gebali. "Word-Based Systolic Processor for Field Multiplication and Squaring Suitable for Cryptographic Processors in Resource-Constrained IoT Systems." Electronics 10, no. 15 (July 25, 2021): 1777. http://dx.doi.org/10.3390/electronics10151777.

Full text
Abstract:
Internet of things (IoT) technology provides practical solutions for a wide range of applications, including but not limited to, smart homes, smart cities, intelligent grid, intelligent transportation, and healthcare. Security and privacy issues in IoT are considered significant challenges that prohibit its utilization in most of these applications, especially relative to healthcare applications. Cryptographic protocols should be applied at the different layers of IoT framework, especially edge devices, to solve all security concerns. Finite-field arithmetic, particularly field multiplication and squaring, represents the core of most cryptographic protocols and their implementation primarily affects protocol performance. In this paper, we present a compact and combined two-dimensional word-based serial-in/serial-out systolic processor for field multiplication and squaring over GF(2m). The proposed structure features design flexibility to manage hardware utilization, execution time, and consumed energy. Application Specific Integrated Circuit (ASIC) Implementation results of the proposed word-serial design and the competitive ones at different embedded word-sizes show that the proposed structure realizes considerable saving in the area and consumed energy, up to 93.7% and 98.2%, respectively. The obtained results enable the implementation of restricted cryptographic primitives in resource-constrained IoT edge devices such as wearable and implantable medical devices, smart cards, and wireless sensor nodes.
APA, Harvard, Vancouver, ISO, and other styles
6

Sajjad, Muhammad, Mohd Zuki Yusoff, and Muhammad Ahmed. "A Customized Floating-point Processor Design for FPGA and ASIC based Thermal Compensation in High-precision Sensing." Annals of Emerging Technologies in Computing 5, no. 1 (January 1, 2021): 40–50. http://dx.doi.org/10.33166/aetic.2021.01.004.

Full text
Abstract:
There are many types of sensors which require large dynamic range as well as high accuracy at the same time. Barometric altimeter is an example of such sensors. The signal processing techniques in the sensors are normally implemented using Field Programmable Gate Arrays (FPGAs) or Application-Specific Integrated Circuits (ASICs). The sensing variable in such type of the sensors is unwantedly environment dependent. So, for ensuring accuracy of the sensors this environmental dependency is minimized using the modeling and compensation techniques. In this work we have proposed a digital architecture for a programmable high precision computational unit which can be implemented in the FPGA or ASIC running the sensing algorithm of the sensors. This architecture can be used to implement polynomial compensation and it also supports reading and writing of the corresponding calibration coefficients even after the development of the sensors. Moreover, the architecture is platform independent. The architecture have been simulated for different FPGAs and ASIC and it has fulfilled the speed, accuracy and programmability requirements of the type of the sensors. The architecture has also been implemented and verified in a prototype of the barometric pressure sensor on Spartan-6 FPGA.
APA, Harvard, Vancouver, ISO, and other styles
7

Fan, G. Y., E. Beuville, P. Datte, J.-F. Beche, J. Millaud, M. H. Ellisman, and N.-H. Xuong. "Event-Driven 2D Detector for Digital Electron Imaging." Microscopy and Microanalysis 3, S2 (August 1997): 1089–90. http://dx.doi.org/10.1017/s1431927600012332.

Full text
Abstract:
An event-driven 2D pixel array detector designed for protein crystallography is being tested to determine its suitability as a direct electron detector for digital imaging in electron microscopy. The detector prototype consists of an 8×8 pixel array with an 150 μm pitch. The device configuration is illustrated in Fig. 1. The detector module consists of a reverse-biased 300 μm thick monolithic silicon diode array which is bump-bonded to an Application Specific Integrated Circuit (ASIC) which instruments each diode in the array. Each pixel cell of the ASIC forms a pixel processor which consists of an amplifier, discriminator, prescalar and readout circuit.When an incident electron enters the detector, a group of electron-hole pairs is created in the silicon. The detector bias of the diode array is such that holes are collected at the input to the amplifier where the signal is then amplified and shaped. When the output signal pulse height is greater than the discriminator threshold, the event is then registered in the prescalar, causing one count to be accumulated.
APA, Harvard, Vancouver, ISO, and other styles
8

Kalpana, G., Raja Krishnamoorthy, and P. T. Kalaivaani. "Design and implementation of low-power CMOS biosignal amplifier for active electrode in biomedical application using subthreshold biasing strategy." International Journal of Wavelets, Multiresolution and Information Processing 18, no. 01 (May 29, 2019): 1941017. http://dx.doi.org/10.1142/s0219691319410170.

Full text
Abstract:
Active Electrodes (AEs) are electrodes which have integrated bio-amplifier circuitry and are known to be less susceptible to motion artifacts and environmental interference. In this work, a low-power and high-input impedance amplifier for active electrode application is implemented based on subthreshold biasing strategies. In this proposed Application Specific Integrated Circuit (ASIC) device was versatile and numerical to achieve a high degree of programmability. It could be adapted to any other external part of one cochlear prosthesis, the sound analyzer that could be driven by a Digital Signal Processor (DSP). This research work also discusses the measurement of the electrode-skin impedance mismatch between two electrodes while concurrently measuring a bioelectrical signal without degradation of the performance of the amplifier, the efficient, noise-optimized analysis of bioelectrical signals utilizing two-wired active buffer electrodes. The reduction of power-line interference when using amplifying electrodes employing autonomous adaption of the gain of the subsequent differential amplification. The amplifier’s features include offset compensation, Common Mode Rejection Ratio (CMRR) improvement in software and a bandwidth extending down to DC. The proposed active electrode amplifier is designed using 90 nm CMOS technology. Simulation results exhibit up to the change in noise immunity and lessening in power utilization contrasted with the traditional bio-amplifier design at a similar delay.
APA, Harvard, Vancouver, ISO, and other styles
9

Sunny, Febin P., Ebadollah Taheri, Mahdi Nikdast, and Sudeep Pasricha. "A Survey on Silicon Photonics for Deep Learning." ACM Journal on Emerging Technologies in Computing Systems 17, no. 4 (June 30, 2021): 1–57. http://dx.doi.org/10.1145/3459009.

Full text
Abstract:
Deep learning has led to unprecedented successes in solving some very difficult problems in domains such as computer vision, natural language processing, and general pattern recognition. These achievements are the culmination of decades-long research into better training techniques and deeper neural network models, as well as improvements in hardware platforms that are used to train and execute the deep neural network models. Many application-specific integrated circuit (ASIC) hardware accelerators for deep learning have garnered interest in recent years due to their improved performance and energy-efficiency over conventional CPU and GPU architectures. However, these accelerators are constrained by fundamental bottlenecks due to (1) the slowdown in CMOS scaling, which has limited computational and performance-per-watt capabilities of emerging electronic processors; and (2) the use of metallic interconnects for data movement, which do not scale well and are a major cause of bandwidth, latency, and energy inefficiencies in almost every contemporary processor. Silicon photonics has emerged as a promising CMOS-compatible alternative to realize a new generation of deep learning accelerators that can use light for both communication and computation. This article surveys the landscape of silicon photonics to accelerate deep learning, with a coverage of developments across design abstractions in a bottom-up manner, to convey both the capabilities and limitations of the silicon photonics paradigm in the context of deep learning acceleration.
APA, Harvard, Vancouver, ISO, and other styles
10

Tulpule, Bhal, Bruce Ohme, Mark Larson, Al Behbahani, John Gerety, and Al Steines. "A System On Chip (SOC) ASIC chipset for Aerospace and Energy Exploration Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000278–84. http://dx.doi.org/10.4071/hitec-tha11.

Full text
Abstract:
This paper describes the design, key features and applications of a System On Chip (SOC) ASIC (Application Specific Integrated Circuit) chipset which was developed by Embedded Systems LLC as a part of the Smart Node based distributed control system architecture under an Air Force SBIR (Small Business Innovative Research) program {4}. The analog part of the SOC chipset has been implemented by Honeywell International under a subcontract using their high temperature SOI (Silicon On Insulator) Process. The complete chipset is expected to be available in early 2015. The key feature of the SOC chipset is that it is a reconfigurable and scalable building block that can be used to interface with most typical aerospace control system sensors and actuators. The SOC chipset captures all of the necessary functions required to power and interface with sensors such as RTD (Resistance Temperature Detectors), Strain Gauges (SG), Thermo Couples (TC) and transducers for measuring mass flow, speed, position or angle. The SOC chipset also contains all of the pre- and post-processing functions to convert electrical signals into digital words and send them on a data bus under the control of a host microprocessor. Finally, the SOC chipset contains PWM (Pulse Width Modulation) circuitry required to interface with external drives for actuators, motors, shutoff Valves etc. The SOC chipset can be powered from a Mil-Std-704F compliant power source or a conditioned DC power source. The chipset can be combined with other devices, such as memory, processor and A to D Converter to implement a high temperature capable Smart Node for localized management of sensors and actuators as a part of a distributed architecture or used as a scalable building block in a more complex function such as a FADEC (Full Authority Digital Engine Control). It is believed that the versatility of the SOC chipset makes it a well suited, affordable, scalable building block for not only aerospace controls but also for diverse applications such as down-hole drilling, energy exploration, wind farms etc. where high temperature electronics and /or high level of miniaturization is required.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "ASIC - Application Specific Integrated Circuit - Processor"

1

Le, Thai Q. (Thai Quoc) Carleton University Dissertation Engineering Electrical. "Application specific integrated circuit (ASIC) hardwired microcontroller." Ottawa, 1991.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

McArdle, Christopher. "The adoption of Application Specific Integrated Circuit (ASIC) technology by the UK manufacturing base." Thesis, Open University, 1997. http://oro.open.ac.uk/57704/.

Full text
Abstract:
Since the late 1970s, families of microelectronic technologies that could bring the advantages of high levels of electronic integration have been available at reasonable prices and manageable risk to all sectors of UK industry. However, the uptake of these technologies has been painfully slow, particularly by the small and medium enterprises (SMEs) that make up most of the companies currently operating in the UK. It is the aim of the research described here to assess how slow the uptake has been, the reasons for it, and possible solutions to the problem. The problem is investigated with reference to SMEs. In order to reach conclusions it has been necessary to:- • Define Application Specific Integrated Circuit (ASIC) technology and review its history • Review that nature of the UK SME base and identify why they should use ASICs • Review the UK, European and World ASIC markets • Analyse the nature of the UK ASIC design and supply industry • Ascertain the reasons for non-adoption and assess their validity • Relate the findings of this research to appropriate business, organisational and system models • Review past and existing technology-transfer programmes operating in the area of ASIC adoption at a UK, European and world level • Compare the adoption of ASIC technology with the adoption of similar, wide-ranging, new technologies The study concludes that the technology is unique in the wide range of industries to which it can be applied, and that although some advances in adoption have been made, there remains a significant number of hurdles to adoption which can best be addressed by government intervention and supporting activity from supply-companies, trade associations, user-groups and professional and educational institutions. Only once adoption has reached a 'critical mass' can it be assumed that a self-sustaining market will result.
APA, Harvard, Vancouver, ISO, and other styles
3

Radhakrishnan, Swarnalatha Computer Science &amp Engineering Faculty of Engineering UNSW. "Heterogeneous multi-pipeline application specific instruction-set processor design and implementation." Awarded by:University of New South Wales. Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/29161.

Full text
Abstract:
Embedded systems are becoming ubiquitous, primarily due to the fast evolution of digital electronic devices. The design of modern embedded systems requires systems to exhibit, high performance and reliability, yet have short design time and low cost. Application Specific Instruction set processors (ASIPs) are widely used in embedded system since they are economical to use, flexible, and reusable (thus saves design time). During the last decade research work on ASIPs have been carried out in mainly for single pipelined processors. Improving performance in processors is possible by exploring the available parallelism in the program. Designing of multiple parallel execution paths for parallel execution of the processor naturally incurs additional cost. The methodology presented in this dissertation has addressed the problem of improving performance in ASIPs, at minimal additional cost. The devised methodology explores the available parallelism of an application to generate a multi-pipeline heterogeneous ASIP. The processor design is application specific. No pre-defined IPs are used in the design. The generated processor contains multiple standalone pipelined data paths, which are not necessarily identical, and are connected by the necessary bypass paths and control signals. Control unit are separate for each pipeline (though with the same clock) resulting in a simple and cost effective design. By using separate instruction and data memories (Harvard architecture) and by allowing memory access by two separate pipes, the complexity of the controller and buses are reduced. The impact of higher memory latencies is nullified by utilizing parallel pipes during memory access. Efficient bypass network selection and encoding techniques provide a better implementation. The initial design approach with only two pipelines without bypass paths show speed improvements of up to 36% and switching activity reductions of up to 11%. The additional area costs around 16%. An improved design with different number of pipelines (more than two) based on applications show on average of 77% performance improvement with overheads of: 49% on area; 51% on leakage power; 17% on switching activity; and 69% on code size. The design was further trimmed, with bypass path selection and encoding techniques, which show a saving of up to 32% of area and 34% of leakage power with 6% performance improvement and 69% of code size reduction compared to the design approach without these techniques in the multi pipeline design.
APA, Harvard, Vancouver, ISO, and other styles
4

Cheung, Newton Computer Science &amp Engineering Faculty of Engineering UNSW. "Design automation methodologies for extensible processor platform." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2005. http://handle.unsw.edu.au/1959.4/26118.

Full text
Abstract:
This thesis addresses two ubiquitous trends in the embedded system world - the increasing importance of design turnaround time as a design metric, and the move towards closing the design productivity gap. Adopting the right choice of design approach has been recognised as an integral part of the design flow in order to meet desired characteristics such as increasing software content, satisfying the growing complexities of an application, reusing off-the-shelf components, and exploring design metrics tradeoff, which closes the design productivity gap. The importance of design turnaround time is motivated by the intensive competition between manufacturers, especially makers of mainstream electronic consumer products, who shrinks the product life cycle and requires faster time-to-market to maximise economic benefits. This thesis presents a suite of design automation methodologies to automatically design embedded systems for an application in the state-of-the-art design approach - the extensible processor platform. These design automation methodologies systematise the extensible processor platform???s design flow, with particular emphasis on solving four challenging design problems: i) code segment identification; ii) instruction generation; iii) architectural customisation selection; and iv) processor evaluation. Our suite of design automation methodologies includes: i) a semi-automatic design system - to design an extensible processor that maximises the application performance while satisfying the area constraint. By specifying a fitting function to identify suitable code segments within an application, a two-level hierarchy selection algorithm is used to first select a predefined processor and then select the right instruction, and a performance estimator is used to estimate an application's performance; ii) a tool to match instructions - to automatically match the pre-designed instructions with computationally intensive code segments, reducing verification time and effort; iii) an instructions estimation model - to estimate the area overhead, latency, power consumption of extensible instructions, exploring larger design space; and iv) an instructions generation tool - to generate new extensible instructions that maximises the speedup while minimising power dissipation. A number of techniques such as system decomposition, combinational equivalence checking and regression analysis etc., have been heavily relied upon in the creation of the final design system. This thesis shows results at every stage to demonstrate the efficacy of our design methodologies in the creation of extensible processors. The methodologies and results presented in this thesis demonstrate that automating the design process for an extensible processor platform results in significant performance increase - on average, an increase of 4.74x (up to 15.71x) compared to the original base processor. Our system achieves significant design turnaround time savings (2.5% of the full simulation time for the entire design space) with majority Pareto points obtained (91% on average), and can lead to fewer and faster design iterations. Our instruction matching tool is 7.3x faster on average compared to the best known approaches to the problem (partial simulations). Our estimation model has a mean absolute error as small as 3.4% (6.7% max.) for area overhead, 5.9% (9.4% max.) for latency, and 4.2% (7.2% max.) for power consumption, compared to estimation through the time consuming synthesis and simulation steps using commercial tools. Finally, the instruction generation tool reduces energy consumption by a further 5.8% on average (up to 17.7%) compared to extensible instructions generated by previous approaches.
APA, Harvard, Vancouver, ISO, and other styles
5

Tinguy, Pierre. "Etude et développement d’un oscillateur à quartz intégré." Thesis, Besançon, 2011. http://www.theses.fr/2011BESA2017/document.

Full text
Abstract:
Le besoin croissant de réduction du volume, de la masse et de la consommation des dispositifs électroniques sans pertes deperformances concerne aussi les oscillateurs à quartz utilisés dans les applications métrologiques (bases de temps, capteurs),la téléphonie, la navigation... Dans le cadre de cette problématique, nous avons développé un ASIC (Application SpecificIntegrated Circuit) en technologie 0,35 μm SiGe BiCMOS (Austriamicrosystems®) fonctionnant sous 3,3 V (±10%) pourréaliser un oscillateur à quartz miniature opérationnel sur une gamme en fréquence allant de 10 MHz à 100 MHz. Ce circuitdont la surface ne dépasse pas les 4 mm2 est composé de diverses cellules RF, depuis le système d’entretien de type Colpitts,la mise en forme et jusqu’à l’adaptation du signal à sa charge d’utilisation (50 W ou HCMOS). Ces cellules sont toutespolarisées par une référence de tension interne de type bandgap CMOS. La consommation totale du circuit en charge resteinférieure à 100 mW pour un bruit blanc de phase visé de −150 dBc/Hz à 40 MHz. Pour minimiser la sensibilité thermiquedu résonateur et ainsi pouvoir s’orienter également vers des applications OCXO (Oven Controlled Crystal Oscillator),nous avons partiellement intégré une régulation de température dans notre ASIC. Cette régulation fortement dépendante del’architecture thermo-mécanique a été dimensionnée puis validée au travers de modélisations par analogie sous Spectre®.Notre électronique intégrée nécessite peu de composants externes et nous l’avons reportée par flip chip sur une interfacespécifique pour
The increasing demand for high-performance devices featuring compact, lighter-weight designs with low-power consumptionalso impacts quartz crystal oscillators used in metrological applications (time bases, sensors), telephony or navigation. Inthis context, we have developed an ASIC (Application Specific Integrated Circuit) in 0.35 μm SiGe BiCMOS technology(Austriamicrosystems®) supplied by 3.3 V (±10%) to realize a miniaturized quartz crystal oscillator operating in the 10 MHzto 100 MHz frequency range. The fabricated die hosts several RF cells in a 4 mm2 area, including a sustaining amplifier(Colpitts topology), a signal shaping circuit and an output buffer dedicated to a specific load (50 W or HCMOS). These cellsare biased by a fully integrated CMOS bandgap voltage reference. The die power consumption remains lower than 100 mWfor a targeted phase noise floor as low as −150 dBc/Hz at a 40 MHz carrier frequency. A thermal control loop has in additionbeen partially integrated to the ASIC, in order to reduce the quartz resonator thermal sensitivity as well as to extend thepotential application field of the developed die to oven applications (OCXO). The thermal control, that is strongly dependanton the mechanical design, has been designed and tested by using electrical analogy modeling on Spectre® simulator. Finallyour integrated circuit has been connected to a specific substrate using flip chip technology to realize a miniaturized quartzcrystal oscillator packaged on a TO-8 enclosure (Ø15.2 mm)
APA, Harvard, Vancouver, ISO, and other styles
6

Li, Bo. "Conception et test de cellules de gestion d'énergie à commande numérique en technologies CMOS avancées." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00782429.

Full text
Abstract:
Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de découpage élevée sur FPGA et ASIC. Cette thèse vise à proposer des contrôleurs numériques des performances élevées, de faible consommation énergétique et qui peuvent être implémentés facilement. En plus des contrôleurs numériques existants comme PID, RST, tri-mode et par mode de glissement, un nouveau contrôleur numérique (DDP) pour le convertisseur abaisseur de tension est proposé sur le principe de la commande prédictive: il introduit une nouvelle variable de contrôle qui est la position de la largeur d'impulsion permettant de contrôler de façon simultanée le courant dans l'inductance et la tension de sortie. La solution permet une dynamique très rapide en transitoire, aussi bien pour la variation de la charge que pour les changements de tension de référence. Les résultats expérimentaux sur FPGA vérifient les performances de ce contrôleur jusqu'à la fréquence de découpage de 4MHz. Un contrôleur numérique nécessite une modulation numérique de largeur d'impulsion (DPWM). L'approche Sigma-Delta de la DPWM est un bon candidat en ce qui concerne le compromis entre la complexité et les performances. Un guide de conception d'étage Sigma-Delta pour le DPWM est présenté. Une architecture améliorée de traditionnelles 1-1 MASH Sigma-Delta DPWM est synthétisée sans détérioration de la stabilité en boucle fermée ainsi qu'en préservant un coût raisonnable en ressources matérielles. Les résultats expérimentaux sur FPGA vérifient les performances des DPWM proposées en régimes stationnaire et transitoire. Deux ASICs sont portés en CMOS 0,35µm: le contrôleur en tri-mode pour le convertisseur abaisseur de tension et la commande par mode de glissement pour les convertisseurs abaisseur et élévateur de tension. Les bancs de test sont conçus pour conduire à un modèle d'évaluation de consommation énergétique. Pour le contrôleur en tri-mode, la consommation de puissance mesurée est seulement de 24,56mW/MHz lorsque le ratio de temps en régime de repos (stand-by) est 0,7. Les consommations de puissance de command par mode de glissement pour les convertisseurs abaisseur et élévateur de tension sont respectivement de 4,46mW/MHz et 4,79mW/MHz. En utilisant le modèle de puissance, une consommation de la puissance estimée inférieure à 1mW/MHz est envisageable dans des technologies CMOS plus avancées. Comparé aux contrôlés homologues analogiques de l'état de l'art, les prototypes ASICs illustrent la possibilité d'atteindre un rendement comparable pour les applications de faible et de moyen puissance mais avec l'avantage d'une meilleure précision et une meilleure flexibilité.
APA, Harvard, Vancouver, ISO, and other styles
7

Zhou, Yang. "Development of a CMOS pixel sensor for embedded space dosimeter with low weight and minimal power dissipation." Thesis, Strasbourg, 2014. http://www.theses.fr/2014STRAE021/document.

Full text
Abstract:
Cette thèse porte sur le développement d'un capteur de pixel monolithique CMOS utilisé pourl’identification et le comptage des particules ionisés dan l’espace avec un flux élevé. Un nouveauconcept pour l’identification de l’espèce des particules proposé dans la présente étude, est basésur l'analyse des amas de particules déclenchés. Pour valider ce nouveau concept, un capteur detaille complet, qui comprend la matrice de pixel sensible aux particules ionisés signal, une chaînede traitement du signal analogique, un convertisseur analogue numérique de 3 bits, et untraitement du signal numérique a été conçu dans un processus de 0.35 μm. Le capteur sortiedirectement des informations de flux à travers 4 canaux avec un débit de données très faible(80 bps) et dissipation d’énergie minimale (~ 100 mW). Chaque canal représente particules avecdifférentes espèces et les énergies. La densité maximum de flux mesurable est jusqu'à 108particules/cm2/s (coups s'accumulent < 5%). Un prototype à échelle réduite a été fabriqué et testéavec trois types d'illumination de rayonnement (rayons X, les électrons et laser infrarouge). Tousles résultats obtenus valident le nouveau concept proposé. Un moniteur de rayonnement spatialtrès miniaturisé basé sur un capteur de pixel CMOS peut être prévu. Le moniteur peut présente lesmêmes performances que les compteurs actuels, mais avec une dissipation de puissance réduited'un ordre de grandeur qu'un poids, un volume d'encombrement et un coût moindre. En outre, enraison de ses sorties de haut niveau et faible débit de données, aucune traitement supplémentairedu signal dehors du capteur est nécessaire, ce qui le rend particulièrement attrayant pour desapplications dan les petits satellitaires
This thesis focuses on the development of a CMOS monolithic pixel sensor used for space ionizingparticles identification and counting in high flux. A new concept for single particle identification isproposed in this study, which is based on the analysis of particle triggered clusters. To validate thisnew concept, a full size sensor including the sensitive pixel matrix, an analogue signal processingchain, a 3-bit analogue to digital converter, and a digital processing stage was designed in a 0.35μm process. The sensor directly output particles flux information through 4 channels with a verylow data rate (80 bps) and minimal power dissipation (~ 100mW). Each channel representsparticles with different species and energies. The highest measurable flux density is up to 108particles/cm2/s (hits pile up < 5%). A reduced scale prototype was fabricated and tested with 3types of radiation illumination (X-ray, electrons and infrared laser). All the results obtained validatethe proposed new concept and a highly miniaturized space radiation monitor based on a singleCMOS pixel sensor could be foreseen. The monitor could provide measurements of comparable orbetter quality than existing instruments, but at around an order of magnitude lower powerconsumption, mass and volume and a lower unit cost. Moreover, due to its high level and low datarate outputs, no signal treatment power aside the sensor is required which makes it especiallyattractive for small satellite application
APA, Harvard, Vancouver, ISO, and other styles
8

Gunawardena, Sanjeev. "Feasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays." Ohio University / OhioLINK, 2000. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1171990779.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Tinguy, Pierre. "Etude et développement d'un oscillateur à quartz intégré." Phd thesis, Université de Franche-Comté, 2011. http://tel.archives-ouvertes.fr/tel-00675277.

Full text
Abstract:
Le besoin croissant de réduction du volume, de la masse et de la consommation des dispositifs électroniques sans pertes deperformances concerne aussi les oscillateurs à quartz utilisés dans les applications métrologiques (bases de temps, capteurs),la téléphonie, la navigation... Dans le cadre de cette problématique, nous avons développé un ASIC (Application SpecificIntegrated Circuit) en technologie 0,35 μm SiGe BiCMOS (Austriamicrosystems®) fonctionnant sous 3,3 V (±10%) pourréaliser un oscillateur à quartz miniature opérationnel sur une gamme en fréquence allant de 10 MHz à 100 MHz. Ce circuitdont la surface ne dépasse pas les 4 mm2 est composé de diverses cellules RF, depuis le système d'entretien de type Colpitts,la mise en forme et jusqu'à l'adaptation du signal à sa charge d'utilisation (50 W ou HCMOS). Ces cellules sont toutespolarisées par une référence de tension interne de type bandgap CMOS. La consommation totale du circuit en charge resteinférieure à 100 mW pour un bruit blanc de phase visé de −150 dBc/Hz à 40 MHz. Pour minimiser la sensibilité thermiquedu résonateur et ainsi pouvoir s'orienter également vers des applications OCXO (Oven Controlled Crystal Oscillator),nous avons partiellement intégré une régulation de température dans notre ASIC. Cette régulation fortement dépendante del'architecture thermo-mécanique a été dimensionnée puis validée au travers de modélisations par analogie sous Spectre®.Notre électronique intégrée nécessite peu de composants externes et nous l'avons reportée par flip chip sur une interfacespécifique pour
APA, Harvard, Vancouver, ISO, and other styles
10

Chadha, Vishal. "Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "ASIC - Application Specific Integrated Circuit - Processor"

1

Romdhane, Mohamed S. Ben. Quick-turnaround ASIC design in VHDL: Core-based behavioral synthesis. Boston: Kluwer Academic Publishers, 1996.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

European Design and Test Conference (1994 Paris, France). The European Design and Test Conference: Proceedings : EDAC, The European Conference on Design Automation : ETC, European Test Conference : EUROASIC, The European Event in ASIC Design : February 28-March 3, 1994, Paris, France. Los Alamitos, Calif: IEEE Computer Society Press, 1994.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Application Specific Integrated Circuit (ASIC) Technology. Elsevier, 1991. http://dx.doi.org/10.1016/b978-0-122-34123-6.x5001-x.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

G, Einspruch Norman, and Hilbert Jeffrey L, eds. Application specific integrated circuit (ASIC) technology. London: Academic Press Inc., 1991.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

IEEE Computer Society. Design Automation Standards Committee., Institute of Electrical and Electronics Engineers., and IEEE Standards Board, eds. IEEE standard for VITAL Application-Specific Integrated Circuit (ASIC) modeling specification. New York, N.Y., USA: Institute of Electrical and Electronics Engineers, 1996.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

IEEE Computer Society. Design Automation Standards Subcommittee., Institute of Electrical and Electronics Engineers., and IEEE Standards Board, eds. IEEE standard for VITAL ASIC (Application Specific Integrated Circuit) modeling specification. New York: Institute of Electrical and Electronics Engineers, 2001.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

G, Einspruch Norman, and Hilbert Jeffrey L, eds. Application specific integrated circuit (ASIC) technology: Edited by Norman G. Einspruch, Jeffrey L. Hilbert. San Diego: Academic Press, 1991.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

A Low Power Application-Specific Integrated Circuit (ASIC) implementation of Wavelet Transform/Inverse Transform. Storming Media, 2001.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Wiangtong, Theerayod. Application-specific integrated circuit (ASIC) design for the "Hodgart-Massey" coherent MSK demodulator/decoder. 1996.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis (The International Series in Engineering and Computer Science). Springer, 1996.

Find full text
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "ASIC - Application Specific Integrated Circuit - Processor"

1

Wicaksana, Arya, Dareen Kusuma Halim, Dicky Hartono, Felix Lokananta, Sze-Wei Lee, Mow-Song Ng, and Chong-Ming Tang. "Case Study: First-Time Success ASIC Design Methodology Applied to a Multi-Processor System-on-Chip." In Application Specific Integrated Circuits - Technologies, Digital Systems and Design Methodologies. IntechOpen, 2019. http://dx.doi.org/10.5772/intechopen.79855.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Vestias, Mário Pereira. "High-Performance Reconfigurable Computing." In Encyclopedia of Information Science and Technology, Fourth Edition, 4018–29. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-2255-3.ch348.

Full text
Abstract:
High-Performance Reconfigurable Computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to General-Purpose Processors. Better performance and lower power consumption could be achieved using Application Specific Integrated Circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter we will provide a description of reconfigurable hardware for high performance computing.
APA, Harvard, Vancouver, ISO, and other styles
3

Vestias, Mário Pereira. "High-Performance Reconfigurable Computing." In Advances in Computer and Electrical Engineering, 731–44. IGI Global, 2019. http://dx.doi.org/10.4018/978-1-5225-7598-6.ch053.

Full text
Abstract:
High-performance reconfigurable computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to general-purpose processors. Better performance and lower power consumption could be achieved using application-specific integrated circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter, the authors provide a description of reconfigurable hardware for high-performance computing.
APA, Harvard, Vancouver, ISO, and other styles
4

MONTALBO, JOSEPH. "ASIC Manufacturing." In Application Specific Integrated Circuit (ASIC) Technology, 185–219. Elsevier, 1991. http://dx.doi.org/10.1016/b978-0-12-234123-6.50012-3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

HILBERT, JEFFREY L. "Introduction to ASIC Technology." In Application Specific Integrated Circuit (ASIC) Technology, 1–6. Elsevier, 1991. http://dx.doi.org/10.1016/b978-0-12-234123-6.50006-8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

COLLETT, RONALD. "Market Dynamics of the ASIC Revolution." In Application Specific Integrated Circuit (ASIC) Technology, 7–25. Elsevier, 1991. http://dx.doi.org/10.1016/b978-0-12-234123-6.50007-x.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

HICKMAN, PAT, BOB HALL, FRANK REID, and DOUG SCHUCKER. "Design and Architecture of ASIC Products." In Application Specific Integrated Circuit (ASIC) Technology, 59–105. Elsevier, 1991. http://dx.doi.org/10.1016/b978-0-12-234123-6.50009-3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

MITCHELL, G. THOMAS. "Application and Selection of ASICs." In Application Specific Integrated Circuit (ASIC) Technology, 275–97. Elsevier, 1991. http://dx.doi.org/10.1016/b978-0-12-234123-6.50015-9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

EINSPRUCH, NORMAN G., and JEFFREY L. HILBERT. "Preface." In Application Specific Integrated Circuit (ASIC) Technology, xi. Elsevier, 1991. http://dx.doi.org/10.1016/b978-0-12-234123-6.50005-6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

CHAKRAVARTY, DEV. "Marketing ASICs." In Application Specific Integrated Circuit (ASIC) Technology, 27–57. Elsevier, 1991. http://dx.doi.org/10.1016/b978-0-12-234123-6.50008-1.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "ASIC - Application Specific Integrated Circuit - Processor"

1

Ned, Alex A., Wolf S. Landmann, Andrew Bemis, and David S. Kerr. "Amplified Pressure Transducers Using SOI Sensors and SOI Electronics, Suitable for High Temperature Operation (250°C)." In ASME 2011 Turbo Expo: Turbine Technical Conference and Exposition. ASMEDC, 2011. http://dx.doi.org/10.1115/gt2011-45704.

Full text
Abstract:
In an effort to improve efficiency, reliability and reduce costs, engineers are moving towards distributed control systems on trains, cars, planes and other systems in place of centralized control systems. In a distributed control system, sensors, processors and actuators are all located together at remote locations [1]. Distributed control systems require significantly less cabling which leads to weight reductions and therefore cost and energy savings. To implement distributed control, in many applications sensors and their electronics must be able to withstand higher temperatures. Kulite Semiconductor Products has therefore developed a high temperature amplifier to be coupled with high temperature pressure sensors. While the suitable sensing technologies have been under the development for some time, the development of an Application Specific Integrated circuit (ASIC) utilizing SOI technology is now introduced and optimized. This paper reports on the latest developments of the Silicon-On-Insulator (SOI) piezoresistive sensors, the SOI application specific integrated circuits (ASICs) and the high temperature packaging of the two together. The design of the latest miniature amplified-pressure transducers capable of operating reliably under extreme environmental conditions (in excess of 250°C and under accelerations of greater than 200g) is described in detail. The performance of such amplified pressure transducers is presented and indicates that ruggedized, piezoresistive transducers with excellent static and dynamic performance characteristics are capable of operation in extremely harsh, high temperature environments.
APA, Harvard, Vancouver, ISO, and other styles
2

Mori, Hiroyuki, Sayuri Kohara, Keishi Okamoto, Hirokazu Noma, and Kazushige Toriyama. "Effects of Low CTE Materials on Thermal Deformation of Organic Substrates in Flip Chip Package Application." In ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels. American Society of Mechanical Engineers, 2015. http://dx.doi.org/10.1115/ipack2015-48741.

Full text
Abstract:
Coefficient of thermal expansion (CTE) characteristic of organic materials for substrates in flip chip package application demanded by semiconductor package requirements is becoming lower than ever. In general, height restrictions are imposed on package-on-package (PoP) devices in mobile applications. One should hence establish a tight budget on the height variation in manufacturing of the devices. Given such background, a lowering of the CTE characteristic of package substrates is an attractive solution for reducing package deformation upon manufacturing, since it contributes to minimize CTE mismatch of the substrates with silicon chips. In large-die flip chip applications such as high-end processors, a lower CTE substrate can mitigate mechanical stress not only on low-k layers in back end of the line (BEOL) underneath the chip bumps, but also on underfill layers during thermal cycling. Therefore an introduction of lower CTE materials in organic substrates is becoming essential for future applications of electronic devices. In this paper, thermal deformation behaviors of organic substrates associated with lowering of the CTEs of their constituent materials are analyzed by finite element analysis (FEA). The analyses are done on a 3-2-3 build-up layer structure substrate in order to focus onto typical application specific integrated circuit (ASIC) products. A finite element model for a test substrate is constructed by a method in which the substrate is divided into sections according to its circuitry patterns so that the lateral inhomogeneity of mechanical property is taken into account. The finite element analyses using the model showed that the package warpage decreases with lowering of the effective CTE of the substrate, but the warpage of the substrate itself increases and its surface profile changes from a concave shape to a convex shape. The analysis result of substrate warpage variation with the build-up material’s CTE showed that the selection of build-up materials with appropriate material properties can contribute to reduce the substrate warpage. The analysis also showed that the adverse impact to the substrate’s CTE reduction by such material selection is limited.
APA, Harvard, Vancouver, ISO, and other styles
3

Liou, Jian-Chiun, Wen-Chieh Lin, Yun-Yao Kong, Yuan-Cheng Song, and Kuan-Wen Fang. "Medical ultrasound system with an application-specific integrated circuit(ASIC)." In 2017 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW). IEEE, 2017. http://dx.doi.org/10.1109/icce-china.2017.7991039.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Lebedev, Sergey, Alexey Timofeev, Sergey Sinutin, and Anatoly Grigoriev. "Development Application-Specific Integrated Circuit (ASIC) for Intelligent Vibration Sensor." In 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus). IEEE, 2020. http://dx.doi.org/10.1109/eiconrus49466.2020.9039520.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Covas, Marie, Jean-Noel Contensou, and Thierry M. Bosch. "PulCar: an application-specific integrated circuit (ASIC) for an optoelectronic sensor." In International Symposium on Biomedical Optics Europe '94, edited by Anna M. Verga Scheggi, Francesco Baldini, Pierre R. Coulet, and Otto S. Wolfbeis. SPIE, 1995. http://dx.doi.org/10.1117/12.201245.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Fischer, Helmut, Tarek Lule, Bernd Schneider, Juergen Schulte, and Markus Boehm. "Analog image detector in thin film on application-specific integrated circuit (ASIC) technology." In Optics for Productivity in Manufacturing, edited by Markus Becker, R. W. Daniel, and Otmar Loffeld. SPIE, 1994. http://dx.doi.org/10.1117/12.193939.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Joshi, Atul B., Sachin Kashyap, and Vajayeendra Rao. "Application specific integrated circuit (ASIC) with low power digitizer (ADC) for space imaging applications." In Sensors and Systems for Space Applications XIV, edited by Khanh D. Pham and Genshe Chen. SPIE, 2021. http://dx.doi.org/10.1117/12.2588195.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Cruz, Febus Reidj G., Clarissa M. Magsipoc, Francez Eunika B. Alinea, Marvin Edrian P. Baronia, Mohammad M. Jumahadi, Ramon G. Garcia, and Wen-Yaw Chung. "Application specific integrated circuit (ASIC) for Ion Sensitive Field Effect Transistor (ISFET) L-Asparagine biosensor." In TENCON 2016 - 2016 IEEE Region 10 Conference. IEEE, 2016. http://dx.doi.org/10.1109/tencon.2016.7848529.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Tuan, Min-Chun, Shih-Lun Chen, Yu-Kuen Lai, Chun-Chieh Chen, and Ho-Yin Lee. "A 3-wire SPI Protocol Chip Design with Application-Specific Integrated Circuit (ASIC) and FPGA Verification." In The 3rd World Congress on Electrical Engineering and Computer Systems and Science. Avestia Publishing, 2017. http://dx.doi.org/10.11159/eee17.110.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Wei Li, Xiaoyang Zeng, Longmei Nan, Tao Chen, and Zibin Dai. "A high-flexibility and energy-efficient application-specific cryptography VLIW processor for symmetric cipher algorithms." In 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2016. http://dx.doi.org/10.1109/icsict.2016.7998715.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Reports on the topic "ASIC - Application Specific Integrated Circuit - Processor"

1

Nuckolls, L. CMOS ASIC (application specific integrated circuit). Office of Scientific and Technical Information (OSTI), July 1989. http://dx.doi.org/10.2172/5551185.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Brockman, Jay, Peter Kogge, Michael Niemier, and Larry Pileggi. Memory-Based Structured Application Specific Integrated Circuit (ASIC) Study. Fort Belvoir, VA: Defense Technical Information Center, October 2008. http://dx.doi.org/10.21236/ada499474.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Simpson, R. L., and B. T. Meyer. Characteristics and development report for the SA3871 Intent Controller application specific integrated circuit (ASIC). Office of Scientific and Technical Information (OSTI), August 1995. http://dx.doi.org/10.2172/110167.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'ASIC - Application Specific Integrated Circuit - Processor' for particular source types:
Journal articles Dissertations / Theses
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography