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FIJALKOWSKI, BOGDAN T., and JAN W. KROSNICKI. "CONCEPTS OF ELECTRONICALLY-CONTROLLED ELECTROMECHANICAL/MECHANOELECTRICAL STEER-, AUTODRIVE- AND AUTOABSORBABLE WHEELS FOR ENVIRONMENTALLY-FRIENDLY TRI-MODE SUPERCARS." Journal of Circuits, Systems and Computers 04, no. 04 (December 1994): 501–16. http://dx.doi.org/10.1142/s0218126694000296.
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Concepts of the electronically-controlled electromechanical/mechanoelectrical Steer-, Autodrive- and Autoabsorbable Wheels (SA2W) with their brushless Alternating Current-to-Alternating Current (AC-AC), Alternating Current-to-Direct Current-Alternating Current (AC-DC-AC) and/or Direct Current-to-Alternating Current (DC-AC)/Alternating Current-to-Direct Current (AC-DC) macroelectronic converter commutator (macro-commutator) wheel-hub motors/generators with the Application Specific Integrated Matrixer (ASIM) macroelectronic converter commutators (ASIM macrocommutators) and Application Specific Integrated Circuit (ASIC) microelectronic Neuro-Fuzzy (NF) computer (processor) controllers (ASIC NF microcontrollers) for environmentally-friendly tri-mode supercars (advanced ultralight hybrids) have been conceived by the first author and designed by both authors with the Cracow University of Technology’s Automotive Mechatronics Research and Development (R&D) Team. These electromechanical/mechanoelectrical wheel-hub motors/generators, respectively, for instance, can be composed of the outer rotor with the Interior Permanent Magnet (IPM) poles and the inner stator that has the three-phase armature winding. The macroelectronic converter commutator establishes the AC-AC cycloconverter, AC-DC rectifier-DC-AC inverter and/or DC-AC inverter/AC-DC rectifier ASIM macrocommutator. The microelectronic NF computer (processor) controller establishes the ASIC microcomputer-based NF microcontroller. By adopting continuous semiconductor bipolar electrical valves in the high-power ASIM, it has been able to increase the commutation (switching) frequency and reduce harmonic losses of the electromechanical/mechanoelectrical wheel-hub motors/generators, respectively.
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Lee, Jae-Eun, Ji-Won Kang, Woo-Suk Kim, Jin-Kyum Kim, Young-Ho Seo, and Dong-Wook Kim. "Digital Image Watermarking Processor Based on Deep Learning." Electronics 10, no. 10 (May 15, 2021): 1183. http://dx.doi.org/10.3390/electronics10101183.
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Much research and development have been made to implement deep neural networks for various purposes with hardware. We implement the deep learning algorithm with a dedicated processor. Watermarking technology for ultra-high resolution digital images and videos needs to be implemented in hardware for real-time or high-speed operation. We propose an optimization methodology to implement a deep learning-based watermarking algorithm in hardware. The proposed optimization methodology includes algorithm and memory optimization. Next, we analyze a fixed-point number system suitable for implementing neural networks as hardware for watermarking. Using these, a hardware structure of a dedicated processor for watermarking based on deep learning technology is proposed and implemented as an application-specific integrated circuit (ASIC).
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Majerus, Steve J. A., Daniel T. Goff, and Walter Merrill. "A 200 °C Motor Control ASIC." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000159–64. http://dx.doi.org/10.4071/hitec-wa15.
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A custom application-specific integrated circuit (ASIC) has been designed for positional control of brushless DC or servo motors in high-temperature (>200 °C) environments. Applications would include valve and position control for aerospace and industrial systems. Patented high-temperature circuit design techniques facilitate hightemperature operation from a conventional, low-cost, 0.5-micron bulk CMOS foundry process. The ASIC is highly integrated to enable software- and processor-free local control of motor position, and uses external power MOSFETs for motor commutation. Motor position can be controlled in open- or closed-loop modes with an integrated rotational variable displacement transformer (RVDT) direct digital synthesis (DDS) waveform generator, rail-to-rail op-amp driver and demodulation circuit. The ASIC can accept both analog (0–10 V) or digital (SPI bus) position setpoint commands from an external controller. Motor position is indicated by both analog and digital output signals. The full-scale displacement of the controlled motor is programmable from 5 to 8 bits of resolution, permitting 32–256 positions of control. Safety features such as a 500-ms power-on delay, overtemperature and motor overcurrent detection, and control signal undervoltage lockout were included to minimize the need for external control. ASIC bench-test results confirmed circuit functionality at ambient temperatures up to 225 °C using room-temperature power MOSFETs and motor load. ASIC performance at the 8-bit level was demonstrated, although the clock oscillator frequency shifted by about 15% over the full temperature range. Control of the motor at 200 °C was also demonstrated, although moderate loss of motor holding torque was observed due to internal heat generation in the motor. The ASIC was combined with commercially-available off-the-shelf high-temperature components on a printed wiring board (PWB) to form a compact (4 × 3.5 inch) motor control demonstration system capable of prolonged operation at temperatures beyond 200 °C. Environmental and long-term testing of the PWB is planned to demonstrate system reliability.
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Gao, Zhenyi, Bin Zhou, Yang Li, Lei Yang, Xiang Li, Qi Wei, Hongyang Chu, and Rong Zhang. "Design and Implementation of an On-Chip Low-Power and High-Flexibility System for Data Acquisition and Processing of an Inertial Measurement Unit." Sensors 20, no. 2 (January 14, 2020): 462. http://dx.doi.org/10.3390/s20020462.
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For signal processing of a Micro-Electro-Mechanical System (MEMS) Inertial Measurement Unit (IMU), a digital-analog hybrid system-on-chip (SoC) with small area and low power consumption was designed and implemented in this paper. To increase the flexibility of the processing circuit, the designed SoC integrates a low-power processor and supports three startup or debugging modes for different application scenarios. An application-specific computing module and communication interface are designed in the circuit to meet the requirements of IMU signal processing. The configurable clock allows users to dynamically balance computing speed and power consumption in their applications. The chip was taped out under SMIC 180 nm CMOS technology and tested for performance. The results show that the chip’s maximum running frequency is 105 MHz. The total area is 33.94 mm 2 . The dynamic and static power consumption are 0.65 mW/MHz and 0.30 mW/MHz, respectively. When the system clock is 25 MHz, the dynamic and static power consumption of the chip is 76 mW and 66 mW, and the dynamic and static power consumption of the FPGA level are 634 mW and 520 mW. The results verify the superiority of the application specific integrated circuit (ASIC) solution in terms of integration and low power consumption.
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Ibrahim, Atef, and Fayez Gebali. "Word-Based Systolic Processor for Field Multiplication and Squaring Suitable for Cryptographic Processors in Resource-Constrained IoT Systems." Electronics 10, no. 15 (July 25, 2021): 1777. http://dx.doi.org/10.3390/electronics10151777.
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Internet of things (IoT) technology provides practical solutions for a wide range of applications, including but not limited to, smart homes, smart cities, intelligent grid, intelligent transportation, and healthcare. Security and privacy issues in IoT are considered significant challenges that prohibit its utilization in most of these applications, especially relative to healthcare applications. Cryptographic protocols should be applied at the different layers of IoT framework, especially edge devices, to solve all security concerns. Finite-field arithmetic, particularly field multiplication and squaring, represents the core of most cryptographic protocols and their implementation primarily affects protocol performance. In this paper, we present a compact and combined two-dimensional word-based serial-in/serial-out systolic processor for field multiplication and squaring over GF(2m). The proposed structure features design flexibility to manage hardware utilization, execution time, and consumed energy. Application Specific Integrated Circuit (ASIC) Implementation results of the proposed word-serial design and the competitive ones at different embedded word-sizes show that the proposed structure realizes considerable saving in the area and consumed energy, up to 93.7% and 98.2%, respectively. The obtained results enable the implementation of restricted cryptographic primitives in resource-constrained IoT edge devices such as wearable and implantable medical devices, smart cards, and wireless sensor nodes.
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Sajjad, Muhammad, Mohd Zuki Yusoff, and Muhammad Ahmed. "A Customized Floating-point Processor Design for FPGA and ASIC based Thermal Compensation in High-precision Sensing." Annals of Emerging Technologies in Computing 5, no. 1 (January 1, 2021): 40–50. http://dx.doi.org/10.33166/aetic.2021.01.004.
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There are many types of sensors which require large dynamic range as well as high accuracy at the same time. Barometric altimeter is an example of such sensors. The signal processing techniques in the sensors are normally implemented using Field Programmable Gate Arrays (FPGAs) or Application-Specific Integrated Circuits (ASICs). The sensing variable in such type of the sensors is unwantedly environment dependent. So, for ensuring accuracy of the sensors this environmental dependency is minimized using the modeling and compensation techniques. In this work we have proposed a digital architecture for a programmable high precision computational unit which can be implemented in the FPGA or ASIC running the sensing algorithm of the sensors. This architecture can be used to implement polynomial compensation and it also supports reading and writing of the corresponding calibration coefficients even after the development of the sensors. Moreover, the architecture is platform independent. The architecture have been simulated for different FPGAs and ASIC and it has fulfilled the speed, accuracy and programmability requirements of the type of the sensors. The architecture has also been implemented and verified in a prototype of the barometric pressure sensor on Spartan-6 FPGA.
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Fan, G. Y., E. Beuville, P. Datte, J.-F. Beche, J. Millaud, M. H. Ellisman, and N.-H. Xuong. "Event-Driven 2D Detector for Digital Electron Imaging." Microscopy and Microanalysis 3, S2 (August 1997): 1089–90. http://dx.doi.org/10.1017/s1431927600012332.
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An event-driven 2D pixel array detector designed for protein crystallography is being tested to determine its suitability as a direct electron detector for digital imaging in electron microscopy. The detector prototype consists of an 8×8 pixel array with an 150 μm pitch. The device configuration is illustrated in Fig. 1. The detector module consists of a reverse-biased 300 μm thick monolithic silicon diode array which is bump-bonded to an Application Specific Integrated Circuit (ASIC) which instruments each diode in the array. Each pixel cell of the ASIC forms a pixel processor which consists of an amplifier, discriminator, prescalar and readout circuit.When an incident electron enters the detector, a group of electron-hole pairs is created in the silicon. The detector bias of the diode array is such that holes are collected at the input to the amplifier where the signal is then amplified and shaped. When the output signal pulse height is greater than the discriminator threshold, the event is then registered in the prescalar, causing one count to be accumulated.
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Kalpana, G., Raja Krishnamoorthy, and P. T. Kalaivaani. "Design and implementation of low-power CMOS biosignal amplifier for active electrode in biomedical application using subthreshold biasing strategy." International Journal of Wavelets, Multiresolution and Information Processing 18, no. 01 (May 29, 2019): 1941017. http://dx.doi.org/10.1142/s0219691319410170.
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Active Electrodes (AEs) are electrodes which have integrated bio-amplifier circuitry and are known to be less susceptible to motion artifacts and environmental interference. In this work, a low-power and high-input impedance amplifier for active electrode application is implemented based on subthreshold biasing strategies. In this proposed Application Specific Integrated Circuit (ASIC) device was versatile and numerical to achieve a high degree of programmability. It could be adapted to any other external part of one cochlear prosthesis, the sound analyzer that could be driven by a Digital Signal Processor (DSP). This research work also discusses the measurement of the electrode-skin impedance mismatch between two electrodes while concurrently measuring a bioelectrical signal without degradation of the performance of the amplifier, the efficient, noise-optimized analysis of bioelectrical signals utilizing two-wired active buffer electrodes. The reduction of power-line interference when using amplifying electrodes employing autonomous adaption of the gain of the subsequent differential amplification. The amplifier’s features include offset compensation, Common Mode Rejection Ratio (CMRR) improvement in software and a bandwidth extending down to DC. The proposed active electrode amplifier is designed using 90 nm CMOS technology. Simulation results exhibit up to the change in noise immunity and lessening in power utilization contrasted with the traditional bio-amplifier design at a similar delay.
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Sunny, Febin P., Ebadollah Taheri, Mahdi Nikdast, and Sudeep Pasricha. "A Survey on Silicon Photonics for Deep Learning." ACM Journal on Emerging Technologies in Computing Systems 17, no. 4 (June 30, 2021): 1–57. http://dx.doi.org/10.1145/3459009.
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Deep learning has led to unprecedented successes in solving some very difficult problems in domains such as computer vision, natural language processing, and general pattern recognition. These achievements are the culmination of decades-long research into better training techniques and deeper neural network models, as well as improvements in hardware platforms that are used to train and execute the deep neural network models. Many application-specific integrated circuit (ASIC) hardware accelerators for deep learning have garnered interest in recent years due to their improved performance and energy-efficiency over conventional CPU and GPU architectures. However, these accelerators are constrained by fundamental bottlenecks due to (1) the slowdown in CMOS scaling, which has limited computational and performance-per-watt capabilities of emerging electronic processors; and (2) the use of metallic interconnects for data movement, which do not scale well and are a major cause of bandwidth, latency, and energy inefficiencies in almost every contemporary processor. Silicon photonics has emerged as a promising CMOS-compatible alternative to realize a new generation of deep learning accelerators that can use light for both communication and computation. This article surveys the landscape of silicon photonics to accelerate deep learning, with a coverage of developments across design abstractions in a bottom-up manner, to convey both the capabilities and limitations of the silicon photonics paradigm in the context of deep learning acceleration.
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Tulpule, Bhal, Bruce Ohme, Mark Larson, Al Behbahani, John Gerety, and Al Steines. "A System On Chip (SOC) ASIC chipset for Aerospace and Energy Exploration Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000278–84. http://dx.doi.org/10.4071/hitec-tha11.
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This paper describes the design, key features and applications of a System On Chip (SOC) ASIC (Application Specific Integrated Circuit) chipset which was developed by Embedded Systems LLC as a part of the Smart Node based distributed control system architecture under an Air Force SBIR (Small Business Innovative Research) program {4}. The analog part of the SOC chipset has been implemented by Honeywell International under a subcontract using their high temperature SOI (Silicon On Insulator) Process. The complete chipset is expected to be available in early 2015. The key feature of the SOC chipset is that it is a reconfigurable and scalable building block that can be used to interface with most typical aerospace control system sensors and actuators. The SOC chipset captures all of the necessary functions required to power and interface with sensors such as RTD (Resistance Temperature Detectors), Strain Gauges (SG), Thermo Couples (TC) and transducers for measuring mass flow, speed, position or angle. The SOC chipset also contains all of the pre- and post-processing functions to convert electrical signals into digital words and send them on a data bus under the control of a host microprocessor. Finally, the SOC chipset contains PWM (Pulse Width Modulation) circuitry required to interface with external drives for actuators, motors, shutoff Valves etc. The SOC chipset can be powered from a Mil-Std-704F compliant power source or a conditioned DC power source. The chipset can be combined with other devices, such as memory, processor and A to D Converter to implement a high temperature capable Smart Node for localized management of sensors and actuators as a part of a distributed architecture or used as a scalable building block in a more complex function such as a FADEC (Full Authority Digital Engine Control). It is believed that the versatility of the SOC chipset makes it a well suited, affordable, scalable building block for not only aerospace controls but also for diverse applications such as down-hole drilling, energy exploration, wind farms etc. where high temperature electronics and /or high level of miniaturization is required.
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Kondo, Yoshisuke. "ASIC=Application specific integrated circuit." Journal of the Institute of Television Engineers of Japan 42, no. 6 (1988): 553–61. http://dx.doi.org/10.3169/itej1978.42.553.
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G.W.A.D. "Application specific integrated circuit (ASIC) technology." Microelectronics Reliability 32, no. 3 (March 1992): 447–48. http://dx.doi.org/10.1016/0026-2714(92)90076-w.
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Pantho, Md Jubaer Hossain, Pankaj Bhowmik, and Christophe Bobda. "Towards an Efficient CNN Inference Architecture Enabling In-Sensor Processing." Sensors 21, no. 6 (March 10, 2021): 1955. http://dx.doi.org/10.3390/s21061955.
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The astounding development of optical sensing imaging technology, coupled with the impressive improvements in machine learning algorithms, has increased our ability to understand and extract information from scenic events. In most cases, Convolution neural networks (CNNs) are largely adopted to infer knowledge due to their surprising success in automation, surveillance, and many other application domains. However, the convolution operations’ overwhelming computation demand has somewhat limited their use in remote sensing edge devices. In these platforms, real-time processing remains a challenging task due to the tight constraints on resources and power. Here, the transfer and processing of non-relevant image pixels act as a bottleneck on the entire system. It is possible to overcome this bottleneck by exploiting the high bandwidth available at the sensor interface by designing a CNN inference architecture near the sensor. This paper presents an attention-based pixel processing architecture to facilitate the CNN inference near the image sensor. We propose an efficient computation method to reduce the dynamic power by decreasing the overall computation of the convolution operations. The proposed method reduces redundancies by using a hierarchical optimization approach. The approach minimizes power consumption for convolution operations by exploiting the Spatio-temporal redundancies found in the incoming feature maps and performs computations only on selected regions based on their relevance score. The proposed design addresses problems related to the mapping of computations onto an array of processing elements (PEs) and introduces a suitable network structure for communication. The PEs are highly optimized to provide low latency and power for CNN applications. While designing the model, we exploit the concepts of biological vision systems to reduce computation and energy. We prototype the model in a Virtex UltraScale+ FPGA and implement it in Application Specific Integrated Circuit (ASIC) using the TSMC 90nm technology library. The results suggest that the proposed architecture significantly reduces dynamic power consumption and achieves high-speed up surpassing existing embedded processors’ computational capabilities.
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Pogra, Vivek, Santosh Kumar Vishvakarma, and Balwinder Raj. "Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Application." Sensor Letters 18, no. 1 (January 1, 2020): 31–38. http://dx.doi.org/10.1166/sl.2020.4176.
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This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the Internet. The transfer of data between different networks and internet of things (IoT) platform is controlled by IoT platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to the fact that it is designed for IoT applications. It is described in VHDL at RTL level and simulation is done on the Vivado 2016.2.
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Kong, Qing Chen, Guang Can Zhang, and Yong Xin Li. "Research on the Development of Large Application Specific Integrated Circuit Based on SOPC." Advanced Materials Research 328-330 (September 2011): 1663–66. http://dx.doi.org/10.4028/www.scientific.net/amr.328-330.1663.
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This paper introduces a design of ASIC with the advantages of high performance, low power, low cost and short development cycle, which is especially suitable for the middle and small scale production of complicated large programmable ASIC. Through introducing the performance and latest development of HardCopy series devices and Stratix FPGA series devices, and based on the development platform of Quartus II and Nios II system, this paper analyzes the complete development process of Stratix FPGA and HardCopy ASIC based on SOPC. This paper concludes the seamless transplant from Stratix FPGA to HardCopy ASIC based on the SOPC with IP multiplexing, which is the most promising development direction of producing large programmable ASIC with high performance and low cost in the future.
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Pogra, Vivek, Amandeep Singh, Santosh Kumar Vishvakarma, and Balwinder Raj. "Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Applications." Sensor Letters 18, no. 9 (September 1, 2020): 700–705. http://dx.doi.org/10.1166/sl.2020.4239.
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This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the internet. The transfer of data between different networks and electronic systems is controlled by internet of things (IoT) platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to SPI feature along with DMA on ASIC for IoT applications. It is described in very high speed integrated circuit hardware description language (VHDL) at register transfer level (RTL) and simulation is done on the Vivado 2016.2.
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Kameyama, Michitaka. "Special Issue on Computer Architecture for Robotics." Journal of Robotics and Mechatronics 2, no. 6 (December 20, 1990): 417. http://dx.doi.org/10.20965/jrm.1990.p0417.
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In the realization of intelligent robots, highly intelligent manipulation and movement techniques are required such as intelligent man-machine interfaces, intelligent information processing for path planning and problem solutions, practical robot vision, and high-speed sensor signal processing. Thus, very high-speed processing to cope with vast amounts of data as well as the development of various algorithms has become important subjects. To fulfill such requirements, the development of high-performance computer architecture using advanced microelectronics technology is required. For these purposes, the development of implementing computer systems’ for robots will be classified as follows: (a) Use of general-purpose computers As the performance of workstations and personal computers is increased year by year, software development is the major task without requiring hardware development except the interfaces with peripheral equipment. Since current high-level languages and software can be applied, the approach is excellent in case of system development, but the processing performance is limited. (b) Use of commercially available (V) LSI chips This is an approach to design a computer system by the combination of commercially available LSIs. Since the development of both hardware and software is involved in this system development, the development period tends to be longer than in (a). These chips include general-purpose microprocessors, memory chips, digital signal processors (DSPs) and multiply-adder LSIs. Though the kinds of available chips are limited to some degree, the approach can cope with a considerably high-performance specifications because a number of chips can be flexibly used. (c) Design, development and system configuration of VLSI chips This is an approach to develop new special-purpose VLSI chips using ASIC (Application Specific Integrated Circuit) technology, that is, semicustom or full-custom technology. If these attain practical use and are marketed, they will be widely used as high-performance VLSI chips of the level (b). Since a very high-performance specification must be satisfied, the study of very high performance VLSI computer architecture becomes very important. But this approach involving chip development requires a very long period in the design-development from the determination of processor specifications to the system configuration using the fabricated chips. For the above three approaches, the order from the viewpoint of ease of development will be (a), (b) and (c), while that from the viewpoint of performance will be (c), (b) and (a). Each approach is not exclusive but is complementary each other. For example, the development of new chips by (c) can also give new impact as the components of (a) and (b). Further, the common point of these approaches is that performance improvement by highly parallel architecture becomes important. This special edition introduces, from the above standpoint, the latest information on the present state and' future prospects of the computer techniques in Japan. We hope that this edition will contribute to the development of this field.
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Tariq, W. "Application-specific integrated circuit based image processor and its simulated results." Journal of Electronic Imaging 4, no. 3 (July 1, 1995): 260. http://dx.doi.org/10.1117/12.208653.
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Whitlow, Harry J. "Application specific integrated circuit (ASIC) readout technologies for future ion beam analytical instruments." Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms 161-163 (March 2000): 281–86. http://dx.doi.org/10.1016/s0168-583x(99)00709-0.
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Alonso, Oscar, Angel Diéguez, Sebastian Schostek, and Marc O. Schurr. "A System-on-Chip Solution for a Low Power Active Capsule Endoscope with Therapeutic Capabilities for Clip Application in the Gastrointestinal Tract." Journal of Medical Robotics Research 02, no. 04 (November 2, 2017): 1750005. http://dx.doi.org/10.1142/s2424905x17500052.
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This paper addresses the circuit implementation challenges resulting from the integration of a therapeutic clip in a magnetically maneuverable wireless capsule intended for colonoscopy. To deal with the size constraints typical of a capsule endoscope, an Application Specific Integrated Circuit (ASIC) has been designed specifically to habilitate the release of the therapeutic clip. The ASIC is a complete System on Chip (SoC) that incorporates a circuit for the low power release of the clip, thus overcoming the limitations of the power supply system. With a size of 14[Formula: see text]mm2, the ASIC can be incorporated in practically any capsule endoscope, consuming only an idle-state power of 1.5[Formula: see text]mW.
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FITRIO, DAVID, SUHARDI TJOA, ANAND MOHAN, RONNY VELJANOVSKI, ANDREW BERRY, and GORAN PANJKOVIC. "A CMOS ANALOG INTEGRATED CIRCUIT FOR PIXEL X-RAY DETECTOR." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 71–87. http://dx.doi.org/10.1142/s0218126611007086.
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A front-end read-out application specific integrated circuit (ASIC) for a multichannel pixel X-Ray detector system has been fabricated and tested. The chip provides signal amplification for pixelated compound semiconductors such as Cadmium Telluride ( CdTe ) and Cadmium Zinc Telluride ( CZT ) with either 1 mm or 200 μm pitch. Both the detector (compound semiconductor) and ASIC are combined to target future research applicable to spectroscopic imaging in high intensity X-Ray biomedical detector systems. The ASIC was fabricated in a 0.35 μm process by Austria Microsystems and consists of 32 channels, where each channel contains a charge-sensitive amplifier, a pulse shaper and two further stages of amplification providing an overall gain of 1 mV per kilo electron volt (keV) for photons within the energy range of 30–120 keV. The preamplifier and shaper circuits are designed for both positive and negative charge collection (electrons and holes) produced by the CdTe or CZT detectors. The ASIC's shaper has been designed with a time constant of 100 ns to allow operation at photon rate events above 1 Million photons per pixel per second. The design and characterization of the readout chip will be discussed in this paper presenting results from both the simulated and the fabricated chip.
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Huang, Sheng-Chieh, Hui-Min Wang, and Wei-Yu Chen. "A ±6 ms-Accuracy, 0.68 mm2, and 2.21 μW QRS Detection ASIC." VLSI Design 2012 (November 22, 2012): 1–13. http://dx.doi.org/10.1155/2012/809393.
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Healthcare issues arose from population aging. Meanwhile, electrocardiogram (ECG) is a powerful measurement tool. The first step of ECG is to detect QRS complexes. A state-of-the-art QRS detection algorithm was modified and implemented to an application-specific integrated circuit (ASIC). By the dedicated architecture design, the novel ASIC is proposed with 0.68 mm2 core area and 2.21 μW power consumption. It is the smallest QRS detection ASIC based on 0.18 μm technology. In addition, the sensitivity is 95.65% and the positive prediction of the ASIC is 99.36% based on the MIT/BIH arrhythmia database certification.
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Zhang, Ai Rong. "The Integration on Electrical Control Systems Based on Optimized Method." Advanced Materials Research 490-495 (March 2012): 2604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2604.
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Very large scale integration (VLSI) applications have improved control implementation performance. Indeed, an application specific integrated circuit (ASIC) solution can exploit efficiently specificities of the control algorithms that fixed hardware architecture cannot do. For example, parallel calculation cannot be included in a software solution based on sequential processing. In addition, ASIC can reduce wire and electromagnetic field interference by a fully system on a chip (SoC) integration. However, there are still two main drawbacks to an integrated circuit solution: design complexity and reuse difficulty. This is true even with programmable logic device (PLD) solutions. Conception aid developer (CAD) combined with hardware description languages (HDL) and VLSI design methodology have accelerated conception and reuse. Nevertheless, the main problem of integrated circuit design is to define the hardware architecture; this is particularly true for heterogeneous algorithm structures such as electrical controls.
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Rydygier, Przemysław, Władysław Dąbrowski, Tomasz Fiutowski, and Piotr Wiącek. "Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode Arrays." International Journal of Electronics and Telecommunications 56, no. 4 (November 1, 2010): 399–404. http://dx.doi.org/10.2478/v10177-010-0053-9.
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Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode ArraysIn the paper we present the design and test results of an integrated circuit combining a sample&hold circuit and an analogue multiplexer. The circuit has been designed as a building block for a multi-channel Application Specific Integrated Circuit (ASIC) for recording signals from alive neuronal tissue using high-density micro-electrode arrays (MEAs). The design is optimised with respect to critical requirements for such applications, i.e. short sampling time, low power dissipation, good linearity and high dynamic range. Presented design comprises sample&hold circuits with class AB operational amplifier, novel shift register, which allows minimising cross-coupling of the clock signal and control logic. The circuit has been designed in 0.35μm CMOS process and has been successfully implemented in a prototype multi-channel ASIC.
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Yuan, Yu Ying, and Yong Gang Luo. "The ASIC Design and Verification Based on Verilog HDL." Advanced Materials Research 433-440 (January 2012): 4578–83. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.4578.
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Logic design and verification is the frontend of ASIC (Application Specific Integrated Circuit), and is a very important design part during the design process of ASIC. A Verilog HDL design case－2×2 SDH digital cross-connect matrix is provided to illustrate the entire design process including logic-level description, verification and synthesis based on the frontend tools of Synopsys. After that a gate-level netlist conforming to the design requirements can be obtained.
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Abraitis, Vidas, and Žydrūnas Tamoševičius. "Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA." Solid State Phenomena 144 (September 2008): 214–19. http://dx.doi.org/10.4028/www.scientific.net/ssp.144.214.
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Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) of Virtex family. Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration.
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Bahr, Andreas, Lait Abu Saleh, Dietmar Schroeder, and Wolfgang H. Krautschneider. "High speed digital interfacing for a neural data acquisition system." Current Directions in Biomedical Engineering 2, no. 1 (September 1, 2016): 87–90. http://dx.doi.org/10.1515/cdbme-2016-0022.
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AbstractDiseases like schizophrenia and genetic epilepsy are supposed to be caused by disorders in the early development of the brain. For the further investigation of these relationships a custom designed application specific integrated circuit (ASIC) was developed that is optimized for the recording from neonatal mice [Bahr A, Abu-Saleh L, Schroeder D, Krautschneider W. 16 Channel Neural Recording Integrated Circuit with SPI Interface and Error Correction Coding. Proc. 9th BIOSTEC 2016. Biodevices: Rome, Italy, 2016; 1: 263; Bahr A, Abu-Saleh L, Schroeder D, Krautschneider W. Development of a neural recording mixed signal integrated circuit for biomedical signal acquisition. Biomed Eng Biomed Tech Abstracts 2015; 60(S1): 298–299; Bahr A, Abu-Saleh L, Schroeder D, Krautschneider WH. 16 Channel Neural Recording Mixed Signal ASIC. CDNLive EMEA 2015 Conference Proceedings, 2015.]. To enable the live display of the neural signals a multichannel neural data acquisition system with live display functionality is presented. It implements a high speed data transmission from the ASIC to a computer with a live display functionality. The system has been successfully implemented and was used in a neural recording of a head-fixed mouse.
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Kim, Hyunjun, Kyungho Kim, Hyeokdong Kwon, and Hwajeong Seo. "ASIC-Resistant Proof of Work Based on Power Analysis of Low-End Microcontrollers." Mathematics 8, no. 8 (August 12, 2020): 1343. http://dx.doi.org/10.3390/math8081343.
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Application-Specific Integrated Circuit (ASIC)-resistant Proof-of-Work (PoW) is widely adopted in modern cryptocurrency. The operation of ASIC-resistant PoW on ASIC is designed to be inefficient due to its special features. In this paper, we firstly introduce a novel ASIC-resistant PoW for low-end microcontrollers. We utilized the measured power trace during the cryptographic function on certain input values. Afterward, the post-processing routine was performed on the power trace to remove the noise. The refined power trace is always constant information depending on input values. By performing the hash function with the power trace, the final output was obtained. This framework only works on microcontrollers and the power trace depends on certain input values, which is not predictable and computed by ASIC.
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Khan, Angshuman, Sudip Halder, and Shubhajit Pal. "Design of ASIC Square Calculator Using AncientVedic Mathematics." International Journal of Engineering & Technology 7, no. 2.23 (April 20, 2018): 464. http://dx.doi.org/10.14419/ijet.v7i2.23.15334.
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This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.
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Hou, Bo, Bin Zhou, Xiang Li, Zhenyi Gao, Qi Wei, and Rong Zhang. "An Analog Interface Circuit for Capacitive Angle Encoder Based on a Capacitance Elimination Array and Synchronous Switch Demodulation Method." Sensors 19, no. 14 (July 15, 2019): 3116. http://dx.doi.org/10.3390/s19143116.
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This paper presents an analog interface application-specific integrated circuit (ASIC) for a capacitive angle encoder, which is widely used in control machine systems. The encoder consists of two parts: a sensitive structure and analog readout circuit. To realize miniaturization, low power consumption, and easy integration, an analog interface circuit including a DC capacitance elimination array and switch synchronous demodulation module was designed. The DC capacitance elimination array allows the measurement circuit to achieve a very high capacitance to voltage conversion ratio at a low supply voltage. Further, the switch synchronous demodulation module effectively removes the carrier signal and greatly reduces the sampling rate requirement of the analog-to-digital converter (ADC). The ASIC was designed and fabricated with standard 0.18 µm CMOS processing technology and integrated with the sensitive structure. An experiment was conducted to test and characterize the performance of the proposed analog interface circuit. The encoder measurement results showed a resolution of 0.01°, power consumption of 20 mW, and accuracy over the full absolute range of 0.1°, which indicates the great potential of the encoder for application in control machine systems.
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Assaf, Mansour, Leslie-Ann Moore, Sunil Das, Satyendra Biswas, and Scott Morton. "Low-level logic fault testing ASIC simulation environment." World Journal of Engineering 11, no. 3 (June 1, 2014): 279–86. http://dx.doi.org/10.1260/1708-5284.11.3.279.
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A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation environment emulates a typical built-in self-testing (BIST) environment with test pattern generator (TPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The developed simulator is very suitable for testing embedded digital intellectual property (IP) cores-based systems. The paper describes the total test architecture environment, including the application of the logic fault simulator. Results on simulation on some specific International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.
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Qi, Min, An-qiang Guo, and Dong-hai Qiao. "A High-Temperature, Low-Noise Readout ASIC for MEMS-Based Accelerometers." Sensors 20, no. 1 (December 31, 2019): 241. http://dx.doi.org/10.3390/s20010241.
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This paper presents the development and measurement results of a complementary metal oxide semiconductor (CMOS) readout application-specific integrated circuit (ASIC) for bulk-silicon microelectromechanical system (MEMS) accelerometers. The proposed ASIC converts the capacitance difference of the MEMS sensor into an analog voltage signal and outputs the analog signal with a buffer. The ASIC includes a switched-capacitor analog front-end (AFE) circuit, a low-noise voltage reference generator, and a multi-phase clock generator. The correlated double sampling technique was used in the AFE circuits to minimize the low-frequency noise of the ASIC. A programmable capacitor array was implemented to compensate for the capacitance offset of the MEMS sensor. The ASIC was developed with a 0.18 μm CMOS process. The test results show that the output noise floor of the low-noise amplifier was −150 dBV/√Hz at 100 Hz and 175 °C, and the sensitivity of the AFE was 750 mV/pF at 175 °C. The output noise floor of the voltage reference at 175 °C was −133 dBV/√Hz at 10 Hz and −152 dBV/√Hz at 100 Hz.
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Li, Jie, Wei Wei Shan, and Chao Xuan Tian. "Hamming Distance Model Based Power Analysis for Cryptographic Algorithms." Applied Mechanics and Materials 121-126 (October 2011): 867–71. http://dx.doi.org/10.4028/www.scientific.net/amm.121-126.867.
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In order to evaluate the security of Application Specific Integrated Circuit (ASIC) implemented cryptographic algorithms at an early design stage, a Hamming distance model based power analysis is proposed. The Data Encryption Standard (DES) algorithm is taken as an example to illustrate the threats of differential power analysis (DPA) attack against the security of ASIC chip. A DPA attack against the ASIC implementation of a DES algorithm is realized based on hamming distance power model (HD model), and it realized the attack by successfully guessing the right 48-bit subkey. This result indicates that the power analysis attack based on the HD model is simple, rapid and effective for the design and evaluation of security chips.
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FANG, RAN, WENGAO LU, GUANNAN WANG, TINGTING TAO, YACONG ZHANG, ZHONGJIAN CHEN, and DUNSHAN YU. "A LOW-NOISE HIGH-VOLTAGE INTERFACE CIRCUIT FOR CAPACITIVE MEMS GYROSCOPE." Journal of Circuits, Systems and Computers 22, no. 09 (October 2013): 1340019. http://dx.doi.org/10.1142/s0218126613400197.
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This paper presents a high-voltage control and readout interface circuit implemented for capacitive Micro-Electro-Mechanic System (MEMS) gyroscope. A charge sensitive amplifier (CSA) with chopper technique is used to accomplish low-noise capacitive sensing. The stabilization of the closed drive loop is maintained by an auto gain controller (AGC) and an adjustable phase shifter. The outputs of the ASIC directly drive the gyroscope after buffered by an on-chip high-voltage level shifter. The chip is fabricated in a 0.35 um 5 V/12 V Bipolar, CMOS and DMOS (BCD) process. The test of the chip is performed with a MEMS vibratory gyroscope. The result shows that the Application Specific Integrated Circuit (ASIC) can ensure a stable oscillation in the drive axis, and the noise floor is 0.0015°/s/√Hz within 100 Hz.
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Ranjan, Rajeev, Pablo Mendoza Ponce, Wolf Lukas Hellweg, Alexandros Kyrmanidis, Lait Abu Saleh, Dietmar Schroeder, and Wolfgang H. Krautschneider. "Integrated Circuit with Memristor Emulator Array and Neuron Circuits for Biologically Inspired Neuromorphic Pattern Recognition." Journal of Circuits, Systems and Computers 26, no. 11 (May 31, 2017): 1750183. http://dx.doi.org/10.1142/s0218126617501833.
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This paper details an application-specific integrated circuit (ASIC) with an array of switched-resistor-based memristors (resistor with memory) and integrate & fire (I & F) neuron circuits for the development of memristor-based pattern recognition. Since real memristors are not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has five memristor emulators with one having a conductance range from 4.88[Formula: see text]ns to 4.99[Formula: see text][Formula: see text]s (200[Formula: see text]k[Formula: see text] to 204.8[Formula: see text]M[Formula: see text]) and other four having conductance ranging from 195[Formula: see text]ns to 190[Formula: see text][Formula: see text]s (5.2[Formula: see text]k[Formula: see text] to 5.12[Formula: see text]M[Formula: see text]). Signal processing has been planned to be off-chip to get the freedom of programmability of a wide range of memristive behavior. This paper introduces the memristor emulator and the realization of synapse functionalities used in neuromorphic circuits such as long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has two I & F neuron circuits which are intended to be used in conjunction with memristors in a multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neuron circuit and a respective neuromorphic system for pattern recognition simulated in LTspice. The ASIC has been fabricated in AMS 350[Formula: see text]nm process.
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Makihata, Mitsutoshi, Masanori Muroyama, Shuji Tanaka, Takahiro Nakayama, Yutaka Nonomura, and Masayoshi Esashi. "Design and Fabrication Technology of Low Profile Tactile Sensor with Digital Interface for Whole Body Robot Skin." Sensors 18, no. 7 (July 21, 2018): 2374. http://dx.doi.org/10.3390/s18072374.
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Covering a whole surface of a robot with tiny sensors which can measure local pressure and transmit the data through a network is an ideal solution to give an artificial skin to robots to improve a capability of action and safety. The crucial technological barrier is to package force sensor and communication function in a small volume. In this paper, we propose the novel device structure based on a wafer bonding technology to integrate and package capacitive force sensor using silicon diaphragm and an integrated circuit separately manufactured. Unique fabrication processes are developed, such as the feed-through forming using a dicing process, a planarization of the Benzocyclobutene (BCB) polymer filled in the feed-through and a wafer bonding to stack silicon diaphragm onto ASIC (application specific integrated circuit) wafer. The ASIC used in this paper has a capacitance measurement circuit and a digital communication interface mimicking a tactile receptor of a human. We successfully integrated the force sensor and the ASIC into a 2.5 × 2.5 × 0.3 mm die and confirmed autonomously transmitted packets which contain digital sensing data with the linear force sensitivity of 57,640 Hz/N and 10 mN of data fluctuation. A small stray capacitance of 1.33 pF is achieved by use of 10 μm thick BCB isolation layer and this minimum package structure.
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Liu, Yu-Sian, and Kuei-Ann Wen. "Implementation of a CMOS/MEMS Accelerometer with ASIC Processes." Micromachines 10, no. 1 (January 12, 2019): 50. http://dx.doi.org/10.3390/mi10010050.
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This paper presents the design, simulation and mechanical characterization of a newly proposed complementary metal-oxide semiconductor (CMOS)/micro-electromechanical system (MEMS) accelerometer. The monolithic CMOS/MEMS accelerometer was fabricated using the 0.18 μm application-specific integrated circuit (ASIC)-compatible CMOS/MEMS process. An approximate analytical model for the spring design is presented. The experiments showed that the resonant frequency of the proposed tri-axis accelerometer was around 5.35 kHz for out-plane vibration. The tri-axis accelerometer had an area of 1096 μm × 1256 μm.
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Li, Xiangyu, Yangong Zheng, Xiangyan Kong, Yupeng Liu, and Danling Tang. "Research on High-Resolution Miniaturized MEMS Accelerometer Interface ASIC." Sensors 20, no. 24 (December 18, 2020): 7280. http://dx.doi.org/10.3390/s20247280.
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High-precision microelectromechanical system (MEMS) accelerometers have wide application in the military and civil fields. The closed-loop microaccelerometer interface circuit with switched capacitor topology has a high signal-to-noise ratio, wide bandwidth, good linearity, and easy implementation in complementary metal oxide semiconductor (CMOS) process. Aiming at the urgent need for high-precision MEMS accelerometers in geophones, we carried out relevant research on high-performance closed-loop application specific integrated circuit (ASIC) chips. According to the characteristics of the performance parameters and output signal of MEMS accelerometers used in geophones, a high-precision closed-loop interface ASIC chip based on electrostatic time-multiplexing feedback technology and proportion integration differentiation (PID) feedback control technology was designed and implemented. The interface circuit consisted of a low-noise charge-sensitive amplifier (CSA), a sampling and holding circuit, and a PID feedback circuit. We analyzed and optimized the noise characteristics of the interface circuit and used a capacitance compensation array method to eliminate misalignment of the sensitive element. The correlated double sampling (CDS) technology was used to eliminate low-frequency noise and offset of the interface circuit. The layout design and engineering batch chip were fabricated by a standard 0.35 μm CMOS process. The active area of the chip was 3.2 mm × 3 mm. We tested the performance of the accelerometer system with the following conditions: power dissipation of 7.7 mW with a 5 V power supply and noise density less than 0.5 μg/Hz1/2. The accelerometers had a sensitivity of 1.2 V/g and an input range of ±1.2 g. The nonlinearity was 0.15%, and the bias instability was about 50 μg.
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Seybold, Jonathan, André Bülau, Karl-Peter Fritz, Alexander Frank, Cor Scherjon, Joachim Burghartz, and André Zimmermann. "Miniaturized Optical Encoder with Micro Structured Encoder Disc." Applied Sciences 9, no. 3 (January 29, 2019): 452. http://dx.doi.org/10.3390/app9030452.
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A novel optical incremental and absolute encoder based on an optical application-specific integrated circuit (opto-ASIC) and an encoder disc carrying micro manufactured structures is presented. The physical basis of the encoder is the diffraction of light using a reflective phase grating. The opto-ASIC contains a ring of photodiodes that represents the encryption of the encoder. It also includes the analog signal conditioning, the signal acquisition, and the control of a light source, as well as the digital position processing. The development and fabrication of the opto-ASIC is also described in this work. A laser diode was assembled in the center on top of the opto-ASIC, together with a micro manufactured polymer lens. The latter was fabricated using ultra-precision machining. The encoder disc was fabricated using micro injection molding and contains micro structures forming a blazed grating. This way, a 10-bit optical encoder with a form factor of only 1 cm3 was realized and tested successfully.
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Kledrowetz, Vilem, Roman Prokop, Lukas Fujcik, Michal Pavlik, and Jiří Háze. "Low-power ASIC suitable for miniaturized wireless EMG systems." Journal of Electrical Engineering 70, no. 5 (September 1, 2019): 393–99. http://dx.doi.org/10.2478/jee-2019-0071.
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Abstract Nowadays, the technology advancements of signal processing, low-voltage low-power circuits and miniaturized circuits have enabled the design of compact, battery-powered, high performance solutions for a wide range of, particularly, biomedical applications. Novel sensors for human biomedical signals are creating new opportunities for low weight wearable devices which allow continuous monitoring together with freedom of movement of the users. This paper presents the design and implementation of a novel miniaturized low-power sensor in integrated circuit (IC) form suitable for wireless electromyogram (EMG) systems. Signal inputs (electrodes) are connected to this application-specific integrated circuit (ASIC). The ASIC consists of several consecutive parts. Signals from electrodes are fed to an instrumentation amplifier (INA) with fixed gain of 50 and filtered by two filters (a low-pass and high-pass filter), which remove useless signals and noise with frequencies below 20 Hz and above 500 Hz. Then signal is amplified by a variable gain amplifier. The INA together with the reconfigurable amplifier provide overall gain of 50, 200, 500 or 1250. The amplified signal is then converted to pulse density modulated (PDM) signal using a 12-bit delta-sigma modulator. The ASIC is fabricated in TSMC0.18 mixed-signal CMOS technology.
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Iakovidis, George. "VMM - An ASIC for Micropattern Detectors." EPJ Web of Conferences 174 (2018): 07001. http://dx.doi.org/10.1051/epjconf/201817407001.
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The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a variety of charge interpolating tracking detectors. It is designed to be used with the resistive strip micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. It is packaged in a Ball Grid Array with outline dimensions of 21×21 mm2. It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM1 and VMM2 are the first two versions of the VMM ASIC family fabricated in 2012 and 2014 respectively. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 are described.
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Utz, Alexander, Christian Walk, Norbert Haas, Tatjana Fedtschenko, Alexander Stanitzki, Mir Mokhtari, Michael Görtz, Michael Kraft, and Rainer Kokozinski. "An ultra-low noise capacitance to voltage converter for sensor applications in 0.35 µm CMOS." Journal of Sensors and Sensor Systems 6, no. 2 (August 22, 2017): 285–301. http://dx.doi.org/10.5194/jsss-6-285-2017.
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Abstract. In this paper we present a readout circuit for capacitive micro-electro-mechanical system (MEMS) sensors such as accelerometers, gyroscopes or pressure sensors. A flexible interface allows connection of a wide range of types of sensing elements. The ASIC (application-specific integrated circuit) was designed with a focus on ultra-low noise operation and high analog measurement performance. Theoretical considerations on system noise are presented which lead to design requirements affecting the reachable overall measurement performance. Special emphasis is put on the design of the fully differential operational amplifiers, as these have the dominant influence on the achievable overall performance. The measured input referred noise is below 50 zF/Hz within a bandwidth of 10 Hz to 10 kHz. Four adjustable gain settings allow the adaption to measurement ranges from ±750 fF to ±3 pF. This ensures compatibility with a wide range of sensor applications. The full input signal bandwidth ranges from 0 Hz to more than 50 kHz. A high-precision accelerometer system was built from the described ASIC and a high-sensitivity, low-noise sensor MEMS. The design of the MEMS is outlined and the overall system performance, which yields a combined noise floor of 200 ng/Hz, is demonstrated. Finally, we show an application using the ASIC together with a CMOS integrated capacitive pressure sensor, which yields a measurement signal-to-noise ratio (SNR) of more than 100 dB.
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Zhou, Li, Jun She An, Qing Wen Fang, and Fei Cai. "Design of an ASIC Chip for Spacecraft Data System." Applied Mechanics and Materials 390 (August 2013): 611–15. http://dx.doi.org/10.4028/www.scientific.net/amm.390.611.
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ASIC (Application Specific Integrated Circuit) technology is mature and widely used in many fields. It is a trend to integrate some common spacecraft engineering requirements into one chip to take the place of FPGA and some digital chips, which can miniaturize spacecraft avionics and reduce the repeated work for spacecraft engineers. Based on the analysis on small satellites application requirements, the system design of an ASIC chip for spacecraft data system is proposed. Firstly, the chip system architecture is described. Secondly, four key technologies of the ASIC chip design are presented in detail. They are the design of the chip's operating modes, the design of IP cores, the design of reliability, and the design of low power consumption. Generality, adaptability and independent intellectual property make this ASIC different and special from other space chips. Four operating modes are optional: 1553B bus control mode, PCI control mode, ISA control mode, internal CPU control mode. Besides, there are 1553B bus protocol IP cores, CAN bus interface, and abundant peripherals, which can satisfy most of the routine engineering requirements in small satellites. Finally, the chips status and some promising applications are described.
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Pham, Giao N., Anh N. Bui, Binh A. Nguyen, Tung V. Nguyen, and Hai T. Nguyen. "Fast IQ Amplitude Approximation Method for ASIC Digital System." International Journal of Emerging Technology and Advanced Engineering 11, no. 8 (August 19, 2021): 19–22. http://dx.doi.org/10.46338/ijetae0821_03.
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In some modules of digital systems, such as Fast Fourier Transform (FFT), Discrete Fourier transform (DFT), IQ (in-phase and quadrature components) modulation/ demodulation, the outputs use the complex data formed , and the calculation of its magnitude value √ are required. In software digital signal processing platform, the multiplication and square root operations are executed by using its math library; however, in Application specific integrated circuit (ASIC) digital system design, the implementation of those operators via Coordinate Rotation Digital Computer (CORDIC) algorithm requires the numerous resources and delays. So, in this paper, we present a fast approximation method for above problem which takes a small delay but acceptable accuracy for AISC digital system design. Keywords—ASIC, Digital system design, FFT, DFT, Fast amplitude approximation, Max-Min approximation.
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Gryboś, Paweł, Piotr Kmon, Robert Szczygieł, and Mirosław Żołądź. "64 Channel ASIC for Neurobiology Experiments." International Journal of Electronics and Telecommunications 56, no. 4 (November 1, 2010): 375–80. http://dx.doi.org/10.2478/v10177-010-0049-5.
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64 Channel ASIC for Neurobiology ExperimentsThis paper presents the design and measurements of 64 channel Application Specific Integrated Circuits (ASIC) for recording signals in neurobiology experiments. The ASIC is designed in 180 nm technology and operates with ± 0.9 V supply voltage. Single readout channel is built of AC coupling circuit at the input and two amplifier stages. In order to reduce the number of output lines, the 64 analogue signals from readout channels are multiplexed to a single output by an analogue multiplexer. The gain of the single channel can be set either to 350 V/V or 700 V/V. The low and the high cut-off frequencies can be tuned in 9 ÷ 90 Hz and in the 1.6 ÷ 24 kHz range respectively. The input referred noise is 7 μV rms in the bandwidth 90 Hz - 1.6 kHz and 9 μV rms in the bandwidth 9 Hz - 24 kHz. The single channel consumes 200 μW of power and this together with other parameters make the chip suitable for recording neurobiology signals.
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Wang, Li, Hui-Bin Tao, Hang Dong, Zhi-Biao Shao, and Fei Wang. "A Non-Linear Temperature Compensation Model for Improving the Measurement Accuracy of an Inductive Proximity Sensor and Its Application-Specific Integrated Circuit Implementation." Sensors 20, no. 17 (September 3, 2020): 5010. http://dx.doi.org/10.3390/s20175010.
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The non-linear characteristic of a non-contacting Inductive Proximity Sensor (IPS) with the temperature affects the computation accuracy when measuring the target distance in real time. The linear model based method for distance estimation shows a large deviation at a low temperature. Accordingly, this paper presents a non-linear measurement model, which computes the target distance accurately in real time within a wide temperature range from −55 °C to 125 °C. By revisiting the temperature effect on the IPS system, this paper considers the non-linear characteristic of the IPS measurement system due to the change of temperature. The proposed model adopts a non-linear polynomial algorithm rather than the simple linear Look-Up Table (LUT) method, which provides more accurate distance estimation compared to the previous work. The introduced model is fabricated in a 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) process and packaged in a CQFN40. For the most commonly used sensing distance of 4 mm, the computed distance deviation of the Application-Specific Integrated Circuit (ASIC) chips falls within the range of [−0.2,0.2] mm. According to the test results of the ASIC chips, this non-linear temperature compensation model successfully achieves real-time and high-accuracy computation within a wide temperature range with low hardware resource consumption.
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Kim, Taehoon, Fabian Fool, Djalma Simoes dos Santos, Zu-Yao Chang, Emile Noothout, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jong, and Michiel A. P. Pertijs. "Design of an Ultrasound Transceiver ASIC with a Switching-Artifact Reduction Technique for 3D Carotid Artery Imaging." Sensors 21, no. 1 (December 29, 2020): 150. http://dx.doi.org/10.3390/s21010150.
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This paper presents an ultrasound transceiver application-specific integrated circuit (ASIC) directly integrated with an array of 12 × 80 piezoelectric transducer elements to enable next-generation ultrasound probes for 3D carotid artery imaging. The ASIC, implemented in a 0.18 µm high-voltage Bipolar-CMOS-DMOS (HV BCD) process, adopted a programmable switch matrix that allowed selected transducer elements in each row to be connected to a transmit and receive channel of an imaging system. This made the probe operate like an electronically translatable linear array, allowing large-aperture matrix arrays to be interfaced with a manageable number of system channels. This paper presents a second-generation ASIC that employed an improved switch design to minimize clock feedthrough and charge-injection effects of high-voltage metal–oxide–semiconductor field-effect transistors (HV MOSFETs), which in the first-generation ASIC caused parasitic transmissions and associated imaging artifacts. The proposed switch controller, implemented with cascaded non-overlapping clock generators, generated control signals with improved timing to mitigate the effects of these non-idealities. Both simulation results and electrical measurements showed a 20 dB reduction of the switching artifacts. In addition, an acoustic pulse-echo measurement successfully demonstrated a 20 dB reduction of imaging artifacts.
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Wu, Sheng-Tsai, John H. Lau, Heng-Chieh Chien, Yu-Lin Chao, Ra-Min Tain, Li Li, Peng Su, Jie Xue, and Mark Brillhart. "Thermal Stress and Creep Strain Analyses of a 3D IC Integration SiP with Passive Interposer for Network System Application." International Symposium on Microelectronics 2012, no. 1 (January 1, 2012): 001038–45. http://dx.doi.org/10.4071/isom-2012-thp14.
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In this study, the nonlinear thermal stress distributions at the Cu-low-k pads of Moore's law chips and creep strain energy density per cycle at the solder joints of a 3D IC integration system-in-package (SiP) are investigated. At the same time, the warpage of the TSV interposer and reliability assessment of solder joints in the architecture is examined. The analyzed structure comprises one PCB (printed circuit board), one BT (bismaleimide triazene) substrate, one interposer with through silicon vias (TSVs), two DRAM (dynamic random access memory) chips and one high power ASIC (application specific integrated circuit) chip. The high power chip and DRAM chips are supported, respectively on the top-side and bottom-side of the Cu-filled TSV interposer.
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Yaacob, Nor Samida. "Low Power Ring Oscillator Design in 130nm CMOS Technology." Journal of Engineering and Science Research 3, no. 3 (June 28, 2019): 14–18. http://dx.doi.org/10.26666/rmp.jesr.2019.3.3.
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A temperature-stable, low-power ring oscillator design for implementation in an Application-Specific Integrated Circuit (ASIC) is presented. In this work, the design uses a new arrangement of chain delay elements consisting of a current-starved inverter and a CMOS capacitor. This power consumption improvement ring oscillator design was built in the environment of 130nm CMOS process technology using Mentor Graphics environment with voltage supply 1V. The simulation results show a maximum power consumption of 1.036 nW and it shows that the presented design is applicable in low power advanced sensing systems application including biomedical, chemical, and other sensors.
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Zushi, Takahiro, Hirotsugu Kojima, and Hiroshi Yamakawa. "One-chip analog circuits for a new type of plasma wave receiver on board space missions." Geoscientific Instrumentation, Methods and Data Systems 6, no. 1 (March 31, 2017): 159–67. http://dx.doi.org/10.5194/gi-6-159-2017.
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Abstract. Plasma waves are important observational targets for scientific missions investigating space plasma phenomena. Conventional fast Fourier transform (FFT)-based spectrum plasma wave receivers have the disadvantages of a large size and a narrow dynamic range. This paper proposes a new type of FFT-based spectrum plasma wave receiver that overcomes the disadvantages of conventional receivers. The receiver measures and calculates the whole spectrum by dividing the observation frequency range into three bands: bands 1, 2, and 3, which span 1 Hz to 1 kHz, 1 to 10 kHz, and 10 to 100 kHz, respectively. To reduce the size of the receiver, its analog section was realized using application-specific integrated circuit (ASIC) technology, and an ASIC chip was successfully developed. The dimensions of the analog circuits were 4.21 mm × 1.16 mm. To confirm the performance of the ASIC, a test system for the receiver was developed using the ASIC, an analog-to-digital converter, and a personal computer. The frequency resolutions for bands 1, 2, and 3 were 3.2, 32, and 320 Hz, respectively, and the average time resolution was 384 ms. These frequency and time resolutions are superior to those of conventional FFT-based receivers.