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Relevant bibliographies by topics / ASIC design

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Academic literature on the topic 'ASIC design'

Author: Grafiati

Published: 4 June 2021

Last updated: 12 June 2025

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Journal articles on the topic "ASIC design"

1

Alford, David B. "ASIC design with VHDL." ACM SIGDA Newsletter 20, no. 3 (1991): 32–51. http://dx.doi.org/10.1145/122561.122562.

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Trontelj, J., and L. Trontelj. "Analog-digital ASIC design." Microelectronics Journal 21, no. 2 (1990): 41–51. http://dx.doi.org/10.1016/0026-2692(90)90025-x.

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Hasan, M. M., and Rajeev Jain. "PLA in ASIC Design." IETE Technical Review 6, no. 3 (1989): 237–39. http://dx.doi.org/10.1080/02564602.1989.11438479.

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Scarabotollo, N. "Session D2: ASIC design." Microprocessing and Microprogramming 38, no. 1-5 (1993): 343. http://dx.doi.org/10.1016/0165-6074(93)90164-g.

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Patterson, EB, PG Holmes, and D. Morley. "Microprocessor/ASIC to total ASIC design for cycloconverter drives." Microprocessors and Microsystems 14, no. 4 (1990): 219–26. http://dx.doi.org/10.1016/0141-9331(90)90081-6.

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Hamilton, S. N., and A. Orailoglu. "Efficient self-recovering ASIC design." IEEE Design & Test of Computers 15, no. 4 (1998): 25–35. http://dx.doi.org/10.1109/54.735924.

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Newton, A. R., and A. L. Sangiovanni-Vincentelli. "CAD tools for ASIC design." Proceedings of the IEEE 75, no. 6 (1987): 765–76. http://dx.doi.org/10.1109/proc.1987.13798.

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Bednar, T. R., R. A. Piro, D. W. Stout, L. Wissel, and P. S. Zuchowski. "Technology-migratable ASIC library design." IBM Journal of Research and Development 40, no. 4 (1996): 377–86. http://dx.doi.org/10.1147/rd.404.0377.

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Redmond, Sean. "High-level ASIC design tools." Microelectronics Journal 23, no. 3 (1992): 231–38. http://dx.doi.org/10.1016/0026-2692(92)90015-s.

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Manck, O. "Neue Schnittstellen im Asic-Design." Electrical Engineering 79, no. 2 (1996): 85–91. http://dx.doi.org/10.1007/bf01232916.

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Dissertations / Theses on the topic "ASIC design"

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Lothian, Angus, Ivar Härnqvist, Adam Jakobsson, et al. "B-ASIC - Better ASIC Toolbox : En verktygslåda som förenklar design och optimering av ASIC." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-167069.

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Denna rapport behandlar ett arbete skriven av åtta studenter som läste kursen TDDD96 Kandidatprojekt i programvaruutveckling vid Linköpings universitet under vårterminen 2020. Projektets syfte var att utveckla en verktygslåda i Python och C++ för att konstruera signalbehandlade kretsar. Denna verktygslåda är tänkt att användas inom laborationer i kursen TSTE87 Applikationsspecfika integrerande kretsar vid Linköpings universitet och inom forskning för utveckling av ASIC:s. Projektet resulterade i produkten B-ASIC. B-ASIC är ett bibliotek för programmeringsspråket Python som är skrivet i Python med en underliggande modul i C++. B-ASIC används för design och optimering av ASIC:s. Produkten B-ASIC erbjuder ett grafiskt användargränssnitt där användaren kan interagera med biblioteket utan programmeringskunskaper inom Python. I rapporten beskrivs hur projektarbetet har anpassats för att vara till värde för kunden och hur utvecklingsprocessen har påverkat resultatet av produkten. Projektmedlemmarna har dessutom genomfört egna undersökningar och dessa finns att läsa i slutet av rapporten.

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Ehliar, Andreas. "Performance driven FPGA design with an ASIC perspective." Doctoral thesis, Linköpings universitet, Datorteknik, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16372.

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FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient. This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA. Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA. The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated. All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs. Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.

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Han, Tony. "SWASAD Smith & Waterman-algorithm-specific ASIC design /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16391.pdf.

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Venditti, Michael B. "Receiver, transmitter, and ASIC design for optoelectronic-VLSI applications." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=84444.

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In modern digital systems, off-chip and intra-chip electrical interconnections suffer from a multitude of limitations as integrated circuits (ICs) continue to grow in size and processing capacity. Optical interconnects are capable of meeting the increasing I/O bandwidth needs in these systems. Optoelectronic-VLSI (OE-VLSI) technology incorporates optical I/O with ICs through the integration of arrays of optoelectronic devices with on-chip receiver and transmitter circuits. These optical I/Os are intended to replace or complement electrical interconnects for off-chip connections, and for connections between processing modules on the same chip or in a multi-chip module.<br>The design of receivers, transmitters, and OE-VLSI application-specific integrated circuits (ASICs) are described from a system implementation perspective. Numerous techniques to overcome technological problems and allow the successful operation of large receiver and transmitter arrays are considered. The use of a fully differential optical and electrical architecture is strongly advocated. The testing of receiver and transmitter circuits and skew in highly parallel and synchronous digital systems employing optical receivers is also considered.<br>The major portion of this thesis details the design, construction, and optical and electrical testing of two OE-VLSI ASICs. The experiences obtained during the design and test of these ASICs, in conjunction with further analytical and simulation-based analyses, resulted in the conclusion that a fully differential optical and electrical architecture is optimal for OE-VLSI applications. The remainder of the thesis considers receiver and transmitter testing and the integration of testing methodologies at the ASIC level, and the management of skew in large receiver arrays.

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Gilda, Shubham. "ASIC design to monitor current for low frequency applications." University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1291390501.

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DUTTA, MADHULIKA. "DESIGN OF AN INTEGRATED DETECTION SYSTEM FOR THE CHARACTERIZATION OF A BIOSENSOR ARRAY." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1054128572.

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Auras, Dominik [Verfasser], Gerd [Akademischer Betreuer] Ascheid, and Andreas [Akademischer Betreuer] Burg. "MIMO Detector ASIC Design / Dominik Auras ; Gerd Ascheid, Andreas Burg." Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://d-nb.info/116249963X/34.

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Zaveri, Jainish K. "Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology." DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1940.

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Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These devices generally use small solid state or thin film batteries for power supply which need replacement or need to be removed for charging. RF energy harvesting technology can be used to charge these batteries without the need to remove the battery from the device, thus providing a sustainable power supply. In other cases, a battery can become unnecessary altogether. This enables us to deploy wireless network nodes in places where regular physical access to the nodes is difficult or cumbersome. This thesis proposes a design of an RF energy harvesting device able to charge commercially available thin film or solid-state batteries. The energy harvesting amplifier circuit is designed in Global Foundry 0.13um CMOS technology using Cadence integrated circuit design tools. This Application Specific Integrated Circuit (ASIC) is intended to have as small a footprint as possible so that it can be easily integrated with the above-mentioned devices. While a dedicated RF power source is a direct solution to provide sustainable power to the harvesting circuit, harvesting ambient RF power from TV and UHF cellular frequencies increases the possibilities of where the harvesting device can be placed. The biggest challenge for RF energy harvesting technology is the availability of adequate amount of RF power. This thesis also presents a survey of available RF power at various ultra-high frequencies in San Luis Obispo, CA.The idea is to determine the frequency band which can provide maximum RF power for harvesting and design a harvester for that frequency band.

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Mehrez, Fatima. "Design and test of a readout ASIC for a SiPM - based camera : ALPS (ASIC de lecture pour un photodétecteur SiPM)." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT131/document.

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Cette thèse est la R&D de l’électronique de front-end destinée à la camera de deuxième génération du télescope de grande taille LST de projet CTA, étant basée sur les détecteurs de type SiPM. Cette étude rassemble des équipes du LAPP, de l’université de Padoue, de l’INFN et du MPI de Munich. La première partie de cette thèse porte sur les tests de caractérisations d’une matrice de 16 SiPMs fabriquée par Hamamatsu. Les résultats de ces tests ont souligné les avantages qui pourraient être apportés par l’utilisation de tels détecteurs. Un cahier des charges pour l’électronique a été défini à l’issue de ces tests. Notamment, une nécessité de corriger la dispersion en gain entre les 16 pixels qui a été trouvée d’environ 10%. La seconde partie est la conception d’un circuit intégré (ASIC) qui pourrait lire les signaux des pixels -SiPM avec la moindre perturbation possible de fonctionnement du détecteur. Cet ASIC inclut des fonctions de contrôle (slow control) qui permettent l’ajustement de gain des pixels, l’amélioration de l’uniformité de gain et la possibilité de supprimer les canaux bruyants ou encore même le contournement du processus de contrôle de gain. Ces fonctionnalités peuvent unifier le gain de 16 canaux. Les sorties des 16 canaux seront sommées pour en faire deux signaux seulement à la sortie de l’ASIC. Ces deux signaux, un sur le haut gain et l’autre sur le bas gain seront fournis au système d’acquisition qui suivra l’ASIC. Une fonction de déclenchement génèrera un signal de trigger qui sera ainsi transmis au système d’acquisition. Cet ASIC a été réalisée avec la technologie AMS 0.35um BiCMOS. Les simulations ont montré une gamme dynamique linéairement couverte jusqu’à 2000 photoélectrons et la possibilité de mesurer le photoélectron unique grâce au bon rapport signal sur bruit électronique. Les tests au laboratoire confirment une grande partie de ces résultats<br>This thesis is the R&D on front-end electronics for a second generation camera based on the SiPM detectors for the Large Size Telescope (LST) of the CTA project. It is a part of the SiPM collaboration involving the LAPP, the University of Padua, the INFN and the MPI in Munich. The first part of the thesis is the characterization of an array of 16 SiPMs from Hamamatsu. The study proves the advantages of using such detectors in the LST. It defines the specifications of the readout electronics that are the aim of this work. Especially that it should ameliorate the gain dispersion of the 16 pixels that was found of about 10%. The second part is the design of the readout ASIC. The scheme tends to measure the SiPMs’ signals with minimum disturbance of the detector. It integrates slow control facilities that adjust the detector’s gain, minimize the dispersion in gain and provide the possibility of deleting noisy channels or even completely jumping over the control process. These facilities could perfectly get rid of the gain dispersion. Outputs of the 16 pixels will be summed on both high gain and low gain so that only two signals are delivered to the acquisition system that follows. A trigger function will also generate a trigger signal to the acquisition system. The choice was made to realize this ASIC according to the rules of the AMS 0.35um BiCMOS technology. Simulation shows a linearly-covered dynamic range up to 2000 photoelectrons with good signal to noise ratio that allows the measurement of the single photoelectron. Laboratory tests confirm a great part of these results

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Djigbenou, Jeannette Donan. "Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development." Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/32269.

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Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers shorter design time, induces fewer errors in the design process, and is easier to maintain. Development of a cell library is laborious, prone to errors and even a small error on a library cell can possibly be disastrous due to repeated use of the cell in a design. In this thesis, we investigated ways to automate the process for development of a cell library, specifically TSMC 0.18-micron CMOS standard cell library. We examined various steps in the design flow to identify required repetitive tasks for individual cells. Those steps include physical verification, netlist extraction, cell characterization, and generation of Synopsys Liberty Format file. We developed necessary scripts in Skill, Tcl, Perl and Shell to automate those steps. Additionally, we developed scripts to automate the quality assurance process of the cell library, where quality assurance consists of verifying the entire ASIC design flow adopted for the Virginia Tech VLSI Telecommunications (VTVT) lab. Our scripts have been successfully used to develop our TSMC 0.18-micron library and to verify the quality assurance. The first version of the cell library was released on November 1, 2007 to universities worldwide, and as of March 2008, 20 universities have received the library from us.<br>Master of Science

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Books on the topic "ASIC design"

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Hoppe, Bernhard. ASIC-Design. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-642-59818-0.

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Taraate, Vaibbhav. ASIC Design and Synthesis. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-4642-0.

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1934-, Trontelj Lojze, and Shenton Graham 1939-, eds. Analog digital ASIC design. McGraw-Hill, 1989.

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Mehta, Ashok B. ASIC/SoC Functional Design Verification. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-59418-7.

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Romdhane, Mohamed S. Ben, Vijay K. Madisetti, and John W. Hines, eds. Quick-Turnaround ASIC Design in VHDL. Springer US, 1996. http://dx.doi.org/10.1007/978-1-4613-1411-0.

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High-performance ASIC design: Using synthesizable domino logic in an ASIC flow. Cambridge University Press, 2008.

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Leung, Steven S., and Michael A. Shanblatt. ASIC System Design with VHDL: A Paradigm. Springer US, 1989. http://dx.doi.org/10.1007/978-1-4615-6473-7.

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Huber, John P., and Mark W. Rosneck. Successful ASIC Design the First Time Through. Springer US, 1991. http://dx.doi.org/10.1007/978-1-4684-7885-3.

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Huber, John P. Successful ASIC design the first time through. Van Nostrand Reinhold, 1991.

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1952-, Shanblatt Michael A., ed. ASIC system design with VHDL: A paradigm. Kluwer Academic Publishers, 1989.

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Book chapters on the topic "ASIC design"

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Chandrasetty, Vikram Arkalgud. "ASIC Design." In VLSI Design. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-1120-8_3.

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Buffa, Cesare. "ASIC Design." In MEMS Lorentz Force Magnetometers. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-59412-5_9.

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Taraate, Vaibbhav. "ASIC Design." In Digital Logic Design Using Verilog. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-3199-3_18.

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Hope, Bernhard. "Der ASIC-Entwurfsprozeß." In ASIC-Design. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-642-59818-0_3.

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Hope, Bernhard. "Einleitung." In ASIC-Design. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-642-59818-0_1.

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Hope, Bernhard. "Schaltplan- und Symbolerstellung mit DESIGN ARCHITECT." In ASIC-Design. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-642-59818-0_10.

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Hope, Bernhard. "Digital- und Analogsimulation mit QUICKSIMII und ACCUSIM." In ASIC-Design. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-642-59818-0_11.

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Hope, Bernhard. "Automatische Layouterstellung mit ICStation." In ASIC-Design. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-642-59818-0_12.

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Hope, Bernhard. "Konzepte, Technologien und Realisierungstechniken." In ASIC-Design. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-642-59818-0_2.

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Hope, Bernhard. "Transistortheorie und Schaltungstechnik." In ASIC-Design. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-642-59818-0_4.

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Conference papers on the topic "ASIC design"

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Gabriele Saucier. "Tutorial: ASIC Prototyping." In 32nd Design Automation Conference. ACM, 1995. http://dx.doi.org/10.1109/dac.1995.249978.

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Chinnery, D. G., and K. Keutzer. "Closing the power gap between ASIC and custom: an ASIC perspective." In 2005 42nd Design Automation Conference. IEEE, 2005. http://dx.doi.org/10.1109/dac.2005.193816.

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Chong, Ang Boon. "ASIC design margin methodology." In 2013 IEEE TENCON Spring Conference. IEEE, 2013. http://dx.doi.org/10.1109/tenconspring.2013.6584434.

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"About ASIC Technologies." In 2022 International Conference on IC Design and Technology (ICICDT). IEEE, 2022. http://dx.doi.org/10.1109/icicdt56182.2022.9933090.

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Baek, Donkyu, Insup Shin, Seungwhun Paik, and Youngsoo Shin. "Selectively patterned masks: Structured ASIC with asymptotically ASIC performance." In 2011 16th Asia and South Pacific Design Automation Conference ASP-DAC 2011. IEEE, 2011. http://dx.doi.org/10.1109/aspdac.2011.5722217.

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Auras, Dominik, Sebastian Birke, Tobias Piwczyk, Rainer Leupers, and Gerd Ascheid. "A flexible MCMC detector ASIC." In 2016 International SoC Design Conference (ISOCC). IEEE, 2016. http://dx.doi.org/10.1109/isocc.2016.7799789.

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Santarini, M., and S. Jilla. "Panel: whither (or wither?) ASIC handoff?" In Proceedings of 39th Design Automation Conference. IEEE, 2002. http://dx.doi.org/10.1109/dac.2002.1012642.

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Deevy, K. "Algorithmic ADC for use in ASIC design." In Euro ASIC '91. IEEE Comput. Soc. Press, 1991. http://dx.doi.org/10.1109/euasic.1991.212899.

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Baek, Donkyu, Insup Shin, Seungwhun Paik, and Youngsoo Shin. "Selectively patterned masks: Beyond structured ASIC." In 2010 International SoC Design Conference (ISOCC 2010). IEEE, 2010. http://dx.doi.org/10.1109/socdc.2010.5682950.

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Assaf, Mansour H., Sunil R. Das, Wael Hermas, and Wen B. Jone. "Promising Complex ASIC Design Verification Methodology." In 2007 IEEE Instrumentation and Measurement Technology Conference. IEEE, 2007. http://dx.doi.org/10.1109/imtc.2007.379056.

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Reports on the topic "ASIC design"

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Robertson, Perry J., Lyndon George Pierson, and Edward L. Witzke. Data encryption standard ASIC design and development report. Office of Scientific and Technical Information (OSTI), 2003. http://dx.doi.org/10.2172/918309.

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Nguyen, Du Van. An ASIC Power Analysis System for Digital CMOS Design. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.7249.

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Simoneau, A., J. Pizarro, and A. Parker. Experimental High Speed/Power Ratio ASIC Designs Using Residue Numbers. Defense Technical Information Center, 1990. http://dx.doi.org/10.21236/ada220302.

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Neely, J., M. Heroux, and S. Swaminarayan. ASC Co-design Proxy App Strategy. Office of Scientific and Technical Information (OSTI), 2012. http://dx.doi.org/10.2172/1055856.

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Hornung, Rich, Holger Jones, Jeff Keasler, et al. ASC Tri-lab Co-design Level 2 Milestone Report 2015. Office of Scientific and Technical Information (OSTI), 2015. http://dx.doi.org/10.2172/1240955.

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Gupta, Manavi, Avinash Kishore, Samuel Scott, Shreya Chakraborty, Prakashan Veettil Chellattan, and Samira Choudhury. Understanding local food systems in South Asia: An assessment approach and design. International Food Policy Research Institute, 2022. http://dx.doi.org/10.2499/p15738coll2.136543.

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Yoon, Seok Yong, Thilo Zelt, and Ulf Narloch. Smart City Pathways for Developing Asia: An Analytical Framework and Guidance. Asian Development Bank, 2021. http://dx.doi.org/10.22617/wps200342-2.

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The strategic use of digital technologies can enable smart cities to provide more accessible and better quality urban services for citizens, businesses, and governments. This working paper offers an analytical framework to assess, design, and implement smart city concepts that apply digital technologies tailored to specific contexts. It is intended to guide smart city practitioners and decision-makers in developing Asia to enhance their advisory services, project planning and implementation, and stakeholder engagement efforts.

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Bouldin, Don. CHAMPION: A Software Design Environment for Adaptive Computing Systems and Application Specific Integrated Circuits (ASICs). Defense Technical Information Center, 2001. http://dx.doi.org/10.21236/ada397938.

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Jonassen, Rachael, Mikael Skou Andersen, Jacqueline Cottrell, and Sandeep Bhattacharya. Carbon Pricing and Fossil Fuel Subsidy Rationalization Tool Kit. Asian Development Bank, 2023. http://dx.doi.org/10.22617/tim230241.

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This tool kit offers a step-by-step guide for economies in Asia and the Pacific looking to design, build, and implement emission trading systems (ETS) to help speed up their transition to a greener, more inclusive future. Using case studies to illustrate best practices and lessons learned by countries including Viet Nam and India, it explains the need to design robust legal frameworks before setting up ETSs. It outlines carbon taxes, analyzes fossil fuel subsidy rationalization, and shows why securing support from stakeholders is key for countries planning to implement ETS programs to help meet their climate targets.

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Tian, Shu. Primer on Social Bonds and Recent Developments in Asia. Asian Development Bank, 2021. http://dx.doi.org/10.22617/spr210045-2.

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Innovative financial instruments to support more inclusive development have emerged in recent years. These include social bonds designed to raise proceeds for projects with positive social outcomes. Social bonds can help Asia meet its long-term objectives in line with the Sustainable Development Goals and also facilitate the transition to a more inclusive economic recovery from the coronavirus disease (COVID-19). This publication explains why social bond market development is vital to financing the sustainable recovery of Asia from the pandemic. It also outlines salient barriers to social bond market development in the region and potential solutions to overcome them.

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