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Lothian, Angus, Ivar Härnqvist, Adam Jakobsson, Arvid Westerlund, Felix Goding, Jacob Wahlman, Kevin Scott, and Rasmus Karlsson. "B-ASIC - Better ASIC Toolbox : En verktygslåda som förenklar design och optimering av ASIC." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-167069.
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Denna rapport behandlar ett arbete skriven av åtta studenter som läste kursen TDDD96 Kandidatprojekt i programvaruutveckling vid Linköpings universitet under vårterminen 2020. Projektets syfte var att utveckla en verktygslåda i Python och C++ för att konstruera signalbehandlade kretsar. Denna verktygslåda är tänkt att användas inom laborationer i kursen TSTE87 Applikationsspecfika integrerande kretsar vid Linköpings universitet och inom forskning för utveckling av ASIC:s. Projektet resulterade i produkten B-ASIC. B-ASIC är ett bibliotek för programmeringsspråket Python som är skrivet i Python med en underliggande modul i C++. B-ASIC används för design och optimering av ASIC:s. Produkten B-ASIC erbjuder ett grafiskt användargränssnitt där användaren kan interagera med biblioteket utan programmeringskunskaper inom Python. I rapporten beskrivs hur projektarbetet har anpassats för att vara till värde för kunden och hur utvecklingsprocessen har påverkat resultatet av produkten. Projektmedlemmarna har dessutom genomfört egna undersökningar och dessa finns att läsa i slutet av rapporten.
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Ehliar, Andreas. "Performance driven FPGA design with an ASIC perspective." Doctoral thesis, Linköpings universitet, Datorteknik, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16372.
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FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient. This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA. Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA. The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated. All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs. Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.
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Han, Tony. "SWASAD Smith & Waterman-algorithm-specific ASIC design /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16391.pdf.
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Venditti, Michael B. "Receiver, transmitter, and ASIC design for optoelectronic-VLSI applications." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=84444.
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In modern digital systems, off-chip and intra-chip electrical interconnections suffer from a multitude of limitations as integrated circuits (ICs) continue to grow in size and processing capacity. Optical interconnects are capable of meeting the increasing I/O bandwidth needs in these systems. Optoelectronic-VLSI (OE-VLSI) technology incorporates optical I/O with ICs through the integration of arrays of optoelectronic devices with on-chip receiver and transmitter circuits. These optical I/Os are intended to replace or complement electrical interconnects for off-chip connections, and for connections between processing modules on the same chip or in a multi-chip module.The design of receivers, transmitters, and OE-VLSI application-specific integrated circuits (ASICs) are described from a system implementation perspective. Numerous techniques to overcome technological problems and allow the successful operation of large receiver and transmitter arrays are considered. The use of a fully differential optical and electrical architecture is strongly advocated. The testing of receiver and transmitter circuits and skew in highly parallel and synchronous digital systems employing optical receivers is also considered.
The major portion of this thesis details the design, construction, and optical and electrical testing of two OE-VLSI ASICs. The experiences obtained during the design and test of these ASICs, in conjunction with further analytical and simulation-based analyses, resulted in the conclusion that a fully differential optical and electrical architecture is optimal for OE-VLSI applications. The remainder of the thesis considers receiver and transmitter testing and the integration of testing methodologies at the ASIC level, and the management of skew in large receiver arrays.
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Gilda, Shubham. "ASIC design to monitor current for low frequency applications." University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1291390501.
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DUTTA, MADHULIKA. "DESIGN OF AN INTEGRATED DETECTION SYSTEM FOR THE CHARACTERIZATION OF A BIOSENSOR ARRAY." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1054128572.
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Auras, Dominik [Verfasser], Gerd [Akademischer Betreuer] Ascheid, and Andreas [Akademischer Betreuer] Burg. "MIMO Detector ASIC Design / Dominik Auras ; Gerd Ascheid, Andreas Burg." Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://d-nb.info/116249963X/34.
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Zaveri, Jainish K. "Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology." DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1940.
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Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These devices generally use small solid state or thin film batteries for power supply which need replacement or need to be removed for charging. RF energy harvesting technology can be used to charge these batteries without the need to remove the battery from the device, thus providing a sustainable power supply. In other cases, a battery can become unnecessary altogether. This enables us to deploy wireless network nodes in places where regular physical access to the nodes is difficult or cumbersome.
This thesis proposes a design of an RF energy harvesting device able to charge commercially available thin film or solid-state batteries. The energy harvesting amplifier circuit is designed in Global Foundry 0.13um CMOS technology using Cadence integrated circuit design tools. This Application Specific Integrated Circuit (ASIC) is intended to have as small a footprint as possible so that it can be easily integrated with the above-mentioned devices. While a dedicated RF power source is a direct solution to provide sustainable power to the harvesting circuit, harvesting ambient RF power from TV and UHF cellular frequencies increases the possibilities of where the harvesting device can be placed. The biggest challenge for RF energy harvesting technology is the availability of adequate amount of RF power. This thesis also presents a survey of available RF power at various ultra-high frequencies in San Luis Obispo, CA.The idea is to determine the frequency band which can provide maximum RF power for harvesting and design a harvester for that frequency band.
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Mehrez, Fatima. "Design and test of a readout ASIC for a SiPM - based camera : ALPS (ASIC de lecture pour un photodétecteur SiPM)." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT131/document.
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Cette thèse est la R&D de l’électronique de front-end destinée à la camera de deuxième génération du télescope de grande taille LST de projet CTA, étant basée sur les détecteurs de type SiPM. Cette étude rassemble des équipes du LAPP, de l’université de Padoue, de l’INFN et du MPI de Munich. La première partie de cette thèse porte sur les tests de caractérisations d’une matrice de 16 SiPMs fabriquée par Hamamatsu. Les résultats de ces tests ont souligné les avantages qui pourraient être apportés par l’utilisation de tels détecteurs. Un cahier des charges pour l’électronique a été défini à l’issue de ces tests. Notamment, une nécessité de corriger la dispersion en gain entre les 16 pixels qui a été trouvée d’environ 10%. La seconde partie est la conception d’un circuit intégré (ASIC) qui pourrait lire les signaux des pixels -SiPM avec la moindre perturbation possible de fonctionnement du détecteur. Cet ASIC inclut des fonctions de contrôle (slow control) qui permettent l’ajustement de gain des pixels, l’amélioration de l’uniformité de gain et la possibilité de supprimer les canaux bruyants ou encore même le contournement du processus de contrôle de gain. Ces fonctionnalités peuvent unifier le gain de 16 canaux. Les sorties des 16 canaux seront sommées pour en faire deux signaux seulement à la sortie de l’ASIC. Ces deux signaux, un sur le haut gain et l’autre sur le bas gain seront fournis au système d’acquisition qui suivra l’ASIC. Une fonction de déclenchement génèrera un signal de trigger qui sera ainsi transmis au système d’acquisition. Cet ASIC a été réalisée avec la technologie AMS 0.35um BiCMOS. Les simulations ont montré une gamme dynamique linéairement couverte jusqu’à 2000 photoélectrons et la possibilité de mesurer le photoélectron unique grâce au bon rapport signal sur bruit électronique. Les tests au laboratoire confirment une grande partie de ces résultatsThis thesis is the R&D on front-end electronics for a second generation camera based on the SiPM detectors for the Large Size Telescope (LST) of the CTA project. It is a part of the SiPM collaboration involving the LAPP, the University of Padua, the INFN and the MPI in Munich. The first part of the thesis is the characterization of an array of 16 SiPMs from Hamamatsu. The study proves the advantages of using such detectors in the LST. It defines the specifications of the readout electronics that are the aim of this work. Especially that it should ameliorate the gain dispersion of the 16 pixels that was found of about 10%. The second part is the design of the readout ASIC. The scheme tends to measure the SiPMs’ signals with minimum disturbance of the detector. It integrates slow control facilities that adjust the detector’s gain, minimize the dispersion in gain and provide the possibility of deleting noisy channels or even completely jumping over the control process. These facilities could perfectly get rid of the gain dispersion. Outputs of the 16 pixels will be summed on both high gain and low gain so that only two signals are delivered to the acquisition system that follows. A trigger function will also generate a trigger signal to the acquisition system. The choice was made to realize this ASIC according to the rules of the AMS 0.35um BiCMOS technology. Simulation shows a linearly-covered dynamic range up to 2000 photoelectrons with good signal to noise ratio that allows the measurement of the single photoelectron. Laboratory tests confirm a great part of these results
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Djigbenou, Jeannette Donan. "Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development." Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/32269.
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Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers shorter design time, induces fewer errors in the design process, and is easier to maintain.
Development of a cell library is laborious, prone to errors and even a small error on a library cell can possibly be disastrous due to repeated use of the cell in a design. In this thesis, we investigated ways to automate the process for development of a cell library, specifically TSMC 0.18-micron CMOS standard cell library. We examined various steps in the design flow to identify required repetitive tasks for individual cells. Those steps include physical verification, netlist extraction, cell characterization, and generation of Synopsys Liberty Format file. We developed necessary scripts in Skill, Tcl, Perl and Shell to automate those steps. Additionally, we developed scripts to automate the quality assurance process of the cell library, where quality assurance consists of verifying the entire ASIC design flow adopted for the Virginia Tech VLSI Telecommunications (VTVT) lab. Our scripts have been successfully used to develop our TSMC 0.18-micron library and to verify the quality assurance. The first version of the cell library was released on November 1, 2007 to universities worldwide, and as of March 2008, 20 universities have received the library from us.Master of Science
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Mahnke, Torsten. "Low power ASIC design using voltage scaling at the logic level." [S.l. : s.n.], 2003. http://deposit.ddb.de/cgi-bin/dokserv?idn=970311974.
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Classon, Viktor. "Low Power Design Using RNS." Thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-110176.
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Power dissipation has become one of the major limiting factors in the design of digital ASICs. Low power dissipation will increase the mobility of the ASIC by reducing the system cost, size and weight. DSP blocks are a major source of power dissipation in modern ASICs. The residue number system (RNS) has, for a long time, been proposed as an alternative to the regular two's complement number system (TCS) in DSP applications to reduce the power dissipation. The basic concept of RNS is to first encode the input data into several smaller independent residues. The computational operations are then performed in parallel and the results are eventually decoded back to the original number system. Due to the inherent parallelism of the residue arithmetics, hardware implementation results in multiple smaller design units. Therefore an RNS design requires low leakage power cells and will result in a lower switching activity. The residue number system has been analyzed by first investigating different implementations of RNS adders and multipliers (which are the basic arithmetic functions in a DSP system) and then deriving an optimal combination of these. The optimum combinations have been used to implement an FIR filter in RNS that has been compared with a TCS FIR filter. By providing different input data and coefficients to both the RNS and TCS FIR filter an evaluation of their respective performance in terms of area, power and operating frequency have been performed. The result is promising for uniform distributed random input data with approximately 15 % reduction of average power with RNS compared to TCS. For a realistic DSP application with normally distributed input data, the power reduction is negligible for practical purposes.
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Munugala, Anvesh. "An 8 bit Serial Communication module Chip Design Using Synopsys tools and ASIC Design Flow Methodology." Youngstown State University / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ysu152703879322399.
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Balasingam, Naveendran. "Modular, Configurable Bus Architecture for Ease of IP Reuse on System on Chip and ASIC Devices." PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/163.
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Integrated Circuit (IC) designs are increasingly moving towards Intellectual Property (IP) reuse for various targeted products and market segments. Therefore, there is a need to share and synergize internal bus architectures to enable the reuse of IP blocks for various ASIC and SoC applications. Due to the different market segments of various ASICs and SoCs, design teams and architects have opted to use customized internal bus architectures to suit the respective targeted features for their market segments. As a result, many ASIC and SoC companies that produce microprocessors for computers, microcontrollers for consumer electronics as well as memory and I/O controller chipsets have opted to use different internal interfaces, designs and IPs for the different products that they sell. A modular and configurable bus architecture that is flexible and capable of supporting IPs from various ASICs and SoCs would serve to solve many of the problems relating to IP reuse for various applications from a front end design perspective. There are several approaches to resolve this, for example, using a standard existing open source bus, a new all-encompassing bus that covers the needs of the majority of designs and a customization of a particular bus level such as the interface layer, where part of the bus features are fixed and the rest of them are determined by individual design groups. This research covers the analysis of existing bus architectures in industry and considers the various options for bus architecture optimization for design modularity, bus performance and IP reuse with existing technology. The architecture definition, design, logic simulation and performance comparisons of the proposed bus architecture on industry standard RTL design and validation tools was then conducted.
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Alfredsson, Erik. "Design and implementation of a hardware unit for complex division." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5427.
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The purpose of the thesis was to investigate and evaluate existing algorithms for division of complex numbers. The investigation should include implementation of a few suitable algorithms in VHDL. The main application for the divider is compensation for fading in a baseband processor.
Since not much public research is done within the area of complex division in hardware, a divider based on real valued division was designed. The design only implements inversion of complex numbers instead of complete division because it is simpler and the application does not need full division, thus the required chip size is reduced.
An examination of the different kinds of algorithms that exists for real valued division was done and two of the methods were found suitable for implementation, digit recurrence and functional iteration. From each of the two classes of algorithms one algorithm was chosen and implemented in VHDL. Two different versions of the inverter were designed for each method, one with full throughput and one with half throughput. The implementations show very similar results in terms of speed, size and performance. For most cases however, the digit recurrence implementation has a slight advantage.
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Ren, Beibei. "A domain-specific cell based asic design methodology for digital signal processing applications /." Diss., Digital Dissertations Database. Restricted to UC campuses, 2005. http://uclibs.org/PID/11984.
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Kalala, Srivatsa. "Timing and Placement Optimization for Segmented Bus Architectures for Low Power ASIC Design." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1137005658.
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Li, Kwing Kwan Carleton University Dissertation Engineering Electrical. "Analysis of an asic design package via the implementation of an echo canceller." Ottawa, 1990.
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Toreyin, Hakan. "Design of a low-power interface circuitry for a vestibular prosthesis system." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/54018.
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The human vestibular system is responsible for maintaining balance and orientation, and stabilizing gaze during head motion. Head motion is sensed by vestibular sensors and encoded via the firing rate of vestibular neurons. Vestibular disorders can result in dizziness, imbalance, and disequilibrium. Currently there are no therapeutic options for individuals suffering from bilateral vestibular dysfunction. A potential solution is a vestibular prosthesis (VP). This device serves to replace peripheral vestibular organs by sensing angular motion, detected by semicircular canals (SCCs), and linear head motion, detected by the otolith organs, and selectively stimulating the corresponding vestibular afferents. An ideal VP will not only mimic the patient-dependent vestibular neural dynamics, but also consume low power. In this study, three energy-efficient ways to implement the motion encoding function required in a vestibular prosthesis are presented. Both analog and digital signal processing techniques to implement the vestibular signal processing functions are investigated.
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COSSIO, FABIO. "A mixed-signal ASIC for time and charge measurements with GEM detectors." Doctoral thesis, Politecnico di Torino, 2019. http://hdl.handle.net/11583/2743335.
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Sistla, Anil Kumar. "Design Space Exploration of Domain Specific CGRAs Using Crowd-sourcing." Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc699959/.
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CGRAs (coarse grained reconfigurable array architectures) try to fill the gap between FPGAs and ASICs. Over three decades, the research towards CGRA design has produced number of architectures. Each of these designs lie at different points on a line drawn between FPGAs and ASICs, depending on the tradeoffs and design choices made during the design of architectures. Thus, design space exploration (DSE) takes a very important role in the circuit design process. In this work I propose the design space exploration of CGRAs can be done quickly and efficiently through crowd-sourcing and a game driven approach based on an interactive mapping game UNTANGLED and a design environment called SmartBricks. Both UNTANGLED and SmartBricks have been developed by our research team at Reconfigurable Computing Lab, UNT. I present the results of design space exploration of domain-specific reconfigurable architectures and compare the results comparing stripe vs mesh style, heterogeneous vs homogeneous. I also compare the results obtained from different interconnection topologies in mesh. These results show that this approach offers quick DSE for designers and also provides low power architectures for a suite of benchmarks. All results were obtained using standard cell ASICs with 90 nm process.
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Walsh, Declan. "Design and implementation of massively parallel fine-grained processor arrays." Thesis, University of Manchester, 2015. https://www.research.manchester.ac.uk/portal/en/theses/design-and-implementation-of-massively-parallel-finegrained-processor-arrays(e0e03bd5-4feb-4d66-8d4b-0e057684e498).html.
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This thesis investigates the use of massively parallel fine-grained processor arrays to increase computational performance. As processors move towards multi-core processing, more energy-efficient processors can be designed by increasing the number of processor cores on a single chip rather than increasing the clock frequency of a single processor. This can be done by making processor cores less complex, but increasing the number of processor cores on a chip. Using this philosophy, a processor core can be reduced in complexity, area, and speed to form a very small processor which can still perform basic arithmetic operations. Due to the small area occupation this can be multiplied and scaled to form a large scale parallel processor array to offer a significant performance. Following this design methodology, two fine-grained parallel processor arrays are designed which aim to achieve a small area occupation with each individual processor so that a larger array can be implemented over a given area. To demonstrate scalability and performance, SIMD parallel processor array is designed for implementation on an FPGA where each processor can be implemented using four ‘slices’ of a Xilinx FPGA. With such small area utilization, a large fine-grained processor can be implemented on these FPGAs. A 32 × 32 processor array is implemented and fast processing demonstrated using image processing tasks. An event-driven MIMD parallel processor array is also designed which occupies a small amount of area and can be scaled up to form much larger arrays. The event-driven approach allows the processor to enter an idle mode when no events are occurring local to the processor, reducing power consumption. The processor can switch to operational mode when events are detected. The processor core is designed with a multi-bit data path and ALU and contains its own instruction memory making the array a multi-core processor array. With area occupation of primary concern, the processor is relatively simple and connects with its four nearest direct neighbours. A small 8 × 8 prototype chip is implemented in a 65 nm CMOS technology process which can operate at a clock frequency of 80 MHz and offer a peak performance of 5.12 GOPS which can be scaled up to larger arrays. An application of the event-driven processor array is demonstrated using a simulation model of the processor. An event-driven algorithm is demonstrated to perform distributed control of distributed manipulator simulator by separating objects based on their physical properties.
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Ramasamy, Lakshminarayanan. "First Order Mobility Independent ASIC for a Point-of-Care In-Vitro Diagnostic Device." University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1326296847.
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Yu, Zhengtao. "Rotary clock based high-frequency ASIC design methodology." 2007. http://www.lib.ncsu.edu/theses/available/etd-10252007-214239/.
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Hsiao, Yi-Mao, and 蕭詣懋. "High Speed ASIC Design for IPv6 Routing Lookup." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/29901660472776506666.
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碩士國立中正大學
電機工程所
94
For the IP-based network today, there are three main issues of router design— link speed, router performance, and routing lookup. Routing lookup is a bottleneck inside a router. With the growth of Internet users and services, IP address has been exhaustedly used. In order to solve this problem of exhaustion, the quick solution like CIDR is presented, and the future will be IPv6. In this paper, a routing lookup system for IPv6 is presented. The system is composed of routing lookup ASIC and off-chip memory set. The off-chip memory set is a two-level hierarchical memory architecture. 91.89% routing entries of the routing table can be searched in one memory access, and the worst case about 10% in this system is two-memory accesses .The ASIC includes a function unit and a Binary CAM . The Binary CAM is used as cache memory with FIFO replacement algorithm .There are 1024 cache entries in the CAM with 80% hit ratio. The routing lookup system approaches 160Mlps (81.92Gb/s), and now it has overwhelmed the basic necessity. In the future, the bigger requirement will be available. In the system, routing table only needs 20.04KB TCAM, 10.24KB BCAM, and 29.29MB SRAM for a 150000 entries.
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Sun, Jian-Ming, and 孫建明. "Grey Prediction Based Motion Estimation:Algorithm and ASIC Design." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/26865131530907984354.
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碩士國立成功大學
電機工程學系
86
Video compression is becoming increasingly important with the advent of the multimedium and broadband networks. In the videocoding system, the most popular and kernel technique for dynamicvideo compression is the motion estimation (ME), and the video transmission speed depend on its performance deeply. Due to the temporal and spatial correlation of the image sequence, the motion vector of a block is highly related to the motion vectors of its adjacent blocks in the same image frame. If we can obtain useful and enough information from the adjacent motion vectors, the search times used to find the motion vector of each block may be reduced significantly. In this thesis, an efficient grey prediction search(GPS) algorithm for block motion estimation is proposed. Based on the grey system theory, the GPS can determine the motion vectors of image blocks quickly and correctly. Experimental results show that the proposed algorithm performs better than other search algorithm. In addition, the 9 PE's architecture for the algorithm is designed and implemented by using the standard-cell of COMPASS, which employ the 0.6um technology. The physical layout is generated by using CADENCE CAD tools. The core size (contained pads) is 3357.6um×3273.6um, and the gate count is about 8578. By the post-layoutsimulation, it can yield a search rate of about 1393.19×1000 blocks/sec with a clock rate of 66 MHz.
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Chang, Tso Bing, and 莊作彬. "ASIC Design of CORDIC-Based Coordinate Tranformation Processor." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/92347279987745156334.
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Chen, Sin-Yu, and 陳信宇. "A Power Gating Design Methodology for Structured ASIC." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/51514981887898646468.
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碩士元智大學
資訊工程學系
97
With the advances in integrated circuit(IC) process, IC design issues that need to be handled will be more difficult. Since a chip consists of numerous pattern formational layers, mask cost becomes very large for an advanced manufacturing process. To reduce the cost of IC design and manufacturing, structured ASIC emerges as a new design alternative. Structured ASIC consists of some prefabricated transistors and prefabricated masks for some metal layers, and a couple of un-customized mask layers for vias. The designers need only to customize a few masks to complete the design, and share the cost of prefabricated masks. As technology scales, leakage power consumption becomes a serious problem. Among the leakage power reduction methods, power gating is a commonly used technique that disconnects idle blocks from the power network. In this thesis, we design a via-configurable logic block (VCLB) that enables power gating designs and propose a structured ASIC design methodology based on power-gated VCLB. Experimental results show that the leakage power of the designs is on average 0.48 times that of the designs without using power-gating at the expense of 1.16 times delay and 1.07 times area.
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Hsu, Tsu-Jui, and 許祖瑞. "Programmable CNN LSTM ASIC Design for Biomedical Application." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/x35asn.
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碩士國立交通大學
電子研究所
107
Mobile health device is key factor for personal health care. Mobile health device can analyze user's physical well-being instantly. Mobile health device combines Artificial Intelligence, Big Data, Internet of Things, sensors, etc. It plays important role in personal health care. Unlike cloud computing, mobile health device has very limited computing resources and computing power, mobile health device needs to achieve edge computing. Edge computing requires low power and real-time computing. To achieve low power and real-time computing, we design an ASIC that can process multiple deep learning networks. Supported deep learning networks includes Convolutional Neural Network, Long Short Term Memory and Fully Connect. We also make the ASIC programmable, so that our ASIC can support different layers, kernel sizes, channel sizes for CNN and LSTM. Our ASIC achieve low power by sharing same PE among all three networks, and the main buffers used by LSTM is fully shared with FC. Under the real-time processing constrain, our ASIC can achieve 2.56 uW dynamic power and 224 uW static power, the total power is only 226.56 uW, since our ASIC is not running very fast, the clock frequency is only 3MHz, so most of power consumption is from static power. Our ASIC mainly processes PPG signal, and main application is Biometric Identification, Signal Selector, and Blood Glucose Predictor. The first two application utilize LSTM and FC networks. Blood Glucose Predictor utilize CNN, LSTM and FC. By combining these three networks, we can offer more stable and secure personal health care.
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"Architecture and design flow for a highly efficient structured ASIC." 2011. http://library.cuhk.edu.hk/record=b5894769.
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Ho, Man Ho.Thesis (M.Phil.)--Chinese University of Hong Kong, 2011.
Includes bibliographical references (p. 60-64).
Abstracts in English and Chinese.
Abstract --- p.i
Chinese Abstract --- p.iii
Acknowledgement --- p.v
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Objectives --- p.3
Chapter 1.3 --- Contributions --- p.4
Chapter 1.4 --- Thesis Organization --- p.5
Chapter 2 --- Background Study --- p.6
Chapter 2.1 --- Introduction --- p.6
Chapter 2.2 --- Architecture & Design Flows --- p.6
Chapter 2.3 --- Summary --- p.11
Chapter 3 --- Architecture --- p.14
Chapter 3.1 --- Overview --- p.14
Chapter 3.2 --- Fabric Architecture --- p.15
Chapter 3.2.1 --- Programmable Layers --- p.15
Chapter 3.2.2 --- Fabric Organization --- p.16
Chapter 3.3 --- Logic Block Designs --- p.19
Chapter 3.3.1 --- Lookup-table (LUT) Based Logic Block --- p.19
Chapter 3.3.2 --- Static CMOS Style Logic Block --- p.22
Chapter 3.4 --- Summary --- p.26
Chapter 4 --- EDA Design Flow --- p.27
Chapter 4.1 --- Overview --- p.27
Chapter 4.2 --- Library Preparation --- p.27
Chapter 4.3 --- Design Synthesis --- p.29
Chapter 4.4 --- Fabric Creation & Design Mapping Flows --- p.30
Chapter 4.5 --- Summary --- p.35
Chapter 5 --- Experimental Results --- p.36
Chapter 5.1 --- Benchmark Circuits Description --- p.36
Chapter 5.2 --- Experiment Configurations --- p.37
Chapter 5.2.1 --- Synthesis --- p.38
Chapter 5.2.2 --- Placement & Routing --- p.39
Chapter 5.3 --- Comparison Metrics --- p.40
Chapter 5.4 --- Area & Critical Path Delay Comparisons --- p.41
Chapter 5.5 --- Summary --- p.46
Chapter 6 --- Prototypes Testing --- p.47
Chapter 6.1 --- Overview --- p.47
Chapter 6.2 --- Second Tape-out --- p.47
Chapter 6.2.1 --- Sample Application --- p.48
Chapter 6.2.2 --- Signoff preparations --- p.50
Chapter 6.2.3 --- Results for Test unit --- p.51
Chapter 6.2.4 --- Functional test of Peak unit --- p.52
Chapter 6.3 --- Third Tape-out --- p.53
Chapter 6.3.1 --- Test Results . --- p.54
Chapter 7 --- Conclusion --- p.57
Chapter 7.1 --- Future Works --- p.58
Bibliography --- p.59
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Hsieh, Chih-Ho, and 謝志和. "A Microphone Array Echo Canceller and Its ASIC Design." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/01248205031132543506.
Full textAbstract:
碩士國立交通大學
電信工程研究所
86
In this thesis, a new structure for acoustic echo cancellation is presented. This echo canceller uses a microphone array to acquire speech signals. Due to the use of the microphone array, we can use a shorter adaptive FIR filter to identify the acoustic channel. We then describe the operations of the prooposed echo canceller in detail. Besides, a new approach to the detection of double - talk is proposed This is achieved by monitoring the power of the adaptive filter weight vector. Our method is very sensitive to the occurrence of double - talk and it can distinguish the room impulse response double - talk.Finally, we consider the ASIC design of the proposed echo canceller. Using the techniques of pipelining and hardware sharing, we are able to design the ASIC with a high working efficiency as well as a small chip area.
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Yeh, Zhi-Cheng, and 葉志成. "Design and Implementation of ASIC forSMTP Intrusion Prevention System." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/61526623483072497087.
Full textAbstract:
碩士國立中正大學
電機工程所
96
In the fast-growing internet applications, email becomes more and more important in communication. SMTP attacks and spam mails have become one of the most serious problems. Above 50% of all email in the internet are spam mails. Particularly, the SMTP attacks and spam mails varies on email, for example spoofing address, illegal characters, sending in bulk, too many SMTP commands and so on. A single security technique is not enough to protect the system from these attacks and spam mails. In this thesis, we propose an ASIC for SMTP Intrusion Prevention System (SIPS) which bases on the concept of Stateful Protocol Anomaly Detection and Flow-based Inspection and implemented by a finite state machine to inspect all coming email flows.
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"Methodology and design flow for metal programmable structured ASIC." 2010. http://library.cuhk.edu.hk/record=b5894369.
Full textAbstract:
Chau, Chun Pong."August 2010."
Thesis (M.Phil.)--Chinese University of Hong Kong, 2010.
Includes bibliographical references (leaves 67-71).
Abstracts in English and Chinese.
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Objectives --- p.4
Chapter 1.3 --- Contribution --- p.4
Chapter 1.4 --- Thesis Organization --- p.5
Chapter 2 --- Background and Review --- p.6
Chapter 2.1 --- Introduction --- p.6
Chapter 2.2 --- Logic Cell Style and Mask Programmability --- p.6
Chapter 2.3 --- CAD Tools Compatibility --- p.8
Chapter 2.4 --- Summary --- p.9
Chapter 3 --- Architectural Design --- p.11
Chapter 3.1 --- Overview --- p.11
Chapter 3.2 --- Programmable Layers --- p.12
Chapter 3.3 --- Combinational Logics --- p.12
Chapter 3.4 --- Sequential Logics --- p.19
Chapter 3.5 --- Inter-cell Connections --- p.21
Chapter 3.6 --- Hard Macros --- p.22
Chapter 3.7 --- Summary --- p.22
Chapter 4 --- Design Flow --- p.23
Chapter 4.1 --- Overview --- p.23
Chapter 4.2 --- Library Creation --- p.24
Chapter 4.3 --- Synthesis --- p.30
Chapter 4.4 --- Placement and Routing --- p.30
Chapter 4.5 --- Static Timing Analysis --- p.34
Chapter 4.6 --- Summary --- p.35
Chapter 5 --- Experimental Results --- p.36
Chapter 5.1 --- Benchmark Circuits Description --- p.36
Chapter 5.2 --- Experiment Settings --- p.37
Chapter 5.3 --- Ratio of Dedicated Elements --- p.42
Chapter 5.4 --- Delay and Area Comparison --- p.49
Chapter 5.5 --- Distributed Memories --- p.53
Chapter 5.6 --- Summary --- p.54
Chapter 6 --- Prototypes and Applications --- p.55
Chapter 6.1 --- Overview --- p.55
Chapter 6.2 --- First Prototype --- p.55
Chapter 6.3 --- Second Prototype --- p.63
Chapter 7 --- Conclusion --- p.65
Chapter 7.1 --- Future Work --- p.66
Chapter 7.2 --- Concluding Remark --- p.67
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Tu, Tzu-Chen, and 凃咨宸. "Design and Implementation of ASIC for Anti-collision Detection." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/m93qe9.
Full textAbstract:
碩士國立中正大學
電機工程研究所
102
Collision detection is fundamental to many varied applications, including physical simulations, robotics, solid modeling, virtual reality and etc. The goal is to determine whether two objects in three dimension space intersect or not. Even though computers today are over a thousand times faster, collision detection is a key challenge to deal with such large data sets with complicated structures and algorithms. Collision detection is limited by the execution speed of the CPU and take pre-simulation, spend a lot of time and hard to achieve real time-time detection. This theses uses collision detection algorithm to implement the triangle collision detection block on integrated circuit which needs a lot of computing in anti-collision detection system. It will be able to effectively reduce the collision detecting time to achieve real-time anti-collision detection system. This these simplifies the projection theorem and provides a strategy for selecting separating axis. It will effectively reduces the computing time for hardware design.
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SHE, CHUNG-CHI, and 佘中騏. "Design and Implementation of ASIC for Parallelizing Collision Detection." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/y2z63s.
Full textAbstract:
碩士國立中正大學
電機工程研究所
105
With the development of science and technology,automatic anti-collision system becomes more significant. Including robotic arm, virtual reality, self-driving vehicles and etc. Such as the use of automated and intelligent technology, will be applied to the anti-collision detection system. As in the three-dimensional space, The higher the precision of the building object, the greater the amount of demand for computing. Today need to judge in real time Collision, anti-collision detection is still a challenge. This theses is based on separation axis theorem and is realized on the integrated circuit. The separation axis theorem in the detection of the collision time will be unstable. In the best case, only one separation axis needs to be calculated, And the worst case, need to calculate the 11 separation axis to know whether the two objects collide. so the computing time of the separation axis theorem is regularized by the parallelization. And the overall structure of parallel, thus accelerate computing speed. In order to achieve every millisecond to test whether the two objects crash collision anti-collision detection system.
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張儀中. "ASIC design and implementation of a 2D rotational subarray." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/49521317847381938993.
Full text
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Lin, Hsin-chen, and 林信成. "ASIC Design and Implementation for VoIP Intrusion Detection /Prevention." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/07521251455768490642.
Full textAbstract:
碩士國立中正大學
電機工程所
97
With pervasion and rapid growth of Internet , the requirements of transmitting Multimedia data on IP network have become larger and larger . VoIP ( Voice over IP ) is one of killer applications in Internet , even it will replace PSTN in the future. Because of scalability、openness and simple format，SIP has become the most important signaling protocol for VoIP . Due to SIP is a plaintext format ,it will face many additional threats. Well-known antivirus software “Mcafee Avert Labs” published an article by” McAfee Avert Labs Top 10 Threat Predictions for 2008”, forecasting VoIP Vulnerabilities in 2008 than the 50 percent over 2007, and it pointed out that VoIP technology is still very progressive, but the VoIP defense strategies is lagging far behind.Therefore, the issue of VoIP security is a very serious problem. In this paper, the attack can be detected “Spoofing Attack”, “SIP Flooding Attack”, “Call Hijacking Attack” .. etc. We defense the above attack such as “Stateful Protocol Analysis”. “Stateful Protocol Analysis” most can detect abnormal behavior protocol. We increase the overall throughput for “Stateful Protocol Analysis”, so we increased Traffic Filter, it can be filter out a large number of normal packets in TCP/IP layer. And the entire VoIP IDPS (Intrusion Detection / Prevention System) to enhance the overall throughput and reached a parallel processing in ASIC.
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Cheng, Chih-Wei, and 鄭志偉. "Firmware Design under a Micro-Controller Combining ASIC Architecture." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/39906655295893124935.
Full textAbstract:
碩士國立海洋大學
電機工程學系
90
The theme of this thesis is mainly the application of the SoC (System on Chip) architecture of using a micro- controller combining an ASIC.In the CompactFlash Card there is a 8051 micro-controller and an ASIC which are responsible for monitoring host interfaces’ IDE signal transfer protocol.Besides,combining an MP3 decoder chip,an MP3 player can be implemented.In the thesis,the design and the implementation of firmware will be emphasized.
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Jafarian, Hossein. "Low-power ASIC design with integrated multiple sensor system." Thesis, 2013. http://hdl.handle.net/1805/3745.
Full textAbstract:
Indiana University-Purdue University Indianapolis (IUPUI)A novel method of power management and sequential monitoring of several sensors is proposed in this work. Application specific integrated circuits (ASICs) consisting of analog and digital sub-systems forming a system on chip (SoC) has been designed using complementary metal-oxide-semiconductor (CMOS) technology. The analog sub-system comprises the sensor-drivers that convert the input voltage variations to output pulse-frequency. The digital sub-system includes the system management unit (SMU), counter, and shift register modules. This performs the power-usagemanagement, sensor-sequence-control, and output-data-frame-generation functions. The SMU is the key unit within the digital sub-system is that enables or disables a sensor. It captures the pulse waves from a sensor for 3 clocks out of a 16-clock cycle, and transmits the signal to the counter modules. As a result, the analog sub-system is at on-state for only 3/16th fraction (18 %) of the time, leading to reduced power consumption. Three cycles is an optimal number selected for the presented design as the system is unstable with less than 3 cycles and higher clock cycles results in increased power consumption. However, the system can achieve both higher sensitivity and better stability with increased on-state clock cycles. A current-starved-ring-oscillator generates pulse waves that depend on the sensor input parameter. By counting the number of pulses of a sensor-driver in one clock cycle, a sensor input parameter is converted to digital. The digital sub-system constructs a 16-bit frame consisting of 8-bit sensor data, start and stop bits, and a parity bit. Ring oscillators that drive capacitance and resistance-based sensors use an arrangement of delay elements with two levels of control voltages. A bias unit which provides these two levels of control voltages consists of CMOS cascade current mirror to maximize voltage swing for control voltage level swings which give the oscillator wider tuning range and lower temperature induced variations. The ring oscillator was simulated separately for 250 nm and 180 nm CMOS technologies. The simulation results show that when the input voltage of the oscillator is changed by 1 V, the output frequency changes linearly by 440 MHz for 180 nm technology and 206 MHz for 250 nm technology. In a separate design, a temperature sensitive ring oscillator with symmetrical load and temperature dependent input voltage was implemented. When the temperature in the simulation model was varied from -50C to 100C the oscillator output frequency reduced by 510 MHz for the 250 nm and by 810 MHz for 180 nm CMOS technologies, respectively. The presented system does not include memory unit, thus, the captured sensor data has to be instantaneously transmitted to a remote station, e.g. end user interface. This may result in a loss of sensor data in an event of loss of communication link with the remote station. In addition, the presented design does not include transmitter and receiver modules, and thus necessitates the use of separate modules for the transfer of the data.
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Tsai, Yi-ting, and 蔡懿婷. "Design and Implementation of High-Performance Stereo Vision ASIC." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/39153022349026354280.
Full textAbstract:
碩士國立中央大學
資訊工程學系
102
Industrial inspection system or machine vision system are based on stereo vision technology, those systems requires a lot of highly complex image processing to implement their algorithms. Therefore, implementing stereo vision system with software usually needs high-efficiency processor to cope with calculating complex algorithms. And with respect to the software, embedded systems are subject to restrictions of cost and technology due to restriction on hardware resources. For this reasons, making the development of stereo vision in embedded systems is difficult to achieve. In this paper, we proposed a stereo vision embedded hardware architecture using MIAT embedded hardware design methodology. We first calculate the matching cost, and then use the minimum spanning tree algorithm to calculate disparity. After getting the depth of the image, we do disparity smoothing to significantly reduce the error rate of the object depth, which is caused by the light and shadow. The experimental results show that our system can effectively improve the accuracy of detection of the object depth, and reduce the impact of light and shadow. Our system detects moving objects’ depth in image can be stable, and won’t be affects by short-term changes of light. At last, we integrate all algorithms into a stereo vision chip, and applied to various embedded systems.
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Luo, You-Cheng, and 羅友成. "DSP Realization and ASIC Design of 3G WCDMA Baseband Receiver." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/28179751572927463620.
Full textAbstract:
碩士國立交通大學
電子工程系
90
In this thesis, DSP realization and ASIC architecture design of the baseband receiver of the third Generation Mobile Communication (Wideband Code Division Multiple Access) systems were presented. In WCDMA system, a baseband receiver includes Rake receiver, channel estimator, and code synchronization circuit. First, we simulated and analyzed the whole baseband receiver system in C language for Rake receiver, channel estimation of linear interpolation and sliding window method, and path search and tracking in code synchronization. We implement the WCDMA baseband receiver on Innovative Integration Company’s Quatro6x DSP board. Finally, the WCDMA baseband receiver architecture suitable for ASIC design is proposed. With low-power correlator design and low-complexity correlation algorithms design, the architecture can achieve a low-power consumption and high performance baseband receiver.
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Chang, Yen-Shih, and 張彥仕. "Design and Implementation of the Packet Processing and Classification ASIC." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/4u3fu6.
Full textAbstract:
碩士國立臺北科技大學
自動化科技研究所
100
There are various delays in transmission, such as processing delay, queuing delay, transmission delay, propagation delay, and so on. In these delays, this thesis aimed to reduce the processing delay. To complete this goal, the packet processing chip which includes packet analyzing, routing classification and cut-through switching mechanism to forward packet is presented. The chip not only mitigates the burden of the CPU, but also decreases the read/write delay between external memory and processing unit. First of all, verilog hardware description language is used to for the design and implement for both packet processing module and routing classification module. Notify that, the packet format is designed with a scalable architecture based on IEEE standard specification. Simulation results show that the packet length and increasing the port number don’t affect the processing delay time; and that the packet only consume forty five clock cycles from the receiver to the destination port. That is, a low latency and high throughput packet processing module is completed with Verilog HDL. Next, the simulation results need to be verified with FPGA and to calculate the latency time. All designs connect the computer from RJ45 and phy chip to send and receive real packet at Altera DE3 StratixIII. Finally, we accomplish an verification environment and integrated ASIC. We adopted TSMC 0.18-μm technology. An chip area is 1.031 × 1.021 mm2 and power consumption is 30.89 mW.
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Liang, Kai-Shiang, and 梁凱翔. "Design and Implementation of the Predictive Direct Torque Control ASIC." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/mmepuw.
Full textAbstract:
碩士國立臺北科技大學
電機工程系所
100
The thesis aims to design and implement a direct torque control (DTC) chip based on modified predictive scheme not only to decrease the ripple of the hysteresis controller but also to enhance the performance of motor controller. Verilog hardware description language (HDL) is used to implement the hardware architecture; and that an ASIC is implemented in TSMC 0.18-μm technology with cell-based design style. In general, the hysteresis controller is used in traditional direct torque control system. However, the hysteresis controller will introduce more ripple in discrect digital system. Notify that both sampling and calculating delay time contribute the ripple response which degrades the control quality in motor system. By using the predictive scheme, we can not only improve the ripple issue of the traditional direct torque control technique, but also can make the control system more stable by decreasing the time delay in hysteresis controller have been verified. After the syntax and function, the control system is implemented with the synthesis tool, the auto place & routed tool, and the function simulation tool. Finally, an ASIC is fabricated in 0.18-μm 1P6M CMOS process for three-phase induction motor control system.
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Liu, Ching-Hao, and 劉敬豪. "Design and Implementation of the Digital Filter ASIC with AMBA." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/c6mda5.
Full textAbstract:
碩士國立臺北科技大學
電機工程系研究所
102
A system on chip of AMBA(Advanced Microcontroller Bus Architecture) contains AHB(Advanced High-performance Bus) and APB(Advanced Peripheral Bus). AHB is the system bus and APB is the peripheral bus. AHB provides high-performance and multi-function transfer modes. It is applicable for high-speed devices. APB provides simple interface of the transmission and let low-power peripherals interlink. A wrapper of digital filter which can connect with AMBA is designed. Using the ARM module treats as the controller and controls the digital filter. The digital filter makes use of after the Sigma-Delta Modulator. The design uses Comb Filter and FIR Filter. It has the function of down sampling and filters out signals and quantification differences of exceeding frequency mainly. The TSMC 0.18-μm CMOS technology is selected to implement the ASIC by passing through the procedure of Synthesis、APR(Auto Place and Route)、DRC(Design Rule Check)、LVS(Layout Versus Schematic). After simulation, the proposed ASIC performs with the gate count of 60,000, the dynamic power of 7.26mW.
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Chio, Chien-Chung, and 邱健忠. "An all digital multiuser CDMA receiver and its ASIC design." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/77055168245913359247.
Full textAbstract:
碩士國立交通大學
電信工程系
89
In recent years, a class of DS-CDMA schemes has been proposed as a major candidate for the next generation digital cellular system. It is known that the capacity of a CDMA system is interference limited. This problem can be alleviated by the so called multiuser detection (MUD). In this thesis, we propose an all digital CDMA receiver for MUD. We use a two-stage partial parallel interference cancellation (PIC) algorithm for MUD as well as for code tracking. It is shown that the detection and code tracking performance can be greatly enhanced using the proposed structure. Finally, the receiver is implemented using the VHDL with a fixed-point architecture.
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Liu, Fang-Bin, and 劉芳斌. "Hardware/software selecting and scheduling for core-base ASIC design." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/84237019477805674645.
Full textAbstract:
碩士國立中正大學
資訊工程研究所
87
Recently, to speed up the design cycle at a high level for complex embedded systems has been an active research area. The efforts mainly are focused on improving time-to-market for designing application specific integrated chips subject to given constraints such as low power consumption, high performance, and minimal chip area. In the ASIC point of view, we can transform the most frequently used sub-functions of the program into hardware to increase the performance. Although this scheme may increase the chip area, on the premise of speed-up, we can achieve outstanding result. In this thesis, our goal is to develop some solution for reducing execution time and describe architecture and design flow of IP-base architecture. We focused on hardware/software selection and the methods of improve the performance. After we solve those questions, we can satisfy the user requirements.
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Huang, Yen-Lin, and 黃彥陵. "Design and Implementation of ASIC forProxy Server with TCP Splicing." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/45250154295875172727.
Full textAbstract:
碩士國立中正大學
電機工程所
97
The forwarding to be brought up of World Wide Web (WWW) to reduce the network bandwidth waste and server loading, and speed up browsing the web of reaction speed, so a trend of proxy cache server (Proxy Catching) in recent years. Proxy server play important role in the overall network performance. It is widely known that the forwarding delay of proxy’s application layer is much larger than lower layers. Because in operating system, the application layer needs to receive or send data through the TCP/IP stack and also cross the user/kernel protection boundaries. TCP Splicing is a technology to accelerate the front-end servers. It will be transferred the application layer (Layer-7 Switch) and down or moved to the TCP-IP layer. This technology can simplify the overall process, reduce the latency and processor loading to improve the overall performance. When the packet transferred , TCP Splicing have to maintain Client and Server connection status, and connect the Client-Server transferred information. When the network bandwidth development, TCP Splicing may have some bottlenecks appeared in proxy server connection with front-end or back-end. This paper primary aim TCP Splicing to provide an architecture to increase the proxy server of processing performance and support dynamic modify mapping tables based on different network connections servers. According the Back-end servers loading, TCP Splicing can convert different server for data transmission process anytime. This approach can effectively enhance performance, and effective increase the package throughput. In this research, we expects to provide a TCP Splicing for the improvement proposal.
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Chu, Wei-Cheng, and 朱偉誠. "ASIC Design of Wireless Channel Emulator and Adaptive LMS Equalizer." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/75210719408023473367.
Full textAbstract:
碩士國立清華大學
通訊工程研究所
89
The difference between wireless comm. and other comm. is that the channel of wireless comm. is wireless. From this, all the comm. systems should be designed according to channel specifics to improve performance. Otherwise, adaptive signal process methods are frequently used to estimate channel parameters. So I designed a specific integrated circuit (ASIC) which includes a channel emulator and an adaptive LMS equalizer.
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KO, YU-HSUN, and 柯佑勳. "Design and Implementation of ASIC for five-axis CNC machine." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/46398478166175176513.
Full textAbstract:
碩士國立中正大學
電機工程研究所
104
With the advancement of technology, mechanical automatic anti-collision system becomes more significant. Whether in self-driving vehicles, precision instruments, or robot etc…, will have to use this technology. Object collision or not, is mainly deter- mined by checking if two objects are intersect in three-dimensional space. Due to the huge amount of data calculation, resulting in the need of using advanced hardware to achieve real-time computing. And if you want this technology be generalized, we must make our development as fast as advanced hardware. This dissertation makes integrated circuits based on separating axis theorem. Since the algorithm requires a lot of triangles coordinate multiplication, thus reducing the triangle multiplication time is one of key point in this paper. First, we change general multiplication into cross-multiplication to reduce the size of the multiplier, so the operating frequency can be accelerated. Second, we use DI block to predict if data doesn’t have to compare. And at last, we use pipeline design to promote throughput of the design.
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Deng, An-Te. "Flexible ASIC design using the Block Data Flow Paradigm (BDFP)." 2002. http://www.lib.ncsu.edu/theses/available/etd-05152002-131155/unrestricted/etd.pdf.
Full text