Journal articles: 'ASIC design'

1

Alford, David B. "ASIC design with VHDL." ACM SIGDA Newsletter 20, no. 3 (January 22, 1991): 32–51. http://dx.doi.org/10.1145/122561.122562.

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2

Trontelj, J., and L. Trontelj. "Analog-digital ASIC design." Microelectronics Journal 21, no. 2 (January 1990): 41–51. http://dx.doi.org/10.1016/0026-2692(90)90025-x.

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3

Hasan, M. M., and Rajeev Jain. "PLA in ASIC Design." IETE Technical Review 6, no. 3 (May 1989): 237–39. http://dx.doi.org/10.1080/02564602.1989.11438479.

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4

Scarabotollo, N. "Session D2: ASIC design." Microprocessing and Microprogramming 38, no. 1-5 (September 1993): 343. http://dx.doi.org/10.1016/0165-6074(93)90164-g.

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5

Patterson, EB, PG Holmes, and D. Morley. "Microprocessor/ASIC to total ASIC design for cycloconverter drives." Microprocessors and Microsystems 14, no. 4 (May 1990): 219–26. http://dx.doi.org/10.1016/0141-9331(90)90081-6.

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6

Hamilton, S. N., and A. Orailoglu. "Efficient self-recovering ASIC design." IEEE Design & Test of Computers 15, no. 4 (1998): 25–35. http://dx.doi.org/10.1109/54.735924.

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7

Newton, A. R., and A. L. Sangiovanni-Vincentelli. "CAD tools for ASIC design." Proceedings of the IEEE 75, no. 6 (1987): 765–76. http://dx.doi.org/10.1109/proc.1987.13798.

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8

Bednar, T. R., R. A. Piro, D. W. Stout, L. Wissel, and P. S. Zuchowski. "Technology-migratable ASIC library design." IBM Journal of Research and Development 40, no. 4 (July 1996): 377–86. http://dx.doi.org/10.1147/rd.404.0377.

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Redmond, Sean. "High-level ASIC design tools." Microelectronics Journal 23, no. 3 (May 1992): 231–38. http://dx.doi.org/10.1016/0026-2692(92)90015-s.

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10

Manck, O. "Neue Schnittstellen im Asic-Design." Electrical Engineering 79, no. 2 (April 1996): 85–91. http://dx.doi.org/10.1007/bf01232916.

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11

White, Martin, Marcus D. Waller, Graham J. Dunnett, Paul F. Lister, and Richard L. Grimsdale. "Graphics ASIC design using VHDL." Computers & Graphics 19, no. 2 (March 1995): 301–8. http://dx.doi.org/10.1016/0097-8493(94)00156-s.

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12

de Geus, A. J. "Logic synthesis speeds ASIC design." IEEE Spectrum 26, no. 8 (August 1989): 27–31. http://dx.doi.org/10.1109/6.30776.

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13

Yan, XiongBo, Zheng Wang, JinFan Chang, Wei Wei, and WeiGuo Lu. "An ASIC design for LHAASO." Science China Physics, Mechanics and Astronomy 54, no. 10 (September 5, 2011): 1911–14. http://dx.doi.org/10.1007/s11433-011-4484-9.

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14

Stamenkovic, Z., V. Petrovic, and G. Schoof. "Fault-tolerant ASIC: Design and implementation." Facta universitatis - series: Electronics and Energetics 26, no. 3 (2013): 175–86. http://dx.doi.org/10.2298/fuee1303175s.

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The paper presents fault-tolerant CMOS ASICs which are immune to the single event upsets (SEU), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits and SEL protection switches (SPS) make the base for a modified fault-tolerant ASIC design flow. The proposed design flow requires the standard design automation tools and a few additional steps during logic synthesis and layout generation. An extra step is necessary to generate the redundant design net-list including voters. Other two extra steps (definition of the redundant power domains and placement of the SPS) have to be performed in the layout phase. The concept has been proven by design and implementation of the two digital circuits: shift-register and synchronous counter.

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15

Holmes, Jim, A. Matthew Francis, Ian Getreu, and Michael Glover. "A Unified ASIC and LTCC Module Design Kit for High-Temperature High-Density Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, CICMT (May 1, 2016): 000169–72. http://dx.doi.org/10.4071/2016cicmt-wp43.

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Abstract State of the art high temperature ASIC design requires the complement of high temperature modules and circuit boards. Certain LTCC tape systems have coefficients of thermal expansion that are well matched to advanced high temperature semiconductors such as SiC, making them an attractive option for low to mid-volume high temperature products. A computer aided process design kit that supports unified design of high temperature SiC ASICs and the corresponding LTCC module is presented herein. The CAD tools used in the design kit are open source and include basic features such as schematic capture layout drafting, design rule checking, and schematic to layout equivalency checking. In addition, advanced features are included such as automatic routing, automatic pad frame generation, and parasitic extraction for high-fidelity simulation. The kit also allows for the generation of a 3D mock-up rendering of the ASIC and LTCC co-design. Most importantly, pattern file generation for ASIC and LTCC manufacturing data formats is supported. Revision control is also easily accomplished, making collaboration within large design teams tractable. A 12-Volt high-temperature amplifier design using a SiC ASIC process and a compatible LTCC process is presented as a case study.

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16

Tominaga, Yoshio. "The Current Design Methodology and Some Example of ASIC." IEEJ Transactions on Electronics, Information and Systems 107, no. 12 (1987): 1094–100. http://dx.doi.org/10.1541/ieejeiss1987.107.12_1094.

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17

Suganya, G., and R. Muthaiah. "Design of Multiple Master ASIC Interconnect." Journal of Artificial Intelligence 6, no. 1 (December 15, 2012): 95–100. http://dx.doi.org/10.3923/jai.2013.95.100.

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18

Dean, Alvar, David Garrett, Mircea R. Stan, and Sebastian Ventrone. "Low Power Design for ASIC Cores." VLSI Design 12, no. 3 (January 1, 2001): 317–31. http://dx.doi.org/10.1155/2001/90464.

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A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.

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19

Leung, S. S., P. D. Fisher, and M. A. Shanblatt. "A conceptual framework for ASIC design." Proceedings of the IEEE 76, no. 7 (July 1988): 741–55. http://dx.doi.org/10.1109/5.7141.

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20

Gajanana, D., V. Gromov, and P. Timmer. "ASIC design in the KM3NeT detector." Journal of Instrumentation 8, no. 02 (February 13, 2013): C02030. http://dx.doi.org/10.1088/1748-0221/8/02/c02030.

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21

Fasang, P. P. "Analog/digital ASIC design for testability." IEEE Transactions on Industrial Electronics 36, no. 2 (May 1989): 219–26. http://dx.doi.org/10.1109/41.19072.

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22

Engel, J. J., T. S. Guzowski, A. Hunt, D. E. Lackey, L. D. Pickup, R. A. Proctor, K. Reynolds, A. M. Rincon, and D. R. Stauffer. "Design methodology for IBM ASIC products." IBM Journal of Research and Development 40, no. 4 (July 1996): 387–406. http://dx.doi.org/10.1147/rd.404.0387.

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23

Suehnel, Christoph. "ASIC design: progress in the GDR." Microprocessors and Microsystems 14, no. 8 (October 1990): 531–41. http://dx.doi.org/10.1016/0141-9331(90)90053-x.

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24

Kim, Lok-Won, Dong-U. Lee, and John Villasenor. "Automated Iterative Pipelining for ASIC Design." ACM Transactions on Design Automation of Electronic Systems 20, no. 2 (March 2, 2015): 1–24. http://dx.doi.org/10.1145/2660768.

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25

Raud, Raivo. "A language environment for asic design." Microprocessing and Microprogramming 24, no. 1-5 (August 1988): 219–26. http://dx.doi.org/10.1016/0165-6074(88)90057-9.

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26

Ali, Md Liakot, Md Shazzatur Rahman, and Fakir Sharif Hossain. "Design of a BIST implemented AES crypto-processor ASIC." PLOS ONE 16, no. 11 (November 16, 2021): e0259956. http://dx.doi.org/10.1371/journal.pone.0259956.

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This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.

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27

Andorno, M., M. Andersen, G. Borghello, A. Caratelli, D. Ceresa, J. Dhaliwal, K. Kloukinas, and R. Pejasinovic. "Rad-hard RISC-V SoC and ASIP ecosystems studies for high-energy physics applications." Journal of Instrumentation 18, no. 01 (January 1, 2023): C01018. http://dx.doi.org/10.1088/1748-0221/18/01/c01018.

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Abstract The increase in complexity and size of modern ASIC designs in the HEP community and the use of advanced semiconductor fabrication processes raises the need for a shift toward a more abstract design methodology, that takes advantage of modularity and programmability to achieve a faster turnaround time both for design and verification. This contribution will present two complementary approaches, one using a RISC-V based System-on-Chip (SoC) and the other based on Application-Specific Instruction set Processors (ASIP). The SoC uses the PicoRV32 open-source RISC-V core and a rad-hard version of the AMBA APB bus to connect peripherals and is primarily geared towards control and monitoring applications. This solution is a demonstrator of what can become a more complete fully radiation-tolerant SoC platform with a standardized interconnect and an IP block library, to serve as the starting point for future ASIC designs. The ASIP based approach targets more the design of data path elements and the use in data processing applications. The presented approach makes use of a commercial ASIP Designer EDA tool to demonstrate an integrated workflow to define, benchmark and optimize an ASIP for a specific use case, starting from a general-purpose processor.

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28

Pogra, Vivek, Amandeep Singh, Santosh Kumar Vishvakarma, and Balwinder Raj. "Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Applications." Sensor Letters 18, no. 9 (September 1, 2020): 700–705. http://dx.doi.org/10.1166/sl.2020.4239.

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This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the internet. The transfer of data between different networks and electronic systems is controlled by internet of things (IoT) platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to SPI feature along with DMA on ASIC for IoT applications. It is described in very high speed integrated circuit hardware description language (VHDL) at register transfer level (RTL) and simulation is done on the Vivado 2016.2.

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29

SaiAbhinav, B., M. Jaipal Reddy, Y. Siva Kumar, and S. Sivanantham S.Sivanantham. "ASIC Design of Reversible Adder and Multiplier." International Journal of Computer Applications 109, no. 10 (January 16, 2015): 6–10. http://dx.doi.org/10.5120/19222-0638.

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30

Hayashi, S., and M. Yamada. "EMI-noise analysis under ASIC design environment." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19, no. 11 (2000): 1337–46. http://dx.doi.org/10.1109/43.892857.

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31

Comerma, A., D. Gascón, L. Garrido, C. Delgado, J. Marín, J. M. Pérez, G. Martínez, and L. Freixas. "Front End ASIC design for SiPM readout." Journal of Instrumentation 8, no. 01 (January 29, 2013): C01048. http://dx.doi.org/10.1088/1748-0221/8/01/c01048.

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32

Shetty, Ashish. "ASIC Design Flow And Methodology – An Overview." International Journal of Electrical and Electronics Engineering 6, no. 7 (July 25, 2019): 1–5. http://dx.doi.org/10.14445/23488379/ijeee-v6i7p101.

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33

WANG, P. "The Design of a Monolithic MSTP ASIC." IEICE Transactions on Electronics E89-C, no. 8 (August 1, 2006): 1248–54. http://dx.doi.org/10.1093/ietele/e89-c.8.1248.

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34

Zhang, Tianpei, and Sachin S. Sapatnekar. "Buffering global interconnects in structured ASIC design." Integration 41, no. 2 (February 2008): 171–82. http://dx.doi.org/10.1016/j.vlsi.2007.04.002.

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35

Wild, Andreas, Rainer Makowitz, Franz Steininger, and Volker Kiefer. "Toward high-level synthesis for ASIC design." Microelectronics Journal 24, no. 3 (May 1993): 225–28. http://dx.doi.org/10.1016/0026-2692(93)90154-7.

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36

Hurst, S. L. "Successful ASIC design the first time through." Microelectronics Journal 25, no. 8 (November 1994): 769–70. http://dx.doi.org/10.1016/0026-2692(94)90144-9.

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37

Jayakumar, Nikhil, and Sunil P. Khatri. "A Predictably Low-Leakage ASIC Design Style." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15, no. 3 (March 2007): 276–85. http://dx.doi.org/10.1109/tvlsi.2007.893603.

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38

Cao, K., and J. Hu. "ASIC design flow considering lithography-induced effects." IET Circuits, Devices & Systems 2, no. 1 (2008): 23. http://dx.doi.org/10.1049/iet-cds:20070112.

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39

Pogra, Vivek, Santosh Kumar Vishvakarma, and Balwinder Raj. "Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Application." Sensor Letters 18, no. 1 (January 1, 2020): 31–38. http://dx.doi.org/10.1166/sl.2020.4176.

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This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the Internet. The transfer of data between different networks and internet of things (IoT) platform is controlled by IoT platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to the fact that it is designed for IoT applications. It is described in VHDL at RTL level and simulation is done on the Vivado 2016.2.

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40

Reed, Lynn. "A 250°C ASIC Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000134–38. http://dx.doi.org/10.4071/hiten-ta16.

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Tekmos has developed a 250°C ASIC technology that uses the X-Fab XI10 SOI process. A gate array architecture was chosen to allow reduced mask costs and quicker manufacturing cycle times. The design of the technology includes first determining the optimum routing grid and then designing of the basic gate array transistors. The “A” style transistor was chosen over the “H” style to create stronger transistors. The choice of the transistor in turn sets the characteristics of the basic “Block” that is used in the gate array architecture. Another factor in the block design is the requirement for a pre-determined source with “A” transistors. This prevents the use of shared diffusions that are used in most gate array architectures and resulted in a different block layout. The pre-determined sources also required a change to the logic cell library. Since the basic transmission gate found in most flop designs cannot be used, alternative logic architectures were developed. By implementing the SOI specific library into the Tekmos standard logic library, the SOI peculiarities were masked from the end designer. The 250°C ASIC technology was demonstrated in a FPGA conversion, in which a design in an Actel MX series FPGA was reimplemented in the 250°C ASIC technology. A standard FPGA design conversion flow was used, and the only issues were related to the speed and voltage differences between the FPGA and the 1.0μ ASIC. These were addressed through critical path analysis and some slight circuit modifications. The temperature derating for 250°C was significant, but enough margin was retained to allow the circuit to work. Parts were made and worked as expected at 250°C. The life testing results at 280°C have been satisfactory. On an experimental basis, parts were evaluated at temperatures of up to 305°C without failure.

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41

Zhou, Li, Jun She An, Qing Wen Fang, and Fei Cai. "Design of an ASIC Chip for Spacecraft Data System." Applied Mechanics and Materials 390 (August 2013): 611–15. http://dx.doi.org/10.4028/www.scientific.net/amm.390.611.

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ASIC (Application Specific Integrated Circuit) technology is mature and widely used in many fields. It is a trend to integrate some common spacecraft engineering requirements into one chip to take the place of FPGA and some digital chips, which can miniaturize spacecraft avionics and reduce the repeated work for spacecraft engineers. Based on the analysis on small satellites application requirements, the system design of an ASIC chip for spacecraft data system is proposed. Firstly, the chip system architecture is described. Secondly, four key technologies of the ASIC chip design are presented in detail. They are the design of the chip's operating modes, the design of IP cores, the design of reliability, and the design of low power consumption. Generality, adaptability and independent intellectual property make this ASIC different and special from other space chips. Four operating modes are optional: 1553B bus control mode, PCI control mode, ISA control mode, internal CPU control mode. Besides, there are 1553B bus protocol IP cores, CAN bus interface, and abundant peripherals, which can satisfy most of the routine engineering requirements in small satellites. Finally, the chips status and some promising applications are described.

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42

Obert, James, and Tom J. Mannos. "ASIC STA Path Verification Using Semi-Supervised Learning." International Journal of Semantic Computing 13, no. 02 (June 2019): 229–44. http://dx.doi.org/10.1142/s1793351x19400105.

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To counter manufacturing irregularities and ensure ASIC design integrity, it is essential that robust design verification methods are employed. It is possible to ensure such integrity using ASIC static timing analysis (STA) and machine learning. In this research, uniquely devised machine and statistical learning methods which quantify anomalous variations in Register Transfer Level (RTL) or Graphic Design System II (GDSII) format are discussed. To measure the variations in ASIC analysis data, the timing delays in relation to path electrical characteristics are explored. It is shown that semi-supervised learning techniques are powerful tools in characterizing variations within STA path data and have much potential for identifying anomalies in ASIC RTL and GDSII design data.

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43

Yuan, Yu Ying, and Yong Gang Luo. "The ASIC Design and Verification Based on Verilog HDL." Advanced Materials Research 433-440 (January 2012): 4578–83. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.4578.

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Logic design and verification is the frontend of ASIC (Application Specific Integrated Circuit), and is a very important design part during the design process of ASIC. A Verilog HDL design case－2×2 SDH digital cross-connect matrix is provided to illustrate the entire design process including logic-level description, verification and synthesis based on the frontend tools of Synopsys. After that a gate-level netlist conforming to the design requirements can be obtained.

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44

SAVIĆ, NEMANJA, MILE STOJČEV, TATJANA NIKOLIĆ, VLADIMIR PETROVIĆ, and GORAN JOVANOVIĆ. "RECONFIGURABLE LOW POWER ARCHITECTURE FOR FAULT TOLERANT PSEUDO-RANDOM NUMBER GENERATION." Journal of Circuits, Systems and Computers 23, no. 01 (January 2014): 1450002. http://dx.doi.org/10.1142/s0218126614500029.

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High operating speed, fault tolerance (FT), low power and reconfiguration become today dominant issues during development and design of linear feedback shift registers (LFSRs), used as sequence generators, with randomness properties, in a process of testing complex CMOS VLSI ICs. In our design solution, we accomplish FT by using triple modular redundancy (TMR), i.e., a hardware scheme that uses spatial redundancy. For reduction of dynamic power consumption, clock-gating technique, as a simple and effective method, is implemented. The reconfigurable FPGA architecture provides us a feature to program and configure the degree of the primitive polynomial that the LFSR uses. High speed of operation, over 100 MHz, during testing is achieved by using circuits fabricated in submicron technology. An architecture which integrates in a single structure (IP core) all aforementioned design issues, named fault tolerant reconfigurable low-power pseudo-random number generator (FT_RLRG), is described in this article. The design of FT_RLRG is of practical interest in testing triple modular FT systems in the presence of single event upsets (SEUs), especially in a case when the design is SRAM-based. As an IP core the FT_RLRG has been implemented both on FPGA and ASIC technology. The main idea was to design a low-cost and low-power hardware structure which is able to adjust to any standards (past, present and future) operating at high-speed with different polynomials (currently up to 32nd order). The performance of FT_RLRG in respect to speed of operation (up to 150 MHz for FPGA and ASIC designs), low hardware overhead (0.033 mm2 area for ASIC and up to 530 slices for FPGA) and low-power consumption (0.45 mW for ASIC), for three different FPGA architecture (Spartan-3E, Virtex-4 and Virtex-6LP) and as an ASIC design implemented in 130 nm SiGe BiCMOS technology, have been estimated.

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45

Boxer, B., B. Godfrey, C. Grace, J. Johnson, R. Khandwala, and M. Tripathi. "Studies in pulse shape discrimination for an optimized ASIC design." Journal of Instrumentation 18, no. 01 (January 1, 2023): P01020. http://dx.doi.org/10.1088/1748-0221/18/01/p01020.

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Abstract The continued advancements of Silicon Photomultipliers (SiPMs) have made them viable photosensors for low recoil energy Pulse Shape Discrimination (PSD) between fast neutron and gamma interactions when coupled to an appropriate scintillator. At the same time, the large number of channels in a typical array calls for the development of low-cost and low-power electronics. A custom integrated circuit (ASIC) is an ideal solution for this purpose. To assess the requirements for such an ASIC, studies were performed using two scintillators, Stilbene and EJ-276, coupled to a 6 × 6 mm SiPM from Onsemi. We demonstrate that both scintillators are viable for performing PSD for interaction energies from 100 keV to several MeV while optimizing the integration periods used in the PSD metric. These measurements inform the design parameters of the ASIC under development.

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46

Benschwartz, R., and P. Sakthivel. "A Process Variation Tolerant OTA Design for Low Power ASIC Design." Circuits and Systems 07, no. 06 (2016): 956–70. http://dx.doi.org/10.4236/cs.2016.76081.

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47

Sabbavarapu, Srinivas, Karunakar R. Basireddy, and Amit Acharyya. "Novel ASIC Design Flow Using Dynamic Libraries for Reducing Design Time." Journal of Low Power Electronics 14, no. 2 (June 1, 2018): 337–50. http://dx.doi.org/10.1166/jolpe.2018.1548.

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48

Zhang, Wangdong, Bo Fan, Chao Lu, and Huimin Liu. "LADRC Based Digital Control DC-DC ASIC Design." Journal of Physics: Conference Series 2290, no. 1 (June 1, 2022): 012074. http://dx.doi.org/10.1088/1742-6596/2290/1/012074.

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Abstract The Internet of Things (IoT) systems require power management modules to have the characteristics of low power consumption, high conversion efficiency, high integration, stable output, and good dynamic response. Due to its ease of tuning and superior control performance, linear active disturbance rejection control (LADRC) is an attractive design option. Yet, to date, due to its high complexity, LADRC has been used in software systems, while little effort has been made in its hardware implementation. In this work, we investigate and explore efficient hardware implementation of the LADRC algorithm. A fully integrated digital LADRC controller for DC-DC Buck converters is synthesized with UMC 55 nm CMOS process. Its input voltage is 5V, stable output voltage is 2V, and rated operating current is 100mA. To our best knowledge, this is the first work to implement LADRC algorithms in hardware. Simulation results show that the LADRC controller is superior to the PID controller in the terms of start-up time, line regulation, load regulation.

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49

Gholpe, Minal, and Prasad Sangare. "ASIC Design of Reversible Multiplier Using Adiabatic Technique." International Journal of Computer Applications Technology and Research 6, no. 2 (February 20, 2017): 117–20. http://dx.doi.org/10.7753/ijcatr0602.1009.

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50

Khan, Angshuman, Sudip Halder, and Shubhajit Pal. "Design of ASIC Square Calculator Using AncientVedic Mathematics." International Journal of Engineering & Technology 7, no. 2.23 (April 20, 2018): 464. http://dx.doi.org/10.14419/ijet.v7i2.23.15334.

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This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.

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Journal articles on the topic 'ASIC design'

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