Relevant bibliographies by topics / Asymmetric Double Gate MOSFET

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Asymmetric Double Gate MOSFET'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 September 2023

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Journal articles on the topic "Asymmetric Double Gate MOSFET"

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Singh, Ajay Kumar. "Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 38, no. 2 (March 4, 2019): 815–28. http://dx.doi.org/10.1108/compel-08-2018-0327.

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Purpose This study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs. Design/methodology/approach This paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach. Findings It is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement. Originality/value Compact Analytical models for undoped symmetric double gate MOSFETs.
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Wei, Zhaoxiang, Hao Fu, Xiaowen Yan, Sheng Li, Long Zhang, Jiaxing Wei, Siyang Liu, Weifeng Sun, Weili Wu, and Song Bai. "Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example." Materials 15, no. 2 (January 8, 2022): 457. http://dx.doi.org/10.3390/ma15020457.

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The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (Eox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the Cgd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (Vth) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.
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Abebe, H., E. Cumberbatch, H. Morris, V. Tyree, T. Numata, and S. Uno. "Symmetric and Asymmetric Double Gate MOSFET Modeling." JSTS:Journal of Semiconductor Technology and Science 9, no. 4 (December 30, 2009): 225–32. http://dx.doi.org/10.5573/jsts.2009.9.4.225.

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Zou, Yuan, Jue Wang, Hongyi Xu, and Hengyu Wang. "Investigation of SiC Trench MOSFETs’ Reliability under Short-Circuit Conditions." Materials 15, no. 2 (January 13, 2022): 598. http://dx.doi.org/10.3390/ma15020598.

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In this paper, the short-circuit robustness of 1200 V silicon carbide (SiC) trench MOSFETs with different gate structures has been investigated. The MOSFETs exhibited different failure modes under different DC bus voltages. For double trench SiC MOSFETs, failure modes are gate failure at lower dc bus voltages and thermal runaway at higher dc bus voltages, while failure modes for asymmetric trench SiC MOSFETs are soft failure and thermal runaway, respectively. The shortcircuit withstanding time (SCWT) of the asymmetric trench MOSFET is higher than that of the double trench MOSFETs. The thermal and mechanical stresses inside the devices during the short-circuit tests have been simulated to probe into the failure mechanisms and reveal the impact of the device structures on the device reliability. Finally, post-failure analysis has been carried out to verify the root causes of the device failure.
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Jung, Hakkee. "Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 1 (February 1, 2019): 163. http://dx.doi.org/10.11591/ijece.v9i1.pp163-169.

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Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.
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Kumari, Vandana, Manoj Saxena, and Mridula Gupta. "Modeling and Simulation of Nanoscale Lateral Gaussian Doped Channel Asymmetric Double Gate MOSFET." Journal of Nano Research 36 (November 2015): 51–63. http://dx.doi.org/10.4028/www.scientific.net/jnanor.36.51.

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This work presents the drain current model using Evanescent Mode Analysis (EMA) for nanoscale Double Gate MOSFET having Gaussian doping profile along the horizontal direction in the channel i.e. from source to drain region. Due to heavily doped channel, band gap narrowing effect is incorporated in the analytical modeling scheme. The various parameters evaluated in this work using analytical modeling scheme are surface potential, electric field, threshold voltage, sub-threshold slope and drain current. The impact of peak Gaussian doping profile on the drain current and trans-conductance has been demonstrated which are important for assessing the analog performance of the device. The results are also compared with the uniformly doped DG MOSFET. The asymmetric behaviour of Gaussian doped DG MOSFET has also been investigated. In addition to this, digital performance of Gaussian doped DG MOSFET has also been assessed using exhaustive device simulation.
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Jung, Hakkee. "Analysis for Gate Oxide Dependent Subthreshold Swing of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 4 (April 30, 2014): 885–90. http://dx.doi.org/10.6109/jkiice.2014.18.4.885.

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Jung, Hak Kee. "Projected Range Dependent Tunneling Current of Asymmetric Double Gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 1 (February 1, 2016): 113. http://dx.doi.org/10.11591/ijece.v6i1.9342.

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This study is to analyze the changes of tunneling current according to projected range, a variable of Gaussian function of channel doping function of Asymmetric Double Gate; ADG MOSFET. In MOSFET with channel length below 10 nm, tunneling current occupies a large percentage among off-currents. The increase of tunneling current has a large effect on the characteristics of subthreshold such as threshold voltage movement and the decline of subthreshold swing value, so the accurate analysis of this is being required. To analyze this, potential distribution of series form was obtained using Gaussian distribution function, and using this hermeneutic potential distribution, thermionic emission current and tunneling current making up off-current were obtained. At this point, the effect that the changes of projected range, a variable of Gaussian distribution function, have on the ratio of tunneling current among off-currents was analyzed. As a result, the smaller projected range was, the lower the ratio of tunneling current was. When projected range increased, tunneling current increased largely. Also, it was observed that the value of projected range which the ratio of tunneling current increased changed according to maximum channel doping value, channel length, and channel width.
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Jung, Hak Kee. "Projected Range Dependent Tunneling Current of Asymmetric Double Gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 1 (February 1, 2016): 113. http://dx.doi.org/10.11591/ijece.v6i1.pp113-119.

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This study is to analyze the changes of tunneling current according to projected range, a variable of Gaussian function of channel doping function of Asymmetric Double Gate; ADG MOSFET. In MOSFET with channel length below 10 nm, tunneling current occupies a large percentage among off-currents. The increase of tunneling current has a large effect on the characteristics of subthreshold such as threshold voltage movement and the decline of subthreshold swing value, so the accurate analysis of this is being required. To analyze this, potential distribution of series form was obtained using Gaussian distribution function, and using this hermeneutic potential distribution, thermionic emission current and tunneling current making up off-current were obtained. At this point, the effect that the changes of projected range, a variable of Gaussian distribution function, have on the ratio of tunneling current among off-currents was analyzed. As a result, the smaller projected range was, the lower the ratio of tunneling current was. When projected range increased, tunneling current increased largely. Also, it was observed that the value of projected range which the ratio of tunneling current increased changed according to maximum channel doping value, channel length, and channel width.
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Jung, Hakkee. "Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (February 1, 2021): 240. http://dx.doi.org/10.11591/ijece.v11i1.pp240-248.

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In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.
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Dissertations / Theses on the topic "Asymmetric Double Gate MOSFET"

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Lin, Xinnan. "Double gate MOSFET technology and applications /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LIN.

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Borundiya, Amit Parasmal. "Implementation of Hopfield Neural Network Using Double Gate MOSFET." Ohio University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1204910134.

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Man, Tsz Yin. "One dimensional quantum mechanical transport in double-gate MOSFET /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20MAN.

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Liang, Xiaoping. "Analytical modeling of short channel effects in double gate MOSFET." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3204577.

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Thesis (Ph. D.)--University of California, San Diego, 2006.
Title from first page of PDF file (viewed April 4, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references.
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Meinhold, Mitchell W. 1972. "X-ray lithographic alignment and overlay applied to double-gate MOSFET fabrication." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/28271.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (leaves 117-118).
Double-gate MOSFETs represent a significant solution to transistor scaling problems and promise a dramatic improvement in both performance and power consumption. In this work, a planar lithographic process is presented that is capable of producing double-gate MOSFET (DGFET) gate structures with 50 nm physical gate length and <5 nm alignment between upper and lower gates. Because a self-aligned approach is not taken, the central challenge in fabrication is to define each gate in separate lithographic steps with precision alignment of upper to lower-gate masks. In order to obtain optimum device performance, the position of the lower-gate should be aligned to the upper-gate to better than 10% of the gate length. The gates are defined using X-ray lithography (a close-proximity shadow printing scheme). The associated alignment scheme, Interferometric Broad Band Imaging (IBBI), has been proven to yield nanometer level sensitivity. While the IBBI alignment system offers superior alignment detectivity, it must be complemented by comparably successful mask pattern placement in order to yield structure details within the desired 5 nm tolerances. This work addresses the details of a novel mask design and fabrication scheme as well as its incorporation into the process flow of the DGFET. Additionally, the parasitic effects of strain that result from wafer bonding and thermal effects have been measured and analyzed.
by Mitchell W. Meinhold.
Ph.D.
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Varadharajan, Swetha. "Digital and Analog Applications of Double Gate Mosfets." Ohio University / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1132759182.

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Kulkarni, Anish S. "Study of Tunable Analog Circuits Using Double Gate Metal Oxide Semiconductor Field Effect Transistors." Ohio University / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1234552603.

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Ferreira, Luiz Fernando. "Double-gate nanotransistors in silicon-on-insulator : simulation of sub-20 nm FinFETs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/65631.

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Esta Tese apresenta os resultados da simulação do transporte eletrônico em três dimensões (3D) no nano dispositivo eletrônico conhecido como “SOI-FinFET”. Este dispositivo é um transistor MOS em tecnologia Silício sobre Isolante – “Silicon-on- Insulator”, SOI – com porta dupla e cujo canal e zonas de fonte e dreno são realizadas em uma estrutura nanométrica vertical de silício chamada de “finger” ou “fin”. Como introdução ao dispositivo em questão, é feita uma revisão básica sobre a tecnologia e transistores SOI e sobre MOSFETs de múltiplas portas. A implementação de um modelo tipo “charge-sheet” para o transistor SOI-MOSFET totalmente depletado e uma modelagem deste dispositivo em altas frequências também é apresentada. A geometria do “fin” é escalada para valores menores do que 100 nm, com uma espessura entre 10 e 20 nm. Um dos objetivos deste trabalho é a definição de parâmetros para o SOI-FinFET que o viabilizem para a tecnologia de 22 nm, com um comprimento efetivo de canal menor do que 20 nm. O transistor FinFET e uma estrutura básica simplificada para simulação numérica em 3D são descritos, sendo utilizados dados de tecnologias atuais de fabricação. São apresentados resultados de simulação numérica 3D (curvas ID-VG, ID-VD, etc.) evidenciando as principais características de funcionamento do FinFET. É analisada a influência da espessura e dopagem do “fin” e do comprimento físico do canal em parâmetros importantes como a tensão de limiar e a inclinação de sublimiar. São consideradas e analisadas duas possibilidades de dopagens da área ativa do “fin”: (1) o caso em que esta pode ser considerada não dopada, sendo baixíssima a probabilidade da presença de dopantes ativos, e (2) o caso de um alto número de dopantes ativos (> 10 é provável). Uma comparação entre dois simuladores numéricos 3D de dispositivos é realizada no intuito de explicitar diferenças entre modelos de simulação e características de descrição de estruturas 3D. São apresentadas e analisadas medidas em dispositivos FinFET experimentais. Dois métodos de extração de resistência série parasita são utilizados em FinFETs simulados e caracterizados experimentalmente. Para finalizar, são resumidas as principais conclusões deste trabalho e são propostos os trabalhos futuros e novas diretivas na pesquisa dos transistores FinFETs.
This thesis presents the results of 3D-numerical simulation of electron transport in double-gate SOI-FinFETs in the decanometer size range. A basic review on the SOI technology and multiple gates MOSFETs is presented. The implementation of a chargesheet model for the fully-depleted SOI-MOSFET and a high frequency modeling of this device are first presented for a planar device topology. The second part of this work deals with FinFETs, a non-planar topology. The geometry of the silicon nano-wire (or “fin”) in this thesis is scaled down well below 100 nm, with fin thickness in the range of 10 to 20 nm. This work addresses the parameters for a viable 22 nm CMOS node, with electrical effective channel lengths below 20 nm. The basic 3D structure of the FinFET transistor is described in detail, then it is simulated with various device structural parameters, and results of 3D-numerical simulation (ID-VG curves, ID-VD, etc.), showing the main features of operation of this device, are presented. The impacts of varying silicon fin thicknesses, physical channel lengths, and silicon fin doping concentration on both the average threshold voltage and the subthreshold slope are investigated. With respect to the doping concentration, the discrete and highly statistical nature of impurity presence in the active area of the nanometer-range fin is considered in two limiting cases: (1) the zero-doping or undoped case, for highly improbable presence of active dopants, and (2) the many-dopants case, or high number (> 10 are probable) of active dopants in the device channel. A comparison between two 3D-numerical device simulators is performed in order to clarify differences between simulation models and features of the description of 3D structures. A structure for SOIFinFETs is optimized, for the undoped fin, showing its applicability for devices with electrical effective channel lengths below 20 nm. SOI-FinFET measurements were performed on experimental devices, analyzed and compared to device simulation results. This thesis uses parasitic resistance extraction methods that are tested in FinFET simulations and measurements. Finally, the main conclusions of this work are summarized and the future work and new directions in the FinFETs research are proposed.
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Laha, Soumyasanta. "Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs." Ohio University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974.

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Moolamalla, Himaja Reddy. "An analysis on the simulation of the leakage currents of independent double gate SOI MOSFET transistors a thesis presented to the faculty of the Graduate School, Tennessee Technological University /." Click to access online, 2009. http://proquest.umi.com/pqdweb?index=0&did=2000377751&SrchMode=1&sid=5&Fmt=6&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1277473834&clientId=28564.

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Book chapters on the topic "Asymmetric Double Gate MOSFET"

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Yadava, Narendra, Vimal K. Mishra, and R. K. Chauhan. "Analysis of N+N− Epi-Source Asymmetric Double Gate FD-SOI MOSFET." In Advances in Intelligent Systems and Computing, 541–49. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7566-7_54.

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Basak, Arighna, Arpan Deyasi, and Angsuman Sarkar. "Impact of Negative Bottom Gate Voltage for Improvement of RF/Analog Performance in Asymmetric Junctionless Dual Material Double Gate MOSFET." In Lecture Notes in Electrical Engineering, 153–62. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-6301-8_12.

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Srivastava, Viranjay M., and Ghanshyam Singh. "Design of Double-Gate MOSFET." In Analog Circuits and Signal Processing, 45–83. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-01165-3_3.

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Srivastava, Viranjay M., and Ghanshyam Singh. "Cylindrical Surrounding Double-Gate RF MOSFET." In Analog Circuits and Signal Processing, 111–42. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-01165-3_5.

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Yadav, Menka. "Double Gate Tunnel FET Versus Double Gate MOSFET: Electrical Properties Comparison." In Lecture Notes in Electrical Engineering, 791–803. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7031-5_75.

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Camiola, Vito Dario, Giovanni Mascali, and Vittorio Romano. "Mathematical Models for the Double-Gate MOSFET." In Mathematics in Industry, 191–210. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-35993-5_7.

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Srivastava, Viranjay M., and Ghanshyam Singh. "Double-Pole Four-Throw RF Switch Based on Double-Gate MOSFET." In Analog Circuits and Signal Processing, 85–109. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-01165-3_4.

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Lalthlamuana, James, Niladri Pratap Maity, L. L. K. Singh, and Reshmi Maity. "Electrical Performance of Single Gate and Double Gate MOSFET to Optimize the Gate Length." In Lecture Notes in Electrical Engineering, 673–82. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-4909-4_52.

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Prasad, Jitendra, Amit Agarwal, P. C. Pradhan, and B. P. Swain. "Analytical Modeling of Surface Potential for Double-Gate MOSFET." In Advances in Communication, Devices and Networking, 55–62. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-3450-4_7.

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Narang, Rakhi, Gokulnath Rajendran, Mridula Gupta, and Manoj Saxena. "Analytical Model for Tapered Gate Electrode Double Gate MOSFET Incorporating Fringing Field Effects." In Springer Proceedings in Physics, 697–705. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-97604-4_108.

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Conference papers on the topic "Asymmetric Double Gate MOSFET"

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Jilowa, Sudarshana, Sandeep Singh Gill, and Gurjot Kaur Walia. "Design of 3C-SiC symmetric and asymmetric double gate MOSFET." In 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA). IEEE, 2016. http://dx.doi.org/10.1109/vlsi-sata.2016.7593052.

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Hazarika, Mustafizur Rahman, and Nipanka Bora. "Performance analysis of 3-D asymmetric junctionless double gate MOSFET." In 2017 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS). IEEE, 2017. http://dx.doi.org/10.1109/icecds.2017.8389672.

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Jung, Hakkee. "Subthreshold Swing for Top and Bottom Gate Oxide Thickness of Asymmetric Double Gate MOSFET." In Electrical Engineering 2013. Science & Engineering Research Support soCiety, 2013. http://dx.doi.org/10.14257/astl.2013.37.07.

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Ortiz-Conde, Adelmo, Francisco Garcia Sanchez, Slavica Malobabic, Juan Muci, and Ram�n Salazar. "Drain Current and Transconductance Model for the Undoped Body Asymmetric Double-Gate MOSFET." In 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings. IEEE, 2006. http://dx.doi.org/10.1109/icsict.2006.306103.

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Riyadi, Munawar A. "Performance comparison of asymmetric drain/source topology in nanoscale Double Gate vertical MOSFET." In 2013 International Conference on Information Technology and Electrical Engineering (ICITEE). IEEE, 2013. http://dx.doi.org/10.1109/iciteed.2013.6676285.

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Mishra, Abhijit, Subir Kumar Maity, and Sayantika Dutta. "Effect of spacer dielectric of asymmetric underlap double gate MOSFET on SRAM performance." In 2017 Devices for Integrated Circuit (DevIC). IEEE, 2017. http://dx.doi.org/10.1109/devic.2017.8074067.

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Mishra, Abhijit, and Subir Kumar Maity. "Influence of high-κ spacer on analog/RF performance of asymmetric underlap double gate MOSFET." In 2016 International conference on Signal Processing, Communication, Power and Embedded System (SCOPES). IEEE, 2016. http://dx.doi.org/10.1109/scopes.2016.7955522.

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Tiwari, Pramod Kumar, Sarvesh Dubey, and S. Jit. "Subthreshold swing model for asymmetric 3T double gate (DG) MOSFETs." In 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2010. http://dx.doi.org/10.1109/icsict.2010.5667663.

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Vaddi, Ramesh, S. Dasgupta, and R. P. Agarwal. "Two dimensional analytical subthreshold swing model of a double gate MOSFET with Gate-S/D underlap, asymmetric and independent gate features." In 2011 International Conference on Electronic Devices, Systems and Applications (ICEDSA). IEEE, 2011. http://dx.doi.org/10.1109/icedsa.2011.5959057.

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Basak, Arighna, Arpan Deyasi, and Angsuman Sarkar. "Analytical Modeling of Asymmetric Junctionless Dual Material Double Gate MOSFET with Underlap for Enhanced Hot Carrier Reliability." In 2023 IEEE Devices for Integrated Circuit (DevIC). IEEE, 2023. http://dx.doi.org/10.1109/devic57758.2023.10134835.

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