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1
Lin, Xinnan. "Double gate MOSFET technology and applications /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LIN.
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2
Borundiya, Amit Parasmal. "Implementation of Hopfield Neural Network Using Double Gate MOSFET." Ohio University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1204910134.
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Man, Tsz Yin. "One dimensional quantum mechanical transport in double-gate MOSFET /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20MAN.
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4
Liang, Xiaoping. "Analytical modeling of short channel effects in double gate MOSFET." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3204577.
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Thesis (Ph. D.)--University of California, San Diego, 2006.Title from first page of PDF file (viewed April 4, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references.
5
Meinhold, Mitchell W. 1972. "X-ray lithographic alignment and overlay applied to double-gate MOSFET fabrication." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/28271.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (leaves 117-118).
Double-gate MOSFETs represent a significant solution to transistor scaling problems and promise a dramatic improvement in both performance and power consumption. In this work, a planar lithographic process is presented that is capable of producing double-gate MOSFET (DGFET) gate structures with 50 nm physical gate length and <5 nm alignment between upper and lower gates. Because a self-aligned approach is not taken, the central challenge in fabrication is to define each gate in separate lithographic steps with precision alignment of upper to lower-gate masks. In order to obtain optimum device performance, the position of the lower-gate should be aligned to the upper-gate to better than 10% of the gate length. The gates are defined using X-ray lithography (a close-proximity shadow printing scheme). The associated alignment scheme, Interferometric Broad Band Imaging (IBBI), has been proven to yield nanometer level sensitivity. While the IBBI alignment system offers superior alignment detectivity, it must be complemented by comparably successful mask pattern placement in order to yield structure details within the desired 5 nm tolerances. This work addresses the details of a novel mask design and fabrication scheme as well as its incorporation into the process flow of the DGFET. Additionally, the parasitic effects of strain that result from wafer bonding and thermal effects have been measured and analyzed.
by Mitchell W. Meinhold.
Ph.D.
6
Varadharajan, Swetha. "Digital and Analog Applications of Double Gate Mosfets." Ohio University / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1132759182.
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Kulkarni, Anish S. "Study of Tunable Analog Circuits Using Double Gate Metal Oxide Semiconductor Field Effect Transistors." Ohio University / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1234552603.
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Ferreira, Luiz Fernando. "Double-gate nanotransistors in silicon-on-insulator : simulation of sub-20 nm FinFETs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/65631.
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Esta Tese apresenta os resultados da simulação do transporte eletrônico em três dimensões (3D) no nano dispositivo eletrônico conhecido como “SOI-FinFET”. Este dispositivo é um transistor MOS em tecnologia Silício sobre Isolante – “Silicon-on- Insulator”, SOI – com porta dupla e cujo canal e zonas de fonte e dreno são realizadas em uma estrutura nanométrica vertical de silício chamada de “finger” ou “fin”. Como introdução ao dispositivo em questão, é feita uma revisão básica sobre a tecnologia e transistores SOI e sobre MOSFETs de múltiplas portas. A implementação de um modelo tipo “charge-sheet” para o transistor SOI-MOSFET totalmente depletado e uma modelagem deste dispositivo em altas frequências também é apresentada. A geometria do “fin” é escalada para valores menores do que 100 nm, com uma espessura entre 10 e 20 nm. Um dos objetivos deste trabalho é a definição de parâmetros para o SOI-FinFET que o viabilizem para a tecnologia de 22 nm, com um comprimento efetivo de canal menor do que 20 nm. O transistor FinFET e uma estrutura básica simplificada para simulação numérica em 3D são descritos, sendo utilizados dados de tecnologias atuais de fabricação. São apresentados resultados de simulação numérica 3D (curvas ID-VG, ID-VD, etc.) evidenciando as principais características de funcionamento do FinFET. É analisada a influência da espessura e dopagem do “fin” e do comprimento físico do canal em parâmetros importantes como a tensão de limiar e a inclinação de sublimiar. São consideradas e analisadas duas possibilidades de dopagens da área ativa do “fin”: (1) o caso em que esta pode ser considerada não dopada, sendo baixíssima a probabilidade da presença de dopantes ativos, e (2) o caso de um alto número de dopantes ativos (> 10 é provável). Uma comparação entre dois simuladores numéricos 3D de dispositivos é realizada no intuito de explicitar diferenças entre modelos de simulação e características de descrição de estruturas 3D. São apresentadas e analisadas medidas em dispositivos FinFET experimentais. Dois métodos de extração de resistência série parasita são utilizados em FinFETs simulados e caracterizados experimentalmente. Para finalizar, são resumidas as principais conclusões deste trabalho e são propostos os trabalhos futuros e novas diretivas na pesquisa dos transistores FinFETs.This thesis presents the results of 3D-numerical simulation of electron transport in double-gate SOI-FinFETs in the decanometer size range. A basic review on the SOI technology and multiple gates MOSFETs is presented. The implementation of a chargesheet model for the fully-depleted SOI-MOSFET and a high frequency modeling of this device are first presented for a planar device topology. The second part of this work deals with FinFETs, a non-planar topology. The geometry of the silicon nano-wire (or “fin”) in this thesis is scaled down well below 100 nm, with fin thickness in the range of 10 to 20 nm. This work addresses the parameters for a viable 22 nm CMOS node, with electrical effective channel lengths below 20 nm. The basic 3D structure of the FinFET transistor is described in detail, then it is simulated with various device structural parameters, and results of 3D-numerical simulation (ID-VG curves, ID-VD, etc.), showing the main features of operation of this device, are presented. The impacts of varying silicon fin thicknesses, physical channel lengths, and silicon fin doping concentration on both the average threshold voltage and the subthreshold slope are investigated. With respect to the doping concentration, the discrete and highly statistical nature of impurity presence in the active area of the nanometer-range fin is considered in two limiting cases: (1) the zero-doping or undoped case, for highly improbable presence of active dopants, and (2) the many-dopants case, or high number (> 10 are probable) of active dopants in the device channel. A comparison between two 3D-numerical device simulators is performed in order to clarify differences between simulation models and features of the description of 3D structures. A structure for SOIFinFETs is optimized, for the undoped fin, showing its applicability for devices with electrical effective channel lengths below 20 nm. SOI-FinFET measurements were performed on experimental devices, analyzed and compared to device simulation results. This thesis uses parasitic resistance extraction methods that are tested in FinFET simulations and measurements. Finally, the main conclusions of this work are summarized and the future work and new directions in the FinFETs research are proposed.
9
Laha, Soumyasanta. "Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs." Ohio University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974.
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Moolamalla, Himaja Reddy. "An analysis on the simulation of the leakage currents of independent double gate SOI MOSFET transistors a thesis presented to the faculty of the Graduate School, Tennessee Technological University /." Click to access online, 2009. http://proquest.umi.com/pqdweb?index=0&did=2000377751&SrchMode=1&sid=5&Fmt=6&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1277473834&clientId=28564.
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El, Ghouli Salim. "UTBB FDSOI mosfet dynamic behavior study and modeling for ultra-low power RF and mm-Wave IC Design." Thesis, Strasbourg, 2018. http://www.theses.fr/2018STRAD015/document.
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Ce travail de recherche a été principalement motivé par les avantages importants apportés par la technologie UTBB FDSOI aux applications analogiques et RF de faible puissance. L'objectif principal est d'étudier le comportement dynamique du transistor MOSFET du type UTBB FDSOI et de proposer des modèles prédictifs et des recommandations pour la conception de circuits intégrés RF, en mettant un accent particulier sur le régime d'inversion modérée. Après une brève analyse des progrès réalisés au niveau des architectures du transistor MOSFET, un état de l’art de la modélisation du transistor MOSFET UTBB FDSOI est établi. Les principaux effets physiques impliqués dans le transistor à double grille avec une épaisseur du film de 7 nm sont passés en revue, en particulier l’impact de la grille arrière, à l’aide de mesures et de simulations TCAD. La caractéristique gm/ID en basse fréquence et la caractéristique ym/ID proposée pour la haute fréquence sont étudiées et utilisées dans une conception analogique efficace. Enfin, le modèle NQS haute fréquence proposé reproduit les mesures dans toutes les conditions de polarisation y compris l’inversion modérée jusqu’à 110 GHzThis research work has been motivated primarily by the significant advantages brought about by the UTBB FDSOI technology to the Low power Analog and RF applications. The main goal is to study the dynamic behavior of the UTBB FDSOI MOSFET in light of the recent technology advances and to propose predictive models and useful recommendations for RF IC design with particular emphasis on Moderate Inversion regime. After a brief review of progress in MOSFET architectures introduced in the semiconductor industry, a state-of-the-art UTBB FDSOI MOSFET modeling status is compiled. The main physical effects involved in the double gate transistor with a 7 nm thick film are reviewed, particularly the back gate impact, using measurements and TCAD. For better insight into the Weak Inversion and Moderate Inversion operations, both the low frequency gm/ID FoM and the proposed high frequency ym/ID FoM are studied and also used in an efficient first-cut analog design. Finally, a high frequency NQS model is developed and compared to DC and S-parameters measurements. The results show excellent agreement across all modes of operation including very low bias conditions and up to 110 GHz
12
Srivatsava, J. "Compact Modeling Of Asymmetric/Independent Double Gate MOSFET." Thesis, 2012. https://etd.iisc.ac.in/handle/2005/2346.
Full textAbstract:
For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs (MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk-MOSFET, an accurate and physical compact model is important for MuGFET based circuit design.
Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET(DGFET),as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thicknesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG(IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge.
We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two configurations1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG(IDG)MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate(DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device.
We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demonstrate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible.
An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design(TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.
13
Srivatsava, J. "Compact Modeling Of Asymmetric/Independent Double Gate MOSFET." Thesis, 2012. http://etd.iisc.ernet.in/handle/2005/2346.
Full textAbstract:
For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs (MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk-MOSFET, an accurate and physical compact model is important for MuGFET based circuit design.
Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET(DGFET),as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thicknesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG(IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge.
We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two configurations1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG(IDG)MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate(DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device.
We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demonstrate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible.
An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design(TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.
14
Sharan, Neha. "Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry." Thesis, 2014. http://etd.iisc.ac.in/handle/2005/3489.
Full textAbstract:
Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally efficient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, efficient compact models for these new transistors are required for their successful utilization in integrated circuits.
Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational efficiency at the same level. Such effort aims to generalize the compact model and also to capture the oxide thickness asymmetry effect, which might prevail in practical devices due to process uncertainties and thus affects the device performance significantly.
However solution to this modeling problem is nontrivial due to the bias-dependent asym-metric nature of the electrostatic. Using the single implicit equation based Poisson so-lution and the unique quasi-linear relationship between the surface potentials, previous researchers of our laboratory have reported the core model for such asymmetric CDG MOSFET. In this work effort has been put to include Non-Quasistatic (NQS) effects, different small-geometry effects, and noise model to this core, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry effects. This property of the device along with some other new techniques are used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully imple-mented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.
15
Sharan, Neha. "Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry." Thesis, 2014. http://etd.iisc.ernet.in/2005/3489.
Full textAbstract:
Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally efficient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, efficient compact models for these new transistors are required for their successful utilization in integrated circuits.
Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational efficiency at the same level. Such effort aims to generalize the compact model and also to capture the oxide thickness asymmetry effect, which might prevail in practical devices due to process uncertainties and thus affects the device performance significantly.
However solution to this modeling problem is nontrivial due to the bias-dependent asym-metric nature of the electrostatic. Using the single implicit equation based Poisson so-lution and the unique quasi-linear relationship between the surface potentials, previous researchers of our laboratory have reported the core model for such asymmetric CDG MOSFET. In this work effort has been put to include Non-Quasistatic (NQS) effects, different small-geometry effects, and noise model to this core, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry effects. This property of the device along with some other new techniques are used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully imple-mented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.
16
Liu, Shou-En, and 劉守恩. "Threshold Voltage Model of Asymmetry Double Gate MOSFET." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/23002033707927316207.
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Yeh, Ting-Hsien, and 葉婷銜. "Double-gate MOSFET Simulator." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/23537537074173278742.
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碩士國立交通大學
電子研究所
101
It is well known that the scaling of the traditional bulk MOSFETs would encounter several issues like the short channel effects (SCE). To deal with this problem, many of methods have been proposed, one of which is new device architectures, such as multi-gate structures. The aim of this work is to develop a double-gate n-MOSFET simulator by using self-consistent solving of Schrödinger and Poisson equations with some physical models taken into account. Besides, for many simulators in the literature, the boundary conditions of Schrödinger’s equation are often making an infinite potential barrier height at the silicon/gate-oxide interface. Nevertheless, we know that the actual barrier height is finite and is equal to a few electron-volts. Therefore, wave-function actually can penetrate into the gate-oxide dielectric. Hence, we also add wave-function penetration effect to our simulator, and discuss the influences of penetration effect and electron tunneling effective mass on the double-gate structure performance. Finally, we also build mobility and stress related model, and compare those with literature values. From the comparison results, our simulations are consistent with Schred as well as with some articles with and without wave-function penetration included, except for the mobility of thinner substrate thickness which should consider more scattering mechanisms. That is to say, our simulator comes to be reasonable for calculating fundamental properties in DG n-MOSFETs.
18
Hung, Wan-Te, and 洪萬得. "The Investigation on Subthreshold Behavior Model for Asymmetrical Double-gate MOSFETs." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/91003057503160193581.
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碩士南台科技大學
電子工程系
95
In recent years, studies about Double-Gate (DG) transistor have successively been proposed, and have attracted a lot of attention. As CMOS is scaled to the limit, dou-ble-gate (DG) MOSFET becomes increasingly important. A number of authors have ap-plied various simplifying assumptions to model the SCE of DG fully-depleted MOS-FETs analytically. Some of them make use of a parabolic potential approximation ap-proach for the device in the direction perpendicular to the surface. This results in a scale length proportional to the oxide and the silicon thickness. Large errors occur when one of thickness is much less than the other. Other approaches apply the superposition method to solve the 2-D boundary-value problem for the bulk MOSFETs. Most of them only put focus on device scaling scheme, threshold degradation by ignoring the 2-D ef-fects in the gate oxide. In order to give insight into the device physics, we need to de-velop a consolidated threshold voltage model for the DG transistor with fully 2-D ef-fects included in both silicon and gate oxide regions. In this thesis, we successfully develop a physical and analytical threshold voltage model for fully depleted Asymmetric DG MOSFETs by use of the 2-D analytical solu-tion in the entire region of the device based on fully closed-form solutions of Poisson’s equation in both regions of Si body and gate insulator. Without any fitting parameters, these analytical results are useful in predictive compact modeling of Asymmetric DG MOSFETs. The model shows the distribution of electric potential, short channel thresh-old voltage roll-off (ΔVTH), subthreshold current, subthreshold slope (Swing) and drain-induced barrier lowering (DIBL) effects. The new model is verified by published numerical simulations with close agreement. Due to its computational efficiency, this model can be applied for SPICE simulation.
19
Hsun, Chiang Tsung, and 蔣宗勳. "The Investigation on Subthreshold Behavior Model for Asymmetrical Dual Material Double-gate MOSFETs." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/87319086508650725079.
Full textAbstract:
碩士南台科技大學
電子工程系
96
In recent years, studies about Double-Gate (DG) transistor have successively been proposed, and have attracted a lot of attention. As CMOS is scaled to the limit, dou-ble-gate (DG) MOSFET becomes increasingly important. Besides, we use dual material on the front gate to overcome Short Channel Effect (SCE). A number of authors have applied various simplifying assumptions to model the SCE of DMDG fully-depleted MOSFETs analytically. Some of them make use of a parabolic potential approximation approach for the device in the direction perpendicular to the surface. This results in a scale length proportional to the oxide and the silicon thickness. Large errors occur when one of thickness is much less than the other. Other approaches apply the superposition method to solve the 2-D boundary-value problem for the bulk MOSFETs. Most of them only put focus on device scaling scheme, threshold degradation by ignoring the 2-D ef-fects in the gate oxide. In order to give insight into the device physics, we need to de-velop a consolidated threshold voltage model for the DG transistor with fully 2-D ef-fects included in both silicon and gate oxide regions. In this thesis, we successfully develop a physical and analytical sub-threshold be-havior model for fully depleted ADMDG MOSFET’s by use of the 2-D analytical solu-tion in the entire region of the device based on fully closed-form solutions of Poisson’s equation. Without any fitting parameters, these analytical results are useful in predictive compact modeling of ADMDG MOSFET’s. The model shows the distribution of elec-tric potential, electric field, short channel threshold voltage roll-off (ΔVTH), sub-threshold current and sub-threshold slope (Swing). The new model is verified by published numerical simulations with close agreement. Due to its computational effi-ciency, this model can be applied for SPICE simulation.
20
Kao, Chi-Hung, and 高啟弘. "An Investigation on the Asymmetric-Trapezoidal-Gate MOSFET Subthreshold Characteristics." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/76524228001794738566.
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Zhuo, Shi-Geng, and 卓世耿. "On the modelling of the asymmetric trapezoidal gate structure MOSFET." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/02269461737090964645.
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Lin, Chia-Long, and 林佳龍. "Implementation and application of a double-gate MOSFET compact model." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/00702736561428286245.
Full textAbstract:
碩士國立宜蘭大學
電子工程學系碩士班
99
Computer-aided design (CAD) is useful for early development of integrate circuits (ICs). SPICE is commonly used in circuit design. In circuit simulation, an analytical and physics-based compact model plays an important role in predicting performance and also issues. Nowadays, there are still no standard multi-gate MOSFETs compact models available in commercial tools. In this paper, we successfully developed a compact model which is focused on undoped symmetric double-gate (DG) MOSFETs using Verilog-A. Starting from Poisson’s equation solved for the undoped channel, surface and center potentials are then calculated by Newton iteration. An analytical drain current expression is derived from Pao-Sah’s double integral method. The model provides flexible parameters and is completely compatible with SPICE-like simulators.
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Hsin, Hsin-Yi, and 辛信億. "Analysis and Simulation of Double-Gate P-Channel Junctionless MOSFET." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/26016410553842410389.
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碩士國立中央大學
電機工程學系
101
In the thesis, at first we introduce the basic operating principles and advantages of the junctionless transistor. We use the two-dimensional device simulation to simulate the potential distribution of the junctionless transistor and then we get the variation of depletion region from turn-off to accumulation. We try to derive the threshold voltage and depletion layer thickness equation from Poisson’s equation, and furthermore figure out the drain current equation. We compare the equations with the result obtained by 2D numerical device simulation, and we change the parameters to observe effects of threshold voltage and drain current. At last, we simulate the switching characteristics of the short channel CMOS junctionless transistor. We compare the subthreshold swing of the junctionless transistor with a normal transistor in subthreshold region.
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Panda, Sashmita. "Performance Analysis of Single Gate and Double Gate MOSFET with and without Effect of Noise." Thesis, 2015. http://ethesis.nitrkl.ac.in/6827/1/Performance__Panda_2015.pdf.
Full textAbstract:
In modern era, computing systems are designed to perform innumerable number of functions with high speed, low power consumption, less propagation delay, the number of circuits in a chip keeps increasing day by day. So, the electronics industry always faces the challenge of miniaturization of transistors which increases the package density and hence linear scaling of CMOS technology has become a necessity in the present day microelectronic and nano-electronic regime. This causes a problem for static power consumption and hence conventional MOSFETs fail to face the situation. Also Short Channel Effects (SCEs) come into picture while scaling the MOSFET. Hence non-conventional devices started gaining its significance to meet the ITRS requirements. This thesis explains the performance analysis of Single Gate and Double Gate MOSFET with presence of noise. The performance of the MOSFET degrades when different noises come in to picture as compared to the previous MOSFET Model without noise. Also the behaviour of radio frequency (RF) DG MOSFET is analysed and verified up to 1MHz with measurements over a wide range of bias voltages and channel lengths. Significant variation in the noise spectral density has been observed.
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Zhang, Guang-Ming, and 張光明. "Simulation of Double Gate Junctionless MOSFET and Temperature Dependence of Threshold Voltage." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/13479381623399226569.
Full textAbstract:
碩士國立中央大學
電機工程學系
102
This thesis uses the C++ to develop an adapted band matrix solver to simulate the I-V curve and the drain current of the 2-D double-gate n-channel MOSFET. And it discusses the threshold voltage from the I-Vg curve and selects the appropriate doping concentration and channel thickness to complete the following experiments. The I-Vg curve will be simulated to determine threshold voltage. The I-V curve can calculate drain current in different gate voltage. The results can be compared with the other reference papers. The depletion width can be obtained as an analytical equation. The analytical depletion width can be verified by the 2-D simulation. The 2-D simulation also verifies the result with the drain current equation which is obtained by Poisson’s equation. The equations of the threshold voltage can be developed, and the threshold voltage of double-gate n-channel MOSFET can be calculated. Afterword, this paper will simulate and discuss the correction between threshold voltage and temperature. This paper will include the thermal voltage and intrinsic doping concentration of temperature in the C++ program. After simulating, the value of simulation will be compared with the value of the reference paper to confirm the trend of threshold voltage. For circuit application, an inverter including a double-gate n-channel MOSFET and a 100 kΩ resistor will be used to simulate the Vo-Vi characteristics and analyzes the parameters of the inverter, and the noise margin will be calculated in order to determine the inverter’s performance and quality.
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Huang, Ting-Yao, and 黃庭耀. "A Simulation-based Drain Leakage Current for Band-to-Band Tunneling in Single-Gate and Double-Gate n-MOSFET." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/96096956629293907534.
Full textAbstract:
碩士南台科技大學
電子工程系
93
Drain leakage current is a big problem for scaling the MOSFET’s into the deep sub-micrometer regime. When the application voltages much lower than the breakdown voltage, a significant drain leakage current can be detected, with regards this current in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications, and identified as the dominant leakage mechanism in discharging the DRAM storage node. Generally, the drain leakage current impute to the carrier tunneling phenomena. The tunneling phenomena are high electric field effect. In the presence of a high electric field, carriers gain energy from the field as they drift along. In modern VLSI devices, band to band tunneling has leaded to the significant leakage than cause the device performance less than anticipate and that is becoming one of the most important leakage current components. How to suppress the band to band tunneling is a strict challenge. Therefore, it is very important to have understanding and an accurate physical model to express the band to band tunneling current, particularly for applications such as the DRAM where leakage currents must be keep extremely low to lengthen the storage time.
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Tseng, Shih-Chuan, and 曾士權. "Novel Structures of Single/Double Gate MOSFET with Raised Source for Capacitor-less DRAM Application." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/xy4489.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
102
We propose novel 1T-DRAM cells with raised source structure. The cell using the raised source region can achieve the characteristics of long gate length one in a limited area. And, it can suppress short channel effects because the electric field of drain encroaches to vertical channel decreasingly. All these methods can improve the gate controllability. In addition, the raised source region possesses a larger data storage region without increasing the device area. Besides, the programming window can be improved 56.43 % compared with the conventional planar MOSFET, and the retention time can also be improved 56.63 %. Besides, the drain side still maintains the advantages of ultra-thin body structure, and the area of P-N junction is reduced greatly. Finally, since the raised source structure, the drain and source depletion regions of the cell could not to be contacted together easily so that the device does not appear punch through effect even the high drain bias is applied. On the other hand, we also propose the double-gate MOSFET with source-top structure simultaneously. We name it as the STDG MOSFET. By controlling the bias of the second gate, we can operate the device as a MOSFET or the 1T-DRAM friendly. Be a MOSFET, the device exhibits excellent SS = 66.95 mV/dec and DIBL = 28.98 mV/V. Whileas, be a 1T-DRAM we find the maximum value of the programming window (178.63 μA/μm) and the retention time (57.84 ms). STDG MOSFET has excellent programming window compared with those done by the other research teams.
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Singh, Amrinder. "Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor." Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488.
Full textAbstract:
In nanometer technologies, process variation control and low power have emerged as
the first order design goal after high performance. Process variations cause high variability
in performance and power consumption of an IC, which affects the overall yield. Short
channel effects (SCEs) deteriorate the MOSFET performance and lead to higher leakage
power. Double gate devices suppress SCEs and are potential candidates for replacing Bulk
technology in nanometer nodes. Threshold voltage control in planar asymmetric double
gate transistor (IGFET) using a fourth terminal provides an effective means of combating
process variations and low power design. In this thesis, using various case studies, we
analyzed the suitability of IGFET for variation control and low power design. We also
performed an extensive comparison between IGFET and Bulk for reducing variability, improving
yield and leakage power reduction using power gating. We also proposed a new
circuit topology for IGFET, which on average shows 33.8 percent lower leakage and 34.9 percent lower
area at the cost of 2.8 percent increase in total active mode power, for basic logic gates. Finally,
we showed a technique for reducing leakage of minimum sized devices designed using new
circuit topology for IGFET.
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江德光. "The modeling of the short channel devices in deep-submicrometer range:including GaAs MESFET''s, Si-SOI MESFET''s, SOI MOSFET''s and double-gate SOI MOSFET''s." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/83073047844185964096.
Full text
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Ray, Biswajit. "Impact Of Body Center Potential On The Electrostatics Of Undoped Body Multi Gate Transistors : A Modeling Perspective." Thesis, 2008. https://etd.iisc.ac.in/handle/2005/741.
Full textAbstract:
Undoped body multi gate (MG) Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are appearing as replacements for single gate bulk MOSFET in forthcoming sub-45nm technology nodes. It is therefore extremely necessary to develop compact models for MG transistors in order to use them in nano-scale integrated circuit design and simulation. There is however a sharp distinction between the electrostatics of traditional bulk transistors and undoped body devices. In bulk transistor, where the substrate is sufficiently doped, the inversion charges are located close to the surface and hence the surface potential solely controls the electrostatic integrity of the device. However, in undoped body devices, gate electric field penetrates the body center, and inversion charge exists throughout the body. In contrast to the bulk transistors, depending on device geometry, the potential of the body center of undoped body devices could be higher than the surface in weak inversion regime and the current flows through the center-part of the device instead of surface. Several crucial parameters (e.g. Sub-threshold slope) sometimes become more dependable on the potential of body center rather than the surface. Hence the body-center potential should also be modeled correctly along with the surface-potential for accurate calculation of inversion charge, threshold voltage and other related parameters of undoped body multi-gate transistors. Although several potential models for MG transistors have been proposed to capture the short channel behavior in the subthreshold regime but most of them are based on the crucial approximation of coverting the 2D Poisson’s equation into Laplace equation. This approximation holds good only at surface but breaks down at body center and in the moderate inversion regime. As a result all the previous models fail to capture the potential of body center Correctly and remain valid only in weak-inversion regime.
In this work we have developed semiclassical compact models for potential distribution for double gate (DG) and cylindrical Gate-All-Around (GAA) transistors. The models are based on the analytical solution of 2D Poisson’s equation in the channel region and valid for both: a) weak and strong inversion regimes, b) long channel and short channel transistors, and, c) body surface and center. Using the proposed model, for the first time, it is demonstrated that the body potential versus gate voltage characteristics for the devices having equal channel lengths but different body thicknesses pass through a single common point (termed as crossover point). Using the concept of “crossover point” the effect of body thickness on the threshold voltage of undoped body multi-gate transistors is explained. Based on the proposed body potential model, a new compact model for the subthreshold swing is formulated. Some other parameters e.g. inversion charge, threshold voltage roll-off etc are also studied to demonstrate the impact of body center potential on the electrostatics of multi gate transistor. All the models are validated against professional numerical device simulator.
31
Ray, Biswajit. "Impact Of Body Center Potential On The Electrostatics Of Undoped Body Multi Gate Transistors : A Modeling Perspective." Thesis, 2008. http://hdl.handle.net/2005/741.
Full textAbstract:
Undoped body multi gate (MG) Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are appearing as replacements for single gate bulk MOSFET in forthcoming sub-45nm technology nodes. It is therefore extremely necessary to develop compact models for MG transistors in order to use them in nano-scale integrated circuit design and simulation. There is however a sharp distinction between the electrostatics of traditional bulk transistors and undoped body devices. In bulk transistor, where the substrate is sufficiently doped, the inversion charges are located close to the surface and hence the surface potential solely controls the electrostatic integrity of the device. However, in undoped body devices, gate electric field penetrates the body center, and inversion charge exists throughout the body. In contrast to the bulk transistors, depending on device geometry, the potential of the body center of undoped body devices could be higher than the surface in weak inversion regime and the current flows through the center-part of the device instead of surface. Several crucial parameters (e.g. Sub-threshold slope) sometimes become more dependable on the potential of body center rather than the surface. Hence the body-center potential should also be modeled correctly along with the surface-potential for accurate calculation of inversion charge, threshold voltage and other related parameters of undoped body multi-gate transistors. Although several potential models for MG transistors have been proposed to capture the short channel behavior in the subthreshold regime but most of them are based on the crucial approximation of coverting the 2D Poisson’s equation into Laplace equation. This approximation holds good only at surface but breaks down at body center and in the moderate inversion regime. As a result all the previous models fail to capture the potential of body center Correctly and remain valid only in weak-inversion regime.
In this work we have developed semiclassical compact models for potential distribution for double gate (DG) and cylindrical Gate-All-Around (GAA) transistors. The models are based on the analytical solution of 2D Poisson’s equation in the channel region and valid for both: a) weak and strong inversion regimes, b) long channel and short channel transistors, and, c) body surface and center. Using the proposed model, for the first time, it is demonstrated that the body potential versus gate voltage characteristics for the devices having equal channel lengths but different body thicknesses pass through a single common point (termed as crossover point). Using the concept of “crossover point” the effect of body thickness on the threshold voltage of undoped body multi-gate transistors is explained. Based on the proposed body potential model, a new compact model for the subthreshold swing is formulated. Some other parameters e.g. inversion charge, threshold voltage roll-off etc are also studied to demonstrate the impact of body center potential on the electrostatics of multi gate transistor. All the models are validated against professional numerical device simulator.
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Kumar, P. Rakesh. "Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors." Thesis, 2009. https://etd.iisc.ac.in/handle/2005/969.
Full textAbstract:
Silicon nanowire based multiple gate metal oxide field effect transistors(MG-MOSFET) appear as replacements for conventional bulk transistors in post 45nm technology nodes. In such transistors the short channel effect(SCE) is controlled by the device geometry, and hence an undoped (or, lightly doped) ultra-thin body silicon nanowire is used to sustain the channel. The use of undoped body also solves several issues in bulk MOSFETs e.g., random dopant fluctuations, mobility degradation and compatibility with midgap metal gates. The electrostatic integrity of such devices increases with the scaling down of the body thickness. Since the quantization of electron energy cannot be ignored in such ultra-thin body devices, it is extremely important to consider quantum effects in their threshold voltage models.
Most of the models reported so far are valid for long channel double gate devices. Only Munteanu et al. [Journal of non-crystalline solids vol 351 pp 1911-1918 2005] have reported threshold voltage model for short channel symmetric double gate MOSFET, however it involves unphysical fitting parameters. Only Munteanu et al.[Molecular simulation vol 31 pp 839-845 2005] reported threshold voltage model for quad gate transistor which is implicit in nature. On the other hand no modeling work has been reported for other types of MG-MOSFETs (e.g., tri gate, cylindrical body)apart from numerical simulation results.
In this work we report physically based closed form quantum threshold voltage models for short channel symmetric double gate, quad gate and cylindrical body gate-all-around MOSFETs. In these devices quantum effects aries mainly due to the structural confinement of electron energy. Proposed models are based on the analytical solution of two or three-dimensional Poisson equation and one or two-dimensional Schrodinger equation depending on the device geometries. Judicial approximations have been taken to simplify the models in order to make them closed form and efficient for large scale circuit simulation. Effort has also been put to model the quantum threshold voltage of tri gate MOSFET. However it is found that the energy quantization in tri gate devices are mainly due to electronic confinement and hence it is very difficult to develop closed form analytical equations for the threshold voltage. Thus in this work the modeling of tri gate devices have been limited to long channel cases. All the models are validated against the professional numerical simulator.
33
Kumar, P. Rakesh. "Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors." Thesis, 2009. http://hdl.handle.net/2005/969.
Full textAbstract:
Silicon nanowire based multiple gate metal oxide field effect transistors(MG-MOSFET) appear as replacements for conventional bulk transistors in post 45nm technology nodes. In such transistors the short channel effect(SCE) is controlled by the device geometry, and hence an undoped (or, lightly doped) ultra-thin body silicon nanowire is used to sustain the channel. The use of undoped body also solves several issues in bulk MOSFETs e.g., random dopant fluctuations, mobility degradation and compatibility with midgap metal gates. The electrostatic integrity of such devices increases with the scaling down of the body thickness. Since the quantization of electron energy cannot be ignored in such ultra-thin body devices, it is extremely important to consider quantum effects in their threshold voltage models.
Most of the models reported so far are valid for long channel double gate devices. Only Munteanu et al. [Journal of non-crystalline solids vol 351 pp 1911-1918 2005] have reported threshold voltage model for short channel symmetric double gate MOSFET, however it involves unphysical fitting parameters. Only Munteanu et al.[Molecular simulation vol 31 pp 839-845 2005] reported threshold voltage model for quad gate transistor which is implicit in nature. On the other hand no modeling work has been reported for other types of MG-MOSFETs (e.g., tri gate, cylindrical body)apart from numerical simulation results.
In this work we report physically based closed form quantum threshold voltage models for short channel symmetric double gate, quad gate and cylindrical body gate-all-around MOSFETs. In these devices quantum effects aries mainly due to the structural confinement of electron energy. Proposed models are based on the analytical solution of two or three-dimensional Poisson equation and one or two-dimensional Schrodinger equation depending on the device geometries. Judicial approximations have been taken to simplify the models in order to make them closed form and efficient for large scale circuit simulation. Effort has also been put to model the quantum threshold voltage of tri gate MOSFET. However it is found that the energy quantization in tri gate devices are mainly due to electronic confinement and hence it is very difficult to develop closed form analytical equations for the threshold voltage. Thus in this work the modeling of tri gate devices have been limited to long channel cases. All the models are validated against the professional numerical simulator.