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Journal articles on the topic 'Asymmetric Double Gate MOSFET'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

Singh, Ajay Kumar. "Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 38, no. 2 (March 4, 2019): 815–28. http://dx.doi.org/10.1108/compel-08-2018-0327.

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Purpose This study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs. Design/methodology/approach This paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach. Findings It is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement. Originality/value Compact Analytical models for undoped symmetric double gate MOSFETs.

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2

Wei, Zhaoxiang, Hao Fu, Xiaowen Yan, Sheng Li, Long Zhang, Jiaxing Wei, Siyang Liu, Weifeng Sun, Weili Wu, and Song Bai. "Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example." Materials 15, no. 2 (January 8, 2022): 457. http://dx.doi.org/10.3390/ma15020457.

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The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (Eox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the Cgd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (Vth) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.

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3

Abebe, H., E. Cumberbatch, H. Morris, V. Tyree, T. Numata, and S. Uno. "Symmetric and Asymmetric Double Gate MOSFET Modeling." JSTS:Journal of Semiconductor Technology and Science 9, no. 4 (December 30, 2009): 225–32. http://dx.doi.org/10.5573/jsts.2009.9.4.225.

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4

Zou, Yuan, Jue Wang, Hongyi Xu, and Hengyu Wang. "Investigation of SiC Trench MOSFETs’ Reliability under Short-Circuit Conditions." Materials 15, no. 2 (January 13, 2022): 598. http://dx.doi.org/10.3390/ma15020598.

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In this paper, the short-circuit robustness of 1200 V silicon carbide (SiC) trench MOSFETs with different gate structures has been investigated. The MOSFETs exhibited different failure modes under different DC bus voltages. For double trench SiC MOSFETs, failure modes are gate failure at lower dc bus voltages and thermal runaway at higher dc bus voltages, while failure modes for asymmetric trench SiC MOSFETs are soft failure and thermal runaway, respectively. The shortcircuit withstanding time (SCWT) of the asymmetric trench MOSFET is higher than that of the double trench MOSFETs. The thermal and mechanical stresses inside the devices during the short-circuit tests have been simulated to probe into the failure mechanisms and reveal the impact of the device structures on the device reliability. Finally, post-failure analysis has been carried out to verify the root causes of the device failure.

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5

Jung, Hakkee. "Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 1 (February 1, 2019): 163. http://dx.doi.org/10.11591/ijece.v9i1.pp163-169.

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Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.

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6

Kumari, Vandana, Manoj Saxena, and Mridula Gupta. "Modeling and Simulation of Nanoscale Lateral Gaussian Doped Channel Asymmetric Double Gate MOSFET." Journal of Nano Research 36 (November 2015): 51–63. http://dx.doi.org/10.4028/www.scientific.net/jnanor.36.51.

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This work presents the drain current model using Evanescent Mode Analysis (EMA) for nanoscale Double Gate MOSFET having Gaussian doping profile along the horizontal direction in the channel i.e. from source to drain region. Due to heavily doped channel, band gap narrowing effect is incorporated in the analytical modeling scheme. The various parameters evaluated in this work using analytical modeling scheme are surface potential, electric field, threshold voltage, sub-threshold slope and drain current. The impact of peak Gaussian doping profile on the drain current and trans-conductance has been demonstrated which are important for assessing the analog performance of the device. The results are also compared with the uniformly doped DG MOSFET. The asymmetric behaviour of Gaussian doped DG MOSFET has also been investigated. In addition to this, digital performance of Gaussian doped DG MOSFET has also been assessed using exhaustive device simulation.

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7

Jung, Hakkee. "Analysis for Gate Oxide Dependent Subthreshold Swing of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 4 (April 30, 2014): 885–90. http://dx.doi.org/10.6109/jkiice.2014.18.4.885.

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8

Jung, Hak Kee. "Projected Range Dependent Tunneling Current of Asymmetric Double Gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 1 (February 1, 2016): 113. http://dx.doi.org/10.11591/ijece.v6i1.9342.

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This study is to analyze the changes of tunneling current according to projected range, a variable of Gaussian function of channel doping function of Asymmetric Double Gate; ADG MOSFET. In MOSFET with channel length below 10 nm, tunneling current occupies a large percentage among off-currents. The increase of tunneling current has a large effect on the characteristics of subthreshold such as threshold voltage movement and the decline of subthreshold swing value, so the accurate analysis of this is being required. To analyze this, potential distribution of series form was obtained using Gaussian distribution function, and using this hermeneutic potential distribution, thermionic emission current and tunneling current making up off-current were obtained. At this point, the effect that the changes of projected range, a variable of Gaussian distribution function, have on the ratio of tunneling current among off-currents was analyzed. As a result, the smaller projected range was, the lower the ratio of tunneling current was. When projected range increased, tunneling current increased largely. Also, it was observed that the value of projected range which the ratio of tunneling current increased changed according to maximum channel doping value, channel length, and channel width.

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9

Jung, Hak Kee. "Projected Range Dependent Tunneling Current of Asymmetric Double Gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 1 (February 1, 2016): 113. http://dx.doi.org/10.11591/ijece.v6i1.pp113-119.

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This study is to analyze the changes of tunneling current according to projected range, a variable of Gaussian function of channel doping function of Asymmetric Double Gate; ADG MOSFET. In MOSFET with channel length below 10 nm, tunneling current occupies a large percentage among off-currents. The increase of tunneling current has a large effect on the characteristics of subthreshold such as threshold voltage movement and the decline of subthreshold swing value, so the accurate analysis of this is being required. To analyze this, potential distribution of series form was obtained using Gaussian distribution function, and using this hermeneutic potential distribution, thermionic emission current and tunneling current making up off-current were obtained. At this point, the effect that the changes of projected range, a variable of Gaussian distribution function, have on the ratio of tunneling current among off-currents was analyzed. As a result, the smaller projected range was, the lower the ratio of tunneling current was. When projected range increased, tunneling current increased largely. Also, it was observed that the value of projected range which the ratio of tunneling current increased changed according to maximum channel doping value, channel length, and channel width.

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10

Jung, Hakkee. "Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (February 1, 2021): 240. http://dx.doi.org/10.11591/ijece.v11i1.pp240-248.

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In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

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11

Jung, Hak Kee, and Sima Dimitrijev. "The Impact of Tunneling on the Subthreshold Swing in Sub-20 nm Asymmetric Double Gate MOSFETs." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 6 (December 1, 2016): 2730. http://dx.doi.org/10.11591/ijece.v6i6.13265.

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<p>This paper analyzes the subthreshold swing in asymmetric double gate MOSFETs with sub-20 nm channel lengths. The analysis of the carrier transport in the subthreshold region of these nano scaled MOSFET includes tunneling as an important additional mechanism to the thermionic emission. It is found that the subthreshold swing is increasing due to tunneling current and that the performance of nano scaled MOSFETs is degraded. The degradation of the subthreshold swing due to tunneling is quantified using analytical potential distribution and Wentzel–Kramers–Brillouin (WKB) approximation in this paper. This analytical approach is verified by two dimensional simulation. It is shown that the degradation of subthreshold swing increases with both reduction of channel length and increase of channel thickness. We also show that the subthreshold swing is increasing in case of different top and bottom gate oxide thicknesses.</p>

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12

Jung, Hak Kee, and Sima Dimitrijev. "The Impact of Tunneling on the Subthreshold Swing in Sub-20 nm Asymmetric Double Gate MOSFETs." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 6 (December 1, 2016): 2730. http://dx.doi.org/10.11591/ijece.v6i6.pp2730-2734.

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<p>This paper analyzes the subthreshold swing in asymmetric double gate MOSFETs with sub-20 nm channel lengths. The analysis of the carrier transport in the subthreshold region of these nano scaled MOSFET includes tunneling as an important additional mechanism to the thermionic emission. It is found that the subthreshold swing is increasing due to tunneling current and that the performance of nano scaled MOSFETs is degraded. The degradation of the subthreshold swing due to tunneling is quantified using analytical potential distribution and Wentzel–Kramers–Brillouin (WKB) approximation in this paper. This analytical approach is verified by two dimensional simulation. It is shown that the degradation of subthreshold swing increases with both reduction of channel length and increase of channel thickness. We also show that the subthreshold swing is increasing in case of different top and bottom gate oxide thicknesses.</p>

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13

Jung, Hakkee. "Bottom Gate Voltage Dependent Threshold Voltage Roll-off of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 6 (June 30, 2014): 1422–28. http://dx.doi.org/10.6109/jkiice.2014.18.6.1422.

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14

Jung, Hakkee. "Subthreshold Swing for Top and Bottom Gate Voltage of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 3 (March 31, 2014): 657–62. http://dx.doi.org/10.6109/jkiice.2014.18.3.657.

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15

Mendiratta, Namrata, Suman Lata Tripathi, and Bhanu Prakash Kolla. "Analysis of gate engineered asymmetric junctionless double gate MOSFET for varying operating conditions." IOP Conference Series: Materials Science and Engineering 872 (June 27, 2020): 012012. http://dx.doi.org/10.1088/1757-899x/872/1/012012.

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16

Jung, Hakkee. "Threshold Voltage Shift for Doping Profile of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 19, no. 4 (April 30, 2015): 903–8. http://dx.doi.org/10.6109/jkiice.2015.19.4.903.

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17

Jung, Hakkee. "Relation of Oxide Thickness and DIBL for Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 20, no. 4 (April 30, 2016): 799–804. http://dx.doi.org/10.6109/jkiice.2016.20.4.799.

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18

El Ghouli, Salim, Jean-Michel Sallese, Andre Juge, Patrick Scheer, and Christophe Lallement. "Transadmittance Efficiency Under NQS Operation in Asymmetric Double Gate FDSOI MOSFET." IEEE Transactions on Electron Devices 66, no. 1 (January 2019): 300–307. http://dx.doi.org/10.1109/ted.2018.2882539.

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19

WANG, YANGYUAN, RU HUANG, JINFENG KANG, and SHENGDONG ZHANG. "HIGHLY SCALED CMOS DEVICE TECHNOLOGIES WITH NEW STRUCTURES AND NEW MATERIALS." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 147–73. http://dx.doi.org/10.1142/s012915640600359x.

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In this paper field effect transistors (FETs) with new materials and new structures are discussed. A thermal robust HfN/HfO 2 gate stack, which can alleviate the confliction between high quality high k material and low EOT, is investigated. EOT of the gate stack can be scaled down to 0.65nm for MOS capacitor and 0.95nm for MOSFET with higher carrier mobility. A new dual metal gate/high k CMOS integration process was demonstrated based on a dummy HfN technique for better high k quality and metal gate integration. Several new double gate FETs are proposed and investigated, including vertical double gate device with an asymmetric graded lightly doped drain (AGLDD) for better short channel behavior, self-aligned electrically separable double gate device for dynamic threshold voltage operation, new 3-D CMOS inverter based on double gate structure and SOI substrate for compact configuration and new full-symmetric DGJFET for 10nm era with greatly relaxed requirement of silicon film thickness and device design simplification.

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20

Jung, Hakkee. "Channel Doping Concentration Dependent Threshold Voltage Movement of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 9 (September 30, 2014): 2183–88. http://dx.doi.org/10.6109/jkiice.2014.18.9.2183.

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21

Jung, Hakkee. "Analysis for Potentail Distribution of Asymmetric Double Gate MOSFET Using Series Function." Journal of the Korea Institute of Information and Communication Engineering 17, no. 11 (November 30, 2013): 2621–26. http://dx.doi.org/10.6109/jkiice.2013.17.11.2621.

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22

Jung, Hakkee. "Analysis of Subthreshold Swing for Channel Doping of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 3 (March 31, 2014): 651–56. http://dx.doi.org/10.6109/jkiice.2014.18.3.651.

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23

Jung, Hakkee. "Analysis of Subthreshold Swing for Channel Length of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 19, no. 2 (February 28, 2015): 401–6. http://dx.doi.org/10.6109/jkiice.2015.19.2.401.

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24

Jung, Hakkee. "Analysis of Conduction-Path Dependent Off-Current for Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 19, no. 3 (March 31, 2015): 575–80. http://dx.doi.org/10.6109/jkiice.2015.19.3.575.

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25

Chattopadhyay, Ankush, Arpan Dasgupta, Rahul Das, Atanu Kundu, and Chandan K. Sarkar. "Effect of spacer dielectric engineering on Asymmetric Source Underlapped Double Gate MOSFET using Gate Stack." Superlattices and Microstructures 101 (January 2017): 87–95. http://dx.doi.org/10.1016/j.spmi.2016.11.024.

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26

Jung, Hakkee. "Analysis of Subthreshold Swing for Doping Distribution Function of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 5 (May 31, 2014): 1143–48. http://dx.doi.org/10.6109/jkiice.2014.18.5.1143.

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27

Jung, Hakkee. "Analysis of Tunneling Current for Bottom Gate Voltage of Sub-10 nm Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 19, no. 1 (January 31, 2015): 163–68. http://dx.doi.org/10.6109/jkiice.2015.19.1.163.

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28

Sivaram, Gollamudi Sai, Shramana Chakraborty, Rahul Das, Arpan Dasgupta, Atanu Kundu, and Chandan K. Sarkar. "Impact of Lateral Straggle on the Analog/RF Performance of Asymmetric Gate Stack Double Gate MOSFET." Superlattices and Microstructures 97 (September 2016): 477–88. http://dx.doi.org/10.1016/j.spmi.2016.07.009.

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29

Jung, Hakkee. "Analysis of Subthreshold Transmission Characteristics for Gate Voltage and Doping Profiles of Asymmetric Double Gate MOSFET." International Journal of Control and Automation 8, no. 3 (March 31, 2015): 31–36. http://dx.doi.org/10.14257/ijca.2015.8.3.05.

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30

Jung, Hakkee. "Analysis of Subthreshold Swing Mechanism by Device Parameter of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 19, no. 1 (January 31, 2015): 156–62. http://dx.doi.org/10.6109/jkiice.2015.19.1.156.

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31

Jung, Hakkee. "Drain Induced Barrier Lowering of Asymmetric Double Gate MOSFET for Channel Doping Profile." Journal of the Korea Institute of Information and Communication Engineering 19, no. 11 (November 30, 2015): 2643–48. http://dx.doi.org/10.6109/jkiice.2015.19.11.2643.

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32

El Ghouli, Salim, Denis Rideau, Frederic Monsieur, Patrick Scheer, Gilles Gouget, Andre Juge, Thierry Poiroux, Jean-Michel Sallese, and Christophe Lallement. "Experimental ${g}_{m}/{I}_{{D}}$ Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET." IEEE Transactions on Electron Devices 65, no. 1 (January 2018): 11–18. http://dx.doi.org/10.1109/ted.2017.2772804.

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33

Ortiz-Conde, Adelmo, and Francisco J. García-Sánchez. "Generic complex-variable potential equation for the undoped asymmetric independent double-gate MOSFET." Solid-State Electronics 57, no. 1 (March 2011): 43–51. http://dx.doi.org/10.1016/j.sse.2010.10.023.

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Jung, Hakkee. "Analysis of Threshold Voltage for Symmetric and Asymmetric Oxide Structure of Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 12 (December 31, 2014): 2939–45. http://dx.doi.org/10.6109/jkiice.2014.18.12.2939.

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Jung, Hakkee. "Tunneling Current of Sub-10 nm Asymmetric Double Gate MOSFET for Channel Doping Concentration." Journal of the Korea Institute of Information and Communication Engineering 19, no. 7 (July 31, 2015): 1617–22. http://dx.doi.org/10.6109/jkiice.2015.19.7.1617.

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36

Kam Hung Yuen, T. Y. Man, A. C. K. Chan, and M. Chan. "A 2-bit MONOS nonvolatile memory cell based on asymmetric double gate MOSFET structure." IEEE Electron Device Letters 24, no. 8 (August 2003): 518–20. http://dx.doi.org/10.1109/led.2003.815157.

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37

Saha, Priyanka, Pritha Banerjee, Dinesh Kumar Dash, and Subir Kumar Sarkar. "Exploring the Short-Channel Characteristics of Asymmetric Junctionless Double-Gate Silicon-on-Nothing MOSFET." Journal of Materials Engineering and Performance 27, no. 6 (March 15, 2018): 2708–12. http://dx.doi.org/10.1007/s11665-018-3281-2.

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Jung, Hakkee. "Dependence of Channel Doping Concentration on Drain Induced Barrier Lowering for Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 20, no. 4 (April 30, 2016): 805–10. http://dx.doi.org/10.6109/jkiice.2016.20.4.805.

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Jung, Hakkee. "Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (February 1, 2021): 232. http://dx.doi.org/10.11591/ijece.v11i1.pp232-239.

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The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs. The characteristics between the drain current and the gate voltage is derived by using the potential distribution model to propose in this paper. In this case, the threshold voltage is defined as the corresponding gate voltage when the drain current is (W/L) × 10-7 A, and the DIBL representing the change in the threshold voltage with respect to the drain voltage is obtained. As a result, we observe the DIBL is proportional to the negative third power of the channel length and the second power of the silicon thickness and linearly proportional to the geometric mean of the top and bottom gate oxide thicknesses, and derive a relation such as DIBL =25.15ηL_g^(-3) t_si^2 √(t_ox1∙t_ox2 ), where η is a static feedback coefficients between 0 and 1. The η is found to be between 0.5 and 1.0 in this model. The DIBL model of this paper has been observed to be in good agreement with the result of other paper, so it can be used in circuit simulation such as SPICE.

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40

Jung, Hakkee. "Relation of Conduction Path and Subthreshold Swing for Doping Profile of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 8 (August 31, 2014): 1925–30. http://dx.doi.org/10.6109/jkiice.2014.18.8.1925.

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41

Jung, Hakkee. "Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric Double Gate MOSFET." TELKOMNIKA (Telecommunication Computing Electronics and Control) 16, no. 5 (October 1, 2018): 2444. http://dx.doi.org/10.12928/telkomnika.v16i5.10248.

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42

Sharan, Neha, and Santanu Mahapatra. "A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry." IEEE Transactions on Electron Devices 61, no. 8 (August 2014): 2732–37. http://dx.doi.org/10.1109/ted.2014.2331191.

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43

Jung, Hakkee. "Analysis of Tunneling Current of Asymmetric Double Gate MOSFET for Ratio of Top and Bottom Gate Oxide Film Thickness." Journal of the Korea Institute of Information and Communication Engineering 20, no. 5 (May 31, 2016): 992–97. http://dx.doi.org/10.6109/jkiice.2016.20.5.992.

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44

Mendiratta, Namrata, Suman Lata Tripathi, Sanjeevikumar Padmanaban, and Eklas Hossain. "Design and Analysis of Heavily Doped n+ Pocket Asymmetrical Junction-Less Double Gate MOSFET for Biomedical Applications." Applied Sciences 10, no. 7 (April 5, 2020): 2499. http://dx.doi.org/10.3390/app10072499.

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The Complementary Metal-Oxide Semiconductor (CMOS) technology has evolved to a great extent and is being used for different applications like environmental, biomedical, radiofrequency and switching, etc. Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) based biosensors are used for detecting various enzymes, molecules, pathogens and antigens efficiently with a less time-consuming process involved in comparison to other options. Early-stage detection of disease is easily possible using Field-Effect Transistor (FET) based biosensors. In this paper, a steep subthreshold heavily doped n+ pocket asymmetrical junctionless MOSFET is designed for biomedical applications by introducing a nanogap cavity region at the gate-oxide interface. The nanogap cavity region is introduced in such a manner that it is sensitive to variation in biomolecules present in the cavity region. The analysis is based on dielectric modulation or changes due to variation in the bio-molecules present in the environment or the human body. The analysis of proposed asymmetrical junctionless MOSFET with nanogap cavity region is carried out with different dielectric materials and variations in cavity length and height inside the gate–oxide interface. Further, this device also showed significant variation for changes in different introduced charged particles or region materials, as simulated through a 2D visual Technology Computer-Aided Design (TCAD) device simulator.

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Jung, Hakkee. "Analysis of Subthreshold Swing for Ratio of Channel Length and Thickness of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 19, no. 3 (March 31, 2015): 581–86. http://dx.doi.org/10.6109/jkiice.2015.19.3.581.

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Jung, Hakkee. "Influence of Tunneling Current on Threshold voltage Shift by Channel Length for Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 20, no. 7 (July 31, 2016): 1311–16. http://dx.doi.org/10.6109/jkiice.2016.20.7.1311.

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Roy, A. S., J. M. Sallese, and C. C. Enz. "A closed-form charge-based expression for drain current in symmetric and asymmetric double gate MOSFET." Solid-State Electronics 50, no. 4 (April 2006): 687–93. http://dx.doi.org/10.1016/j.sse.2006.03.021.

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Bagga, Navjeet, Saheli Sarkhel, and Subir Kumar Sarkar. "Exploring the Asymmetric Characteristics of a Double Gate MOSFET with Linearly Graded Binary Metal Alloy Gate Electrode for Enhanced Performance." IETE Journal of Research 62, no. 6 (April 26, 2016): 786–94. http://dx.doi.org/10.1080/03772063.2016.1176542.

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FOSSUM, JERRY G. "A SIMULATION-BASED PREVIEW OF EXTREMELY SCALED DOUBLE-GATE CMOS DEVICES AND CIRCUITS." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 563–72. http://dx.doi.org/10.1142/s0129156402001460.

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Abstract:

This paper gives a simulation-based preview of device-design issues and performance of extremely scaled DG CMOS. A suite of simulation tools, including a 2D numerical device simulator, a 1D numerical Poisson-Schrödinger solver, and a generic, physics/process-based DG MOSFET compact model in Spice, is applied to both asymmetrical-and symmetrical-gate DG CMOS devices and circuits to provide physical insight at the device and circuit levels. The results give added motivation as well as preliminary guidance for the development of DG CMOS.

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Shin, Yong Hyeon, and Ilgu Yun. "Analytical model for an asymmetric double-gate MOSFET with gate-oxide thickness and flat-band voltage variations in the subthreshold region." Solid-State Electronics 120 (June 2016): 19–24. http://dx.doi.org/10.1016/j.sse.2016.03.002.

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