Dissertations / Theses on the topic 'Asymmetrical Hybrid Multilevel Inverter'

The Queensland University of Technology (QUT) allows the presentation of theses for the Degree of Doctor of Philosophy in the format of published or submitted papers, where such papers have been published, accepted or submitted during the period of candidature. This thesis is composed of ten published /submitted papers and book chapters of which nine have been published and one is under review. This project is financially supported by an Australian Research Council (ARC) Discovery Grant with the aim of investigating multilevel topologies for high quality and high power applications, with specific emphasis on renewable energy systems. The rapid evolution of renewable energy within the last several years has resulted in the design of efficient power converters suitable for medium and high-power applications such as wind turbine and photovoltaic (PV) systems. Today, the industrial trend is moving away from heavy and bulky passive components to power converter systems that use more and more semiconductor elements controlled by powerful processor systems. However, it is hard to connect the traditional converters to the high and medium voltage grids, as a single power switch cannot stand at high voltage. For these reasons, a new family of multilevel inverters has appeared as a solution for working with higher voltage levels. Besides this important feature, multilevel converters have the capability to generate stepped waveforms. Consequently, in comparison with conventional two-level inverters, they present lower switching losses, lower voltage stress across loads, lower electromagnetic interference (EMI) and higher quality output waveforms. These properties enable the connection of renewable energy sources directly to the grid without using expensive, bulky, heavy line transformers. Additionally, they minimize the size of the passive filter and increase the durability of electrical devices. However, multilevel converters have only been utilised in very particular applications, mainly due to the structural limitations, high cost and complexity of the multilevel converter system and control. New developments in the fields of power semiconductor switches and processors will favor the multilevel converters for many other fields of application. The main application for the multilevel converter presented in this work is the front-end power converter in renewable energy systems. Diode-clamped and cascade converters are the most common type of multilevel converters widely used in different renewable energy system applications. However, some drawbacks – such as capacitor voltage imbalance, number of components, and complexity of the control system – still exist, and these are investigated in the framework of this thesis. Various simulations using software simulation tools are undertaken and are used to study different cases. The feasibility of the developments is underlined with a series of experimental results. This thesis is divided into two main sections. The first section focuses on solving the capacitor voltage imbalance for a wide range of applications, and on decreasing the complexity of the control strategy on the inverter side. The idea of using sharing switches at the output structure of the DC-DC front-end converters is proposed to balance the series DC link capacitors. A new family of multioutput DC-DC converters is proposed for renewable energy systems connected to the DC link voltage of diode-clamped converters. The main objective of this type of converter is the sharing of the total output voltage into several series voltage levels using sharing switches. This solves the problems associated with capacitor voltage imbalance in diode-clamped multilevel converters. These converters adjust the variable and unregulated DC voltage generated by renewable energy systems (such as PV) to the desirable series multiple voltage levels at the inverter DC side. A multi-output boost (MOB) converter, with one inductor and series output voltage, is presented. This converter is suitable for renewable energy systems based on diode-clamped converters because it boosts the low output voltage and provides the series capacitor at the output side. A simple control strategy using cross voltage control with internal current loop is presented to obtain the desired voltage levels at the output voltage. The proposed topology and control strategy are validated by simulation and hardware results. Using the idea of voltage sharing switches, the circuit structure of different topologies of multi-output DC-DC converters – or multi-output voltage sharing (MOVS) converters – have been proposed. In order to verify the feasibility of this topology and its application, steady state and dynamic analyses have been carried out. Simulation and experiments using the proposed control strategy have verified the mathematical analysis. The second part of this thesis addresses the second problem of multilevel converters: the need to improve their quality with minimum cost and complexity. This is related to utilising asymmetrical multilevel topologies instead of conventional multilevel converters; this can increase the quality of output waveforms with a minimum number of components. It also allows for a reduction in the cost and complexity of systems while maintaining the same output quality, or for an increase in the quality while maintaining the same cost and complexity. Therefore, the asymmetrical configuration for two common types of multilevel converters – diode-clamped and cascade converters – is investigated. Also, as well as addressing the maximisation of the output voltage resolution, some technical issues – such as adjacent switching vectors – should be taken into account in asymmetrical multilevel configurations to keep the total harmonic distortion (THD) and switching losses to a minimum. Thus, the asymmetrical diode-clamped converter is proposed. An appropriate asymmetrical DC link arrangement is presented for four-level diode-clamped converters by keeping adjacent switching vectors. In this way, five-level inverter performance is achieved for the same level of complexity of the four-level inverter. Dealing with the capacitor voltage imbalance problem in asymmetrical diodeclamped converters has inspired the proposal for two different DC-DC topologies with a suitable control strategy. A Triple-Output Boost (TOB) converter and a Boost 3-Output Voltage Sharing (Boost-3OVS) converter connected to the four-level diode-clamped converter are proposed to arrange the proposed asymmetrical DC link for the high modulation indices and unity power factor. Cascade converters have shown their abilities and strengths in medium and high power applications. Using asymmetrical H-bridge inverters, more voltage levels can be generated in output voltage with the same number of components as the symmetrical converters. The concept of cascading multilevel H-bridge cells is used to propose a fifteen-level cascade inverter using a four-level H-bridge symmetrical diode-clamped converter, cascaded with classical two-level Hbridge inverters. A DC voltage ratio of cells is presented to obtain maximum voltage levels on output voltage, with adjacent switching vectors between all possible voltage levels; this can minimize the switching losses. This structure can save five isolated DC sources and twelve switches in comparison to conventional cascade converters with series two-level H bridge inverters. To increase the quality in presented hybrid topology with minimum number of components, a new cascade inverter is verified by cascading an asymmetrical four-level H-bridge diode-clamped inverter. An inverter with nineteen-level performance was achieved. This synthesizes more voltage levels with lower voltage and current THD, rather than using a symmetrical diode-clamped inverter with the same configuration and equivalent number of power components. Two different predictive current control methods for the switching states selection are proposed to minimise either losses or THD of voltage in hybrid converters. High voltage spikes at switching time in experimental results and investigation of a diode-clamped inverter structure raised another problem associated with high-level high voltage multilevel converters. Power switching components with fast switching, combined with hard switched-converters, produce high di/dt during turn off time. Thus, stray inductance of interconnections becomes an important issue and raises overvoltage and EMI issues correlated to the number of components. Planar busbar is a good candidate to reduce interconnection inductance in high power inverters compared with cables. The effect of different transient current loops on busbar physical structure of the high-voltage highlevel diode-clamped converters is highlighted. Design considerations of proper planar busbar are also presented to optimise the overall design of diode-clamped converters.

Las topologías de circuitos inversores multinivel pueden trabajar a tensiones y potencias mayores que las alcanzadas por convertidores convencionales de dos niveles. Además, la conversión multinivel reduce la distorsión armónica de las variables de salida y en algunos casos, a pesar del aumento de elementos de conmutación, también reduce las pérdidas de conversión al incrementarse el número de niveles. La reducción de distorsión alcanzada por el número de niveles puede aprovecharse para reducir las pérdidas de conmutación disminuyendo la frecuencia de las señales portadoras. Para reducir aún más esta frecuencia sin degradar el espectro, nosotros controlamos las pendientes de las portadoras triangulares.
Primero se han desarrollado dos modelos analíticos para predecir el espectro del voltage de salida, dependiendo de: el índice de modulación MA, la razón de distribución de voltaje K de las fuentes de alimentación , y las cuatro pendientes de las portadoras{r1, r2, r3, r4}. El primer modelo considera el Muestreo Natural y se basa en Series Dobles de Fourier (SDF) mientras que el segundo modelo, utiliza la Serie Sencilla de Fourier (SSF) introduciendo el concepto de Muestreo Pseudo-Natural, una aproximación digital de la modulación natural. Ambos modelos son programados en Matlab, verificados con Pspice y validados con un prototipo experimental que contiene un modulador digital implementado con DSP.
La concordancia entre las modulaciones natural y pseudo-natural, asi como entre sus respectivos modelos, es aprovechada por un algorítmo genético (AG) donde la THD es la función costo a reducir. Después de varios ensayos y de sintonizar el AG, se genera una matriz que contiene conjuntos de portadoras optimizadas dentro un rango específico de las variables {MA,K} y es probada con un segundo prototipo en lazo cerrado. Un lazo lento digital modifica las portadoras creadas por un dsPIC en modulaciones PWM; estas son demoduladas y sus amplitudes corregidas por un lazo de acción anticipada. Estas portadoras se comparan con una referencia sinusoidal que a su vez es modificada por variables de estado, generando finalmente la modulación multinivel en lazo cerrado. Los resultados finales demuestran la fiabilidad de la reducción de armónicos usando la programación de las pendientes de las portadoras.
Palabras claves: inversor multinivel, PWM, distorsión armónica, modelo espectral, pendiente de portadora, conjunto de portadoras, distribución de niveles, Serie Doble de Fourier, Serie Simple de Fourier, muestreo natural, muestreo regular, muestreo pseudo-natural , Algoritmos Genéticos.
Multilevel inverter (MI) topologies can work at higher voltage and higher power than conventional two-level converters. In addition, multilevel conversion reduces the output variables harmonic distortion and, sometimes, in spite of the devices-count increment, the conversion losses can also decrease by increasing the number of levels. The harmonic distortion reduction achieved by increasing the number of levels, can be used to further reducing the switching losses by decreasing the inverter carrier frequencies. To reduce even more the switching frequency without degrading output spectrum, we control the triangular carrier waveforms slopes.
First, to achieve this target, two analytical models have been created in order to predict the inverter output voltage spectrum, depending on diverse parameters: the amplitude modulation index MA, the voltage distribution K of the inverter input sources, and the four carrier slopes {r1, r2, r3, r4}. The first model considers Natural Sampling and is based on Double Fourier Series (DFS) whereas the second model based on Simple Fourier Series (SFS), introduces the concept of Pseudo-Natural Sampling, as a digital approximation of the natural modulation. Both models are programmed in Matlab, verified with Pspice simulations and validated with a first experimental prototype with a DSP digital modulator.
The good agreement between natural and pseudo-natural modulations, as well as their respective DFS and SFS models, is exploited by a Genetic Algorithm (GA) application where THD is the cost function to minimize. After testing and properly tuning the GA, a framework matrix containing the optimized carriers set for a specific range of variables {MA,K} is generated and then, tested with a second, closed-loop prototype. A slow digital loop modifies the carrier slopes created by dsPIC microcontroller as PWM modulations, whose amplitude, once demodulated, are affected by a feed-forward loop. These carriers, compared with a sinusoidal reference, state-feedback modified, generate finally the closed-loop multilevel modulation. The final results demonstrates the feasibility of harmonic reduction by means of carrier slopes programming.
Keywords: multilevel inverter, PWM, harmonic distortion, spectral modeling, carrier slope, carriers set, level distribution, Double Fourier Series, Simple Fourier Series, natural sampling, regular sampling, pseudo-natural sampling, Genetic Algorithms.

The proposed hybrid system generates AC power by combining solar and wind energy converted by a doubly-fed induction generator (DFIG). The DFIG, driven by a wind turbine, needs rotor excitation so the stator can supply a load or the grid. In a variable-speed wind energy system, the stator voltage and its frequency vary with wind speed, and in order to keep them constant, variable-voltage and variable-frequency rotor excitation is to be provided. A power conversion unit supplies the rotor, drawing power either from AC mains or from a PV panel depending on their availability. It consists of a multilevel inverter which gives lower harmonic distortion in the stator voltage. Maximum power point tracking techniques have been implemented for both wind and solar power. The complete hybrid renewable energy system is implemented in a PSIM-Simulink interface and the wind energy conversion portion is realized in hardware using dSPACE controller board.

This thesis investigates a novel DC/AC resonant inverter of Induction Heating (IH) system presenting a Multilevel Neutral Point Clamped (MNPCI) topology, as a new part of power supply design. The main function of the prototype is to provide a maximum and steady state power transfer from converter to the resonant load tank, by achieving zero current switching (ZCS) with selecting the best design of load tank topology, and utilizing the advantage aspects of both the Voltage Fed Inverter (VFI) and Current Fed Inverter (CFI) kinds, therefore it can considered as a hybrid-inverter (HVCFI) category . The new design benefits from series resonant inverter design through using two bulk voltage source capacitors to feed a constant voltage delivery to the MNPCI inverter with half the DC rail voltage to decrease the switching losses and mitigate the over voltage surge occurred in inverter switches during operation which may cause damage when dealing with high power systems. Besides, the design profits from the resonant load topology of parallel resonant inverter, through using the LLC resonant load tank. The design gives the advantage of having an output current gain value of about Quality Factor (Q) times the inverter current and absorbs the parasitic components. On the contrary, decreasing inverter current means decreasing the switching frequency and thus, decreasing the switching losses of the system. This aspect increases the output power, which increases the heating efficiency. In order for the proposed system to be more reliable and matches the characteristics of IH process , the prototype is modelled with a variable LLC topology instead of fixed load parameters with achieving soft switching mode of ZCS and zero voltage switching (ZVS) at all load conditions and a tiny phase shift angle between output current and voltage, which might be neglected. To achieve the goal of reducing harmonic distortion, a new harmonic control modulation is introduced, by controlling the ON switching time to obtain minimum Total Harmonic Distortion (THD) content accompanied with optimum power for heating energy.

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior
Este trabalho apresenta uma topologia de inversor multinÃvel hÃbrido simÃtrico trifÃsico de cinco nÃveis, concebido a partir das estruturas meia ponte e inversor com grampeamento ativo do neutro, adequado para aplicaÃÃes com alta tensÃo e alta potÃncia. SÃo apresentados os possÃveis estados de comutaÃÃo, lÃgica de acionamento, cÃlculo dos esforÃos nos semicondutores, assim como um estudo de perdas. Duas estratÃgias de modulaÃÃo sÃo selecionadas possibilitando a operaÃÃo concomitante de metade dos interruptores em baixa frequÃncia (60 Hz) e a outra em alta frequÃncia (1020 Hz), reduzindo o nÃmero de comutaÃÃes, consequentemente as perdas nos semicondutores e o conteÃdo harmÃnico da tensÃo de saÃda. Para validar a proposta, foi desenvolvido um protÃtipo com potÃncia de 7,5 kVA e tensÃo de saÃda eficaz de linha 380 V. AlÃm disso, à apresentada a implementaÃÃo de ambas as modulaÃÃes no dispositivo lÃgico programÃvel escolhido, FPGA. Os resultados experimentais da estrutura trifÃsica validam a topologia proposta. A estrutura, operando com a modulaÃÃo baseada na PD-PWM, apresentou DHT de 29,71% e WTHD de 1,93%, enquanto que a baseada na CSV-PWM apresentou DHT de 38,45% e WTHD de 7,21%. AlÃm disso, o rendimento da estrutura proposta à superior se comparado ao da topologia Half-Bridge/NPC, conforme esperado em funÃÃo das perdas na estrutura Half-Bridge/NPC serem maiores e mal distribuÃdas.
This work presents a new topology of a hybrid five-level inverter, conceived from the halfbridge and active neutral point clamped structures, suitable for high-voltage, high-power applications. The possible commutation stages, the switching drive logic, the semiconductors stresses mathematical analysis, and the losses study are presented. Two modulation techniques were selected in order to allow low-frequency (60 Hz) switches operate together with high-frequency switches (1020 Hz), reducing the number of commutations and, consequently, the overall losses and the output voltage total harmonic distortion. In order to validate the proposal, it was developed a 7.5 kVA prototype and AC line output voltage of 380 V. The digital implementation from both modulation techniques on the chosen programmable logic device FPGA is also presented. The experimental results relative to the three-phase structure validate the proposed topology. The topology, operating with the modulation based on Sinusoidal In-Phase Disposition - PWM, presented a THD of 29.71%, and WTHD of 1.93%, while the one based on the Centered Space Vector - PWM presented a THD of 38.45%, and a WTHD of 7.21%. Besides, the overall efficiency is superior when compared to the Half-Bridge/NPC topology, as expected, due to the fact that losses on this structure are higher and misdistributed.

Ces dernières années, l’utilisation des systèmes de transport aérien s'est considérablement amplifié. Par conséquent, les considérations environnementales actuelles poussent à réduire leur utilisation. Des projets tels que Clean Sky 2 tentent d’apporter une réponse à ce problème, en proposant une réduction des émissions de CO2 et des nuisances sonores. Le recours à l’hybridation de la propulsion des avions réduirait ces émissions en réduisant la taille et la masse des systèmes et en utilisant des systèmes électriques plus efficaces ce qui permettrai d’augmenter le nombre de passager. Cela permettrait de réduire la consommation de carburant et donc les émissions polluantes. Ces travaux s'inscrivent dans le cadre du projet européen HASTECS Clean Sky 2 qui vise à optimiser l'ensemble de la chaîne électrique de l'avion à propulsion hybride en intégrant toutes les contraintes aéronautiques telles que les décharges partielles pour les équipements électriques placés en zone non pressurisée. Le projet HASTECS s'est fixé le défi de doubler la densité de puissance des machines électriques pour passer de 5 kW/kg à 10 kW/kg, y compris leur refroidissement, tandis que pour l'électronique de puissance, avec son système de refroidissement, le but sera de passer à 15 kW/kg en 2025 et à 25 kW/kg en 2035. Pour augmenter la densité de puissance, la masse du système de refroidissement doit être diminuée dans un premier temps soit en optimisant ses composants, ce qui est fait par le 4ème lot de travail (WP4), soit en réduisant les pertes. La réduction des pertes de l'onduleur pourrait être obtenue en utilisant de semi-conducteurs de faible calibre en tension, en jouant sur les stratégies de modulation ou en utilisant des semi-conducteurs plus performants. La première option peut être faite en utilisant des architectures multi-niveaux pour éviter l'association en série direct. Contrairement à l'association directe en série, l'association parallèle est plus facile à gérer en termes de commande de interrupteurs, ce qui a été autorisé dans nos études. Plusieurs topologies d'onduleurs (topologies à 2, 3 et 5 niveaux) et stratégies de modulation (PWM, injection de troisième harmonique, PWM discontinu et pleine onde) ont été comparées en utilisant plusieurs technologies de semi-conducteurs pour choisir la solution la plus performante en termes de rendement et de densité de puissance. Pour le profil de mission considéré, l'onduleur pourrait être dimensionné pour le point de puissance maximum (décollage) ou la phase de vol la plus longue (croisière). Une étude comparative des stratégies de modulation a été réalisée pour mettre en évidence la structure et la modulation présentant les meilleures performances afin de minimiser les pertes pour les points de dimensionnement choisis en utilisant les topologies les plus intéressantes pour le profil de mission étudié en utilisant deux configurations différentes de bobinage du moteur électrique proposées par le WP1
Recently, the use of air transport systems has increased considerably. Therefore, the current environmental considerations are pushing to reduce their ecological impact. Projects such as Clean Sky 2 provide an answer to this problem, by proposing a reduction in CO2 emissions and noise pollution. The development of a hybrid-electric aircraft would reduce these emissions by reducing the size and weight of the systems and using more efficient electrical systems. This would reduce fuel consumption and therefore pollutant emissions. This work takes part into HASTECS Clean Sky 2 European project which aims to optimize the complete electrical chain of the hybrid aircraft integrating all aeronautical constraints such as partial discharges for electrical equipment placed in the non-pressurized zone. HASTECS project has set itself the challenge of doubling the specific power of electric machines including their cooling from 5 kW/kg to 10 kW/kg, while the power electronics, with their cooling system, would evolve from 15 kW/kg in 2025 to 25 kW/kg in 2035. To increase the specific power, the cooling system mass should be decreased either by optimizing its components which is done by the 4th work package (WP4) or by reducing power losses. Inverter losses reduction could be achieved by using small voltage rating components, by playing on modulation strategies or by using more performant semiconductors. The first option could be done by using multilevel architectures to avoid the direct series association. Unlike direct series association, the parallel one is easier to manage in terms of switches command so it was allowed in our studies. Several inverter topologies (2-, 3- and 5-level topologies) and modulation strategies (PWM, third harmonic injection, discontinuous PWM and full-wave) were compared using several semiconductors generations to choose the most performant solution in terms of efficiency and specific power. For the considered mission profile, the inverter could be sized for the maximum power point (takeoff) or the most extended flight phase (cruise). A comparative study of modulation strategies was carried out to highlight the structure and modulation presenting the best performance to minimize the losses for the chosen sizing points using most interesting topologies for the studied mission profile using two electrical motor windings configurations proposed by WP1

This thesis reports on the investigations, simulations and analyses of novel power electronics topologies and control strategies. The research is financed by an Australian Research Council (ARC) Linkage (07-09) grant. Therefore, in addition to developing original research and contributing to the available knowledge of power electronics, it also contributes to the design of a DC-DC converter for specific application to the auxiliary power supply in electric trains. Specifically, in this regard, it contributes to the design of a 7.5 kW DC-DC converter for the industrial partner (Schaffler and Associates Ltd) who supported this project. As the thesis is formatted as a ‘thesis by publication’, the contents are organized around published papers. The research has resulted in eleven papers, including seven peer reviewed and published conference papers, one published journal paper, two journal papers accepted for publication and one submitted journal paper (provisionally accepted subject to few changes). In this research, several novel DC-DC converter topologies are introduced, analysed, and tested. The similarity of all of the topologies devised lies in their ‘current circulating’ switching state, which allows them to store some energy in the inductor, as extra inductor current. The stored energy may be applied to enhance the performance of the converter in the occurrence of load current or input voltage disturbances. In addition, when there is an alternating load current, the ability to store energy allows the converter to perform satisfactorily despite frequently and highly varying load current. In this research, the capability of current storage has been utilised to design topologies for specific applications, and the enhancement of the performance of the considered applications has been illustrated. The simplest DC-DC converter topology, which has a ‘current circulating’ switching state, is the Positive Buck-Boost (PBB) converter (also known as the non-inverting Buck-Boost converter). Usually, the topology of the PBB converter is operating as a Buck or a Boost converter in applications with widely varying input voltage or output reference voltage. For example, in electric railways (the application of our industrial partner), the overhead line voltage alternates from 1000VDC to 500VDC and the required regulated voltage is 600VDC. In the course of this research, our industrial partner (Schaffler and Associates Ltd) industrialized a PBB converter–the ‘Mudo converter’–operating at 7.5 kW. Programming the onboard DSP and testing the PBB converter in experimental and nominal power and voltage was part of this research program. In the earlier stages of this research, the advantages and drawbacks of utilization of the ‘current circulating’ switching state in the positive Buck-Boost converter were investigated. In brief, the advantages were found to be robustness against input voltage and current load disturbances, and the drawback was extra conduction and switching loss. Although the robustness against disturbances is desirable for many applications, the price of energy loss must be minimized to attract attention to the utilization of the PBB converter. In further stages of this research, two novel control strategies for different applications were devised to minimise the extra energy loss while the advantages of the positive Buck-Boost converter were fully utilized. The first strategy is Smart Load Controller (SLC) for applications with pre-knowledge or predictability of input voltage and/or load current disturbances. A convenient example of these applications is electric/hybrid cars where a master controller commands all changes in loads and voltage sources. Therefore, the master controller has a pre-knowledge of the load and input voltage disturbances so it can apply the SLC strategy to utilize robustness of the PBB converter. Another strategy aiming to minimise energy loss and maximise the robustness in the face of disturbance is developed to cover applications with unexpected disturbances. This strategy is named Dynamic Hysteresis Band (DHB), and is used to manipulate the hysteresis band height after occurrence of disturbance to reduce dynamics of the output voltage. When no disturbance has occurred, the PBB converter works with minimum inductor current and minimum energy loss. New topologies based on the PBB converter have been introduced to address input voltage disturbances for different onboard applications. The research shows that the performance of applications of symmetrical/asymmetrical multi-level diode-clamped inverters, DC-networks, and linear-assisted RF amplifiers may be enhanced by the utilization of topologies based on the PBB converter. Multi-level diode-clamped inverters have the problem of DC-link voltage balancing when the power factor of their load closes to unity. This research has shown that this problem may be solved with a suitable multi-output DC-DC converter supplying DClink capacitors. Furthermore, the multi-level diode-clamped inverters supplied with asymmetrical DC-link voltages may improve the quality of load voltage and reduce the level of Electromagnetic Interference (EMI). Mathematical analyses and experiments on supplying symmetrical and asymmetrical multi-level inverters by specifically designed multi-output DC-DC converters have been reported in two journal papers. Another application in which the system performance can be improved by utilization of the ‘current circulating’ switching state is linear-assisted RF amplifiers in communicational receivers. The concept of ‘linear-assisted’ is to divide the signal into two frequency domains: low frequency, which should be amplified by a switching circuit; and the high frequency domain, which should be amplified by a linear amplifier. The objective is to minimize the overall power loss. This research suggests using the current storage capacity of a PBB based converter to increase its bandwidth, and to increase the domain of the switching converter. The PBB converter addresses the industrial demand for a DC-DC converter for the application of auxiliary power supply of a typical electric train. However, after testing the industrial prototype of the PBB converter, there were some voltage and current spikes because of switching. To attenuate this problem without significantly increasing the switching loss, the idea of Active Gate Signalling (AGS) is presented. AGS suggests a smart gate driver that selectively controls the switching process to reduce voltage/current spikes, without unacceptable reduction in the efficiency of switching.

Multilevel converters are becoming more and more popular, overcoming some key limitations of conventional two-level structures in handling medium voltages and high voltage gradients. Today they provide the ground for the realization of high efficiency energy conversion systems for medium voltage applications, such as pumps, compressors, extruders, fans, grinding mills, rolling mills, conveyors, crushers, blast furnace blowers, gas turbine starters, mixers, mine hoists, reactive power compensation, marine propulsion, wind energy conversion, and railway traction. A detailed overview of multilevel converters is provided in Chapter 1, while, the state of the art of Open-end Winding Systems is described in Chapter 2. The last systems can be considered as special multilevel inverter structures, tailored around an electrical machine fed from both the ends of the stator, or primary, winding. Overvoltage phenomena generated in industrial motor drives at motor terminals by long feeding cables are investigated in Chapter 3 and an Open-end Winding configuration approach is presented to actively mitigate them. Moreover, an adaptive algorithm is described to make independent the active overvoltage mitigation from system parameters. The main contribution of this work is the development of a new multilevel inverter topology, the Asymmetrical Hybrid Multilevel Inverter (AHMLI), which is introduced in Chapter 4. According to the AHMLI structure, an open-end winding machine (motor, generator or transformer) is supplied on one end by a main multilevel converter, fully managing the active power stream, and, on the other end by an auxiliary two level inverter. This acts as an active power filter, suitably shaping the electrical machine phase current. A mathematical analysis of the proposed structure is first provided, followed by an exhaustive comparison between AHMLI and conventional multilevel structures, emphasizing advantages in terms of efficiency and output current THD. Voltage and current control systems, optimally coping with key characteristics of the AHMLI structure are carried out and an original input capacitors voltage equalization technique is also presented. The application of the AHMLI concept to industrial induction motor drives is then evaluated by simulation and experimental test. A possible exploitation of the AHMLI approach in the realization of photovoltaic and wind plants, as well as STATCOM devices is also assessed. Moreover, a high efficiency three phase rectifier for high speed generation systems exploiting the AHMLI configuration is carried out. Finally, the application of the AHMLI approach to Multiple Motor Drive systems is proposed in Chapter 5. Two new topologies are presented, namely: Open-end Winding Multi Motor Single Converter (MMSC) and Open-end Winding Multi Motor Multi Converter (MMMC). Both configurations exploit the AHMLI structure but the MMMC exploits a five-leg two level inverter to independently control the stator currents of two induction motors.

碩士
國立虎尾科技大學
機械與機電工程研究所
98
This thesis proposed a hybrid multi-level inverters having 3 inverters in series with distinct dc link voltages to generate 13 voltage levels in order to reduce output voltage and current distortion and power switch stress and switching frequency. Therefore, EMI (Electro Magnetic Interference) can be alleviated due to lower switching frequency. The experiments are conducted to show the performance of the proposed hybrid multi-level inverters that in stand-alone system to reduce the voltage distortion significantly in load-variation, rectifier load, and phase-controlled load conditions; for the grid-tied system, the output current is closed to sinusoidal waveform and current ripple is reduced as well.

Dissertação de mestrado integrado em Engenharia Eletrónica e de Computadores
A exigência na qualidade da forma de onda sintetizada pelos inversores de eletrónica de potência é cada vez maior, estando esta qualidade associada a um melhor funcionamento e a um maior tempo de vida por parte das cargas e sistemas associados aos inversores. A melhoria na qualidade das formas de onda geradas pelos inversores tem sido conseguida maioritariamente através do aumento da frequência de comutação dos semicondutores. Esta estratégia provoca perdas de comutação mais elevadas, maior stress aplicado ao semicondutor e um aumento das interferências eletromagnéticas. Outro método que começa a ser utilizado para melhorar a qualidade das formas de onda dos inversores é o aumento do número de níveis na forma de onda gerada à saída. Este método utiliza inversores com topologias multinível, podendo aumentar a qualidade das formas de onda produzidas sem as desvantagens da utilização de uma frequência de comutação muito alta. Inicialmente o uso dos inversores multinível era limitado a aplicações de tensões muito elevadas, devido ao custo elevado dos semicondutores e ao baixo poder de processamento dos controladores digitais existentes. Com a evolução das tecnologias é cada vez mais viável a utilização deste tipo de topologias em aplicações de baixa tensão que necessitam de uma foram de onda com uma distorção mínima. Esta dissertação de mestrado visa o desenvolvimento de um inversor multinível monofásico para uma aplicação de baixa tensão, atribuindo maior foco à qualidade da forma de onda a sintetizar. Para tal, foi escolhida uma aplicação de Qualidade de Energia Elétrica (QEE) nomeadamente um Filtro Ativo de Potência Paralelo (FAPP). A efetividade da compensação por parte do FAPP depende muito da qualidade das correntes sintetizadas. Sendo assim, o principal objetivo é a sintetização de correntes de compensação com elevada qualidade e com baixo ripple. Para tal, foi utilizada uma topologia de cinco níveis, cuja diferença de tensão entre níveis é menor quando comparada com um inversor convencional de 2 níveis, reduzindo assim o ripple da corrente produzida sem necessidade de aumentar os filtros passivos de saída. No decorrer deste trabalho foi realizado um estudo bibliográfico sobre inversores multinível e filtros ativos de potência. Posteriormente, foram realizadas simulações computacionais para validar a topologia a implementar. Por último, foi desenvolvido um protótipo laboratorial e foram realizados testes práticos com diferentes cargas, para comprovar o funcionamento adequado do FAPP.
The quality requirements of the signals synthesized by power inverters are increasing, being this quality associated to a better performance and longer lifetime of the loads and systems related to the inverters. The improvement in the quality of the inverters signal has been achieved by increasing the switching frequency. This strategy leads to high losses, greater stress applied to semiconductor and an increase of electromagnetic interference. Another method that is beginning to be used to improve the quality of the signals produced by power inverters is the increase in the number of levels of the output signals. This method uses inverters with multilevel topologies, allowing increase the quality of the produced signals without the disadvantages of the very high switching frequency. Initially the use of multilevel inverters was limited to high power applications, due to the high cost of semiconductors and low processing power of digital controllers. With the evolution of technologies, the use of multilevel topologies turns out to be more reliable in low voltage applications requiring signals with very low distortion. This dissertation aims at the development of a single-phase multilevel inverter for low-voltage application, giving greater focus to the quality of the synthesized signals. So, a power quality application was chosen, more precisely a Shunt Active Power Filter (SAPF). The effectiveness of a SAPF depends on the quality of the synthesized high quality and low ripple. To accomplish with this requirements, a five-level topology was selected, whose voltage difference between levels is less when compared to a conventional two level inverter, thus reducing the ripple without increasing the output passive filters. Along the work, a bibliographical study on multilevel inverters and active power filters was done. Later, simulations were performed to validate the topology, in order to proceed to its implementation. Finally, a laboratorial prototype has been developed and practical tests were carried out with different loads, to demonstrate the SAPF proper operation.

Today many efforts are made to research and use new energy sources because the potential for an energy crisis is increasing. Multilevel converters have gained much attention in the area of energy distribution and control due to its advantages in high power applications with low harmonics. They not only achieve high power ratings, but also enable the use of renewable energy sources. The general function of the multilevel converter is to synthesize a desired high voltage from several levels of dc voltages that can be batteries, fuel cells, etc. This dissertation presents a new hybrid multilevel inverter for voltage boost. The inverter consists of a standard 3-leg inverter (one leg for each phase) and H-bridge in series with each inverter leg. It can use only a single DC power source to supply a standard 3-leg inverter along with three full H-bridges supplied by capacitors or batteries. The proposed inverter could be applied in hybrid electric vehicles (HEVs) and fuel cell based hybrid electric vehicles (FCVs). It is of voltage boosting capability and eliminates the magnetics. This feature makes it suitable for the motor running from low to high power mode. In addition to hybrid electric vehicle applications, this paper also presents an application where the hybrid multilevel inverter acts as a renewable energy utility interface. In this dissertation, the structure, operation principle, and modulation control schemes of the proposed hybrid multilevel inverter are introduced. Simulation models and results are described and analyzed. An experimental 5 kW prototype inverter is built and tested.

碩士
國立臺灣科技大學
電機工程系
100
This thesis proposes a hybrid modulation strategy, phase-shifted strategy and selective harmonic elimination PWM (SHE PWM) strategy, for the cascaded H-bridge multilevel inverter. The SHE PWM strategy controls the fundamental voltages and eliminates eleventh, thirteenth, twenty-third and twenty-fifth order harmonics with a number of notch angles. These notch angles can be calculated through Fourier analysis. The waveform characters of quarter-wave and half-wave symmetries are useful for solving the notch angles. To set the phase shift of the H-bridge module inverter output fundamental voltages and input DC sources value, the phase-shifted strategy generates stair-case multilevel waveform. The harmonics of 6(2n-1)±1 orders, n=1, 2, 3, ..., in the line to line voltage are eliminated by the phase-shifted strategy unaltered control frequency. Reducing harmonics achieve better power quality. Simulations and experiments taken from a laboratory prototype of three-module asymmetric cascaded H-bridge multilevel inverter are presented to prove the validity and practicability of the hybrid modulation strategy

碩士
國立雲林科技大學
電機工程系碩士班
93
In recent years the development of multilevel inverter has been gradually matured for high power and high voltage applications, such as high-voltage DC transmission and high-speed railroad system. Based on the manufacture technology of power semiconductors, the power switches have large voltage and current stresses and it makes the application of multilevel inverter is achieved. Multilevel inverter can use low voltage devices to implement high or medium voltage applications. The more voltage levels are generated on the inverter such that the voltage harmonic is reduced at the inverter output side. This thesis presents a new multilevel inverter topology to implement the function of dynamic voltage restorer. Therefore the power quality at the load side can be improved by the adopted circuit topology. The system performance is verified by the computer simulation based on the MATLAB/Simulink software package.

D. Tech. Electrical Engineering.
Aims to : 1. Derive the analytical solutions for describing the spectral characteristics of multicarrier based multilevel PWM inverter using double Fourier transform. 2. To carry out a comprehensive modelling of a cascaded NPC/H-bridge for PV-Grid application. 3. To integrate the Cascaded NPC/H-bridge inverter, grid and PV model and analyze the power flow characteristics for varying PV source current and voltage. Detailed analysis of PV and development of MPPT algorithm are not part of this thesis. 4. To develop a novel hybrid phase shifted PWM control algorithm and test its superior harmonic suppression in MATLAB simulation. 5. To compare the developed control algorithm with conventional multicarrier approach in terms of harmonic suppression and component count 6. To develop a control scheme that is capable of injecting maximum power into the grid from the model at different environmental conditions. 7. To explore and develop analytical tools for DC- link voltage control of the model. 8. To design and built a scaled down. 9 Level cascaded NPC/H-bridge inverter for grid connected application.

Multilevel inverters play a major role in the modern day medium and high power energy conversion processes. The classic two level voltage source inverter generates PWM pole voltage output having two levels with strong fundamental component and harmonics centered around the switching frequency and its multiples. With higher switching frequency, its components can be easily filtered and results in better Total harmonic distortion (THD) output voltage and current. But with higher switching frequency, switching loss of power devices increases and electromagnetic interferences also increases. Also in two level inverter, pole voltage switches between zero and DC bus volt-age Vdc. This switching results in high dv=dt and causes EMI and increased stress on the motor winding insulation. The attractive features of multilevel inverters compared to a two level inverter are reduced switching frequency, reduced switching loss, improved volt-age and current THD, reduced dv=dt, etc. Because of these reasons, multilevel invertersultilevelinvertersplayamajorroleinthemoderndaymediumandhighpower find application in electric motor drives, transmission and distribution of power, transportation, traction, distributed generation, renewable energy systems like photo voltaic, hydel power, energy management, power quality, electric vehicle applications, etc. AC motor driven applications are consuming the significant part of the generated electrical energy (more than 60%) around the world. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low with lower out-put voltage dv=dt. Also by using multilevel inverters, the common mode voltage (CMV) switching can be made zero and associated motor bearing failure can be mitigated. For multilevel inverter topologies, as the number of level increases, the power circuit becomes more complex by the increase in the number of DC power supplies, capacitors, switching devices and associated control circuitry. The main focus of development in multilevel inverter for medium and high power applications is to obtain an optimized number of voltage levels with reduced number of switching devices, capacitors and DC power sources. In this thesis, a new hybrid seven level inverter topology with a single DC supply is proposed with reduced switch count. The inverter is realized by cascading two three level flying capacitor inverters with a half bridge module. Compared to the conventional seven level inverter topologies, the proposed inverter topology uses lesser number of semiconductor devices, capacitors and DC power supplies for its operation. For this topology, capacitor voltage balancing is possible for entire modulation range irrespective of the load power factor. Also capacitor voltage can be controlled over a switching cycle and this result in lowering the capacitor sizing for the proposed topology. A simple hysteresis band based capacitor voltage balancing scheme is implemented for the inverter topology. For a voltage source inverter fed induction motor drive system, the inverter pole voltage is the sum of motor phase voltage and common mode voltage. In induction motors, there exists a parasitic capacitance between stator winding and stator iron, and between stator winding and rotor iron. Common mode voltage with significant magnitude and high frequency switching causes leakage current through these parasitic capacitances and motor bearings. This leakage current can cause ash over of bearing lubricant and corrosion of ball bearings, resulting in an early mechanical failure of the drive system. In this thesis, analysis of extending the linear modulation range of a general n-level inverter by allowing reduced magnitude of common mode voltage (CMV) switching (only Vdc/18) is presented. A new hybrid seven level inverter topology, with a single DC supply and with reduced common mode voltage (CMV) switching is presented in this thesis for the first time. Inverter is operated with zero CMV for modulation index less than 86% and is operated with a CMV magnitude of Vdc/18 to extend the linear modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilizing the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology. In recent years, model predictive control (MPC) using the system model has proved to be a good choice for the control of power converter and motor drive applications. MPC predicts system behavior using a system model and current system state. For cascaded multilevel inverter topologies with a single DC supply, closed loop capacitor voltage control is necessary for proper operation. This thesis presents zero and reduced common mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state which minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96% the inverter can operate with reduced CMV magnitude ( Vdc/18) and reduced CMV switching frequency using the new space-vector PWM (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop V/f control scheme. The operation of a two level inverter in the over-modulation region (maximum peak phase fundamental output of inverter is greater than 0:577Vdc) results in lower order harmonics in the inverter output voltage. This lower order harmonics (mainly 5th, 7th, 11th, and 13th) causes electromagnetic torque ripple in motor drive applications. Also these harmonics causes extra losses and adversely affects the efficiency of the drive system. Also inverter control becomes non linear and special control algorithms are required for inverter operation in the over modulation region. In conventional schemes, maximum fundamental output voltage possible is 0:637Vdc. In that case inverter is operated in a square wave mode, also called six-step mode. This operation results in high dv=dt for the inverter output voltage. With multilevel inverters also, the inverter operation with peak phase fundamental output voltage above 0:577Vdc results in lower order harmonics in the inverter output voltage and results in electromagnetic torque pulsation. In this thesis, a new space vector PWM (SVPWM) method to extend the linear modulation range of a cascaded five level inverter topology with a single DC supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0:577Vdc to 0:637Vdc without increasing the DC bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0 Hz to 50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The ve level topology presented in this thesis is realized by cascading a two level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady state and dynamic operating conditions are presented. Zero common mode voltage (CMV) operation of multilevel inverters results in reduced DC bus utilization and reduced linear modulation range. In this thesis two reduced CMV SVPWM schemes are presented to extend the linear modulation range by allowing reduced CMV switching. But using these SVPWM schemes the peak phase fundamental output voltage possible is only 0:55Vdc in the linear region. In this thesis, a method to extend the linear modulation range of a CMV eliminated hybrid cascaded multilevel inverter with a single DC supply is presented. Using this method peak fundamental voltage can be increased from 0 to 0:637Vdc with zero CMV switching inside the linear modulation range. Also inverter can be controlled linearly for the entire modulation range. Also, various PWM switching sequences are analyzed in this thesis and the PWM sequence which gives minimum current ripple is used for the zero CMV operation of the inverter. The inverter topology with single DC supply is realized by cascading a two level inverter with two floating capacitor fed full bridge modules. Simulation and experimental results for steady state and dynamic operating conditions are presented to validate the proposed method. A three phase, 400 V, 3.7 kW, 50 Hz, two-pole induction motor drive with the open-loop V/f control scheme is implemented in the hardware for testing proposed inverter topology and proposed SVPWM algorithms experimentally. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V IGBT half-bridge modules (SKM-75GB-12T4). Optoisolated gate drivers with de-saturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation, TMS320F28335 DSP is used as the main controller and Xilinx SPARTAN-3 XC3S200 FPGA as the PWM signal generator with dead time of 2.5 s. Level shifted carrier-based PWM algorithm is implemented for the normal inverter operation and zero CMV operation. From the PWM algorithm, information about the pole voltage levels to be switched can be obtained for each phase. In the sampling period, for capacitor voltage balancing of each phase, the DSP selects a switching state using the capacitor voltage information, current direction and pole voltage data for each phase. This switching state information along with the PWM timing data is sent to an FPGA module. The FPGA module generates the gating signals with a dead time of 2.5 s for the gate driver module for all the three phases by processing the switching state information and PWM signals for the given sampling period. For fundamental frequencies above 10Hz, synchronous PWM technique was used for testing the inverter topology. For modulation frequencies 10Hz and below, a constant switching frequency of 900 Hz was used. Various steady state and transient operation results are provided to validate the proposed inverter topology and the zero and reduced CMV operation schemes and extending the linear modulation scheme presented in this thesis. With the advantages like reduced switch count, single DC supply requirement, zero and reduced CMV operation, extension of linear modulation range, linear control of induction motor over the entire modulation range with zero CMV, lesser dv=dt stresses on devices and motor phase windings, lower switching frequency, inherent capacitor balancing, the proposed inverter power circuit topologies, and the SVPWM methods can be considered as good choice for medium voltage, high power motor drive applications.

Neutral-point-clamped (NPC) three-level inverter is capable of handling higher dc bus voltage and producing output waveform of better quality than a conventional two-level inverter. The main objective of the present work is to analyze the existing PWM schemes for two-level and three-level inverters in terms of line current ripple, and to design new PWM techniques for the NPC inverter to reduce line current distortion. Various discontinuous PWM or bus-clamping PWM (BCPWM) methods for a two-level voltage source inverter are analyzed in terms of rms line current ripple, which is evaluated by integrating the error voltage (i.e. error between the applied and reference voltages). The BCPWM schemes can be broadly classified into continual-clamp PWM (CCPWM) and split-clamp PWM (SCPWM). It is shown that split-clamp PWM scheme leads to lower harmonic distortion than CCPWM scheme. Further, advanced bus-clamping PWM (ABCPWM) methods for a two-level inverter are also studied. These methods clamp each phase to the positive and negative DC terminals over certain intervals as in BCPWM schemes, and also switch each phase at double the nominal frequency in certain other intervals unlike in BCPWM. Analytical closed-form expressions are derived for the total rms harmonic distortion due to SCPWM, CCPWM and ABCPWM schemes. Existing sinusoidal and bus-clamping PWM schemes for three-level NPC inverters are also analyzed in the space vector domain. These methods are compared in terms of line current ripple analytically as well as experimentally. As earlier, closed-form expressions are derived for the harmonic distortion factors corresponding to centered space vector PWM (CSVPWM) and the various BCPWM methods. A three-level inverter can be viewed as an equivalent two-level inverter in each sixth of the fundamental cycle or hextant. This is widely used to simplify the control of an NPC inverter. Further, this approach makes it simple to extend the BCPWM and ABCPWM methods for two-level inverters to three-level inverters. Furthermore, the method of analysis of line current ripple for the two-level inverter can also be easily extended to the three-level case. The pivot vector, which is half the length of the longest voltage vectors produced by the NPC inverter, acts as an equivalent null vector for the conceptual two-level inverter. Each pivot vector can be produced by two inverter states termed as “pivot states”. Typically, in continuous modulation methods for NPC inverter such as sinusoidal PWM and centered space vector PWM, the switching sequence (i.e. the sequence in which the voltage vectors are applied) begins and ends with the same pivot vector in each subcycle, which is equivalent to a half-carrier cycle. To be more precise, the switching sequence starts with one pivot state and ends with the other in each subcycle. However, in case of BCPWM schemes, only one pivot state is used in a subcycle. The choice of pivot state results in a variety of BCPWM schemes for an NPC inverter. Different BCPWM schemes are evaluated in terms of rms line current ripple. The optimal BCPWM, which minimizes the rms current ripple, is determined for an NPC inverter, controlled as an equivalent two-level inverter. Further, four new switching sequences are proposed here for a three-level inverter, controlled as a conceptual two-level inverter. These sequences apply the pivot vector only once, but employ one of the other two vectors twice within the subcycle. These four switching sequences are termed as “ABCPWM sequences” for three-level inverter. These sequences exploit the flexibility available in the space vector approach to PWM to switch a phase more than once in a subcycle, which results in the application of an active vector twice within the subcycle. Influence of the proposed ABCPWM sequences on the line current ripple over a subcycle is studied. The various sequences are compared in terms of rms line current ripple over a subcycle. An analytical closed-form expression for rms line current ripple over a subcycle is derived in terms of reference magnitude, angle of reference voltage vector, and subcycle duration for each of the sequences. Further, closed-form expressions are also derived for the rms current ripple over a line cycle in terms of modulation index and subcycle duration, corresponding to the various sequences. The four proposed ABCPWM sequences for the NPC inverter can be grouped into two pairs of sequences. Each pair of sequences is shown to perform better than the individual sequences, if the two sequences are employed in appropriate spatial regions. Hence, with these two pairs of sequences, two hybrid PWM schemes are proposed. Finally, a hybrid PWM technique is proposed which employs all five sequences (conventional and proposed four sequences) in spatial regions where each performs the best. This is termed as “five-zone hybrid PWM”. The total harmonic distortion (THD) in the motor current, pertaining to all the proposed schemes, is studied theoretically over the entire range of linear modulation. The theoretical investigations are validated experimentally on a 2.2 kW, 415V, 4.9A, 50 Hz induction motor drive. The no-load current THD is measured over a range of fundamental frequency from 10 Hz to 50 Hz in steps of 2 Hz for the various PWM methods. Theoretical and experimental results bring out the reduction in current THD due to the proposed BCPWM schemes at fundamental frequencies of 45 Hz and above, compared to CSVPWM. The ABCPWM methods improve the performance at higher as well as lower modulation indices. Further improvement is achieved with the proposed five-zone hybrid PWM. At the rated frequency (50 Hz) of the drive, the improvement in line current distortion is around 36% with this hybrid PWM scheme over CSVPWM. The reduction in THD is also experimentally verified at different loads on the motor. The difference between the top and bottom capacitor voltages is measured at various operating conditions, corresponding to CSVPWM and the proposed schemes. No significant difference is observed in the dc neutral voltage shifts with the different proposed schemes and CSVPWM method. Thus, the proposed methods improve the THD at low and high speed ranges without appreciable worsening of the dc voltage unbalance.