Relevant bibliographies by topics / Asynchronous circuit design (clockless)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Asynchronous circuit design (clockless)'

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Published: 28 May 2022

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Journal articles on the topic "Asynchronous circuit design (clockless)"

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Aguénounon, Enagnon, Safa Razavinejad, Jean-Baptiste Schell, Mohammadreza Dolatpoor Lakeh, Wassim Khaddour, Foudil Dadouche, Jean-Baptiste Kammerer, Laurent Fesquet, and Wilfried Uhring. "Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout." Sensors 21, no. 12 (June 8, 2021): 3949. http://dx.doi.org/10.3390/s21123949.

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The usage of single-photon avalanche diode arrays is becoming increasingly common in various domains such as medical imaging, automotive vision systems, and optical communications. Nowadays, thanks to the development of microelectronics technologies, the SPAD arrays designed for these applications has been drastically well-facilitated, allowing for the manufacturing of large matrices. However, there are growing challenges for the design of readout circuits with the needs of reducing their energy consumption (linked to the usage cost) and data rate. Indeed, the design of the readout circuit for the SPAD array is generally based on synchronous logic; the latter requires synchronization that may increase the dead time of the SPADs and clock trees management that are known to increase power consumption. With these limitations, the long-neglected asynchronous (clockless) logic proved to be a better alternative because of its ability to operate without a clock. In this paper, we presented the design of a 16-to-1 fixed-priority tree arbiter readout circuit for a SPAD array based on asynchronous logic principles. The design of this circuit was explained in detail and supported by simulation results. The manufactured chip was tested, and the experimental results showed that it is possible to record up to 333 million events per second; no reading errors were detected during the data extraction test.
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Shin, Ziho, Myeong-Hoon Oh, Jeong-Gun Lee, Hag Young Kim, and Young Woo Kim. "Design of a clockless MSP430 core using mixed asynchronous design flow." IEICE Electronics Express 14, no. 8 (2017): 20170162. http://dx.doi.org/10.1587/elex.14.20170162.

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SAITO, Hiroshi. "Techniques for Asynchronous Circuit Design." IEICE ESS FUNDAMENTALS REVIEW 3, no. 3 (2009): 64–70. http://dx.doi.org/10.1587/essfr.3.3_64.

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Oh, Myeong-Hoon. "Architectural Design Issues in a Clockless 32 Bit Processor Using an Asynchronous HDL." ETRI Journal 35, no. 3 (June 1, 2013): 480–90. http://dx.doi.org/10.4218/etrij.13.0112.0598.

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Harris, M. S. "Asynchronous circuit design for VLSI signal processing." Microelectronics Journal 25, no. 7 (October 1994): 604. http://dx.doi.org/10.1016/0026-2692(94)90050-7.

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Zhou, Liang, Scott Smith, and Jia Di. "Radiation Hardened NULL Convention Logic Asynchronous Circuit Design." Journal of Low Power Electronics and Applications 5, no. 4 (October 20, 2015): 216–33. http://dx.doi.org/10.3390/jlpea5040216.

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Ghavami, Behnam, and Hossein Pedram. "Low power asynchronous circuit back-end design flow." Microelectronics Journal 42, no. 2 (February 2011): 462–71. http://dx.doi.org/10.1016/j.mejo.2010.12.001.

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Shiroie, Masoud, and Karim Mohammadi. "Optimized Asynchronous Circuit Design based on Evolutionary Algorithm." International Journal of Computer Applications 40, no. 4 (February 29, 2012): 1–6. http://dx.doi.org/10.5120/5029-7177.

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Kim, Kyung Ki. "Asynchronous Circuit Design Combined with Power Switch Structure." Journal of the Korea Industrial Information Systems Research 21, no. 1 (February 29, 2016): 17–25. http://dx.doi.org/10.9723/jksiis.2016.21.1.017.

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Di, Jia, Brent A. Bell, William Bouillon, John Brady, Thao Le, Chien-Wei Lo, Liang Men, Spencer Nelson, Francis Sabado, and Andrew Suchanek. "Recent Advances in Low Power Asynchronous Circuit Design." Journal of Low Power Electronics 13, no. 3 (September 1, 2017): 280–97. http://dx.doi.org/10.1166/jolpe.2017.1494.

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Dissertations / Theses on the topic "Asynchronous circuit design (clockless)"

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Alsayeg, Khaled. "Synthèse de contrôleurs séquentiels QDI faible consommation prouvés corrects." Grenoble INPG, 2010. http://www.theses.fr/2010INPG0076.

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L'étude des circuits asynchrones est un secteur dans lequel de nombreuses recherches ont été effectuées ces dernières années. Les circuits asynchrones ont démontré plusieurs caractéristiques intéressantes comme la robustesse, l'extensibilité, la faible consommation ou le faible rayonnement électromagnétique. Parmi les différentes classes de circuits asynchrones, les circuits quasi-insensibles aux délais (QDI) ont montré des caractéristiques extrêmement intéressantes en termes de faible consommation et de robustesse aux variations PVT (Process, Voltage, Temperature). L'usage de ces circuits est notamment bien adapté aux applications fonctionnant dans un environnement sévère et pour lesquelles la consommation est un critère primordial. Les travaux de cette thèse s'inscrivent dans ce cadre et visent la conception et la synthèse de machines à états asynchrones (QDI) faiblement consommatrices. Une méthode de synthèse dédiée à des contrôleurs asynchrones à faible consommation a donc été développée. Cette technique s'est montrée particulièrement efficace pour synthétiser les contrôleurs de grande taille. La méthode s'appuie sur une modélisation appropriée des contrôleurs et une technique de synthèse dirigée par la syntaxe utilisant des composants spécifiques appelés séquenceurs. Les circuits obtenus ont été vérifiés formellement afin de s'assurer de leurs propriétés en termes de robustesse et de correction fonctionnelle. A cette occasion, une méthode de vérification formelle a été mise en place pour valider les contrôleurs d'une part, et plus généralement, n'importe quel circuit asynchrone d'autre part. Cette technique fait appel à une modélisation hiérarchique des circuits asynchrones en PSL et à un outil de vérification formelle (RAT)
The study of asynchronous circuits is an area where much research has been conducted in recent years. Asynchronous circuits have shown several interesting features like robustness, scalability, low consumption or low electromagnetic radiation. Among the different classes of asynchronous circuits, Quasi Delay Insensitive circuits (QDI) showed very interesting characteristics in terms of low power consumption and robustness to variations of PVT (Process, Voltage, and Temperature). The use of these circuits is particularly well suited for applications operating in a critical environment and for which consumption is paramount. In this framework, the work of this thesis aims the low power consumption design and synthesis of asynchronous state machines (QDI). A method for synthesizing low-consumption asynchronous sequential controllers has been developed. The method relies on an adequate modeling of controllers and a direct mapping synthesis technique using specific components called sequencers. This technique is suitable for synthesizing large controllers. The circuits obtained are formally verified to ensure their properties in terms of robustness and are proved functionally correct. Thereby, a formal verification method has been implemented to validate the sequential controllers on the one hand, and more generally, any other asynchronous circuit. This technique uses a hierarchical model of asynchronous circuits in PSL and a formal verification tool called RAT
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Benko, Igor. "ECF processes and asynchronous circuit design." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0003/NQ44753.pdf.

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Beaumont, Jonathan Richard. "Compositional circuit design with asynchronous concepts." Thesis, University of Newcastle upon Tyne, 2018. http://hdl.handle.net/10443/4149.

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Synchronous circuits are pervasive in modern digital systems, such as smart-phones, wearable devices and computers. Synchronous circuits are controlled by a global clock signal, which greatly simplifies their design but is also a limitation in some applications. Asynchronous circuits are a logical alternative: they do not use a global clock to synchronise their components. Instead, every component reacts to input events at the rate they occur. Asynchronous circuits are not widely adopted by industry, because they are often harder to design and require more sophisticated tools and formal models. Signal Transition Graphs (STGs) is a well-studied formal model for the specification, verification and synthesis of asynchronous circuits with state-of-the-art tool support. STGs use a graphical notation where vertices and arcs specify the operation of an asynchronous circuit. These graphical specifications can be difficult to describe compositionally, and provide little reusability of useful sections of a graph. In this thesis we present Asynchronous Concepts, a new design methodology for asynchronous circuit design. A concept is a self-contained description of a circuit requirement, which is composable with any other concept, allowing compositional specification of large asynchronous circuits. Concepts can be shared, reused and extended by users, promoting the reuse of behaviours within single or multiple specifications. Asynchronous Concepts can be translated to STGs to benefit from the existing theory and tools developed by the asynchronous circuits community. Plato is a software tool developed for Asynchronous Concepts that supports the presented design methodology, and provides automated methods for translation to STGs. The design flow which utilises Asynchronous Concepts is automated using Plato and the open-source toolsuite Workcraft, which can use the translated STGs in verification and synthesis using integrated tools. The proposed language, the design flow, and the supporting tools are evaluated on real-world case studies.
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Lam, Hing-Mo. "High performance coarse grain asynchronous circuit design /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20LAM.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.
Includes bibliographical references (leaves 52-54). Also available in electronic version. Access restricted to campus users.
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Morton, Shannon V. "Fast asynchronous VSLI circuit design techniques and their application to microprocessor design /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09phm891.pdf.

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Tabrizi, Nozar. "Asynchronous control circuit design and hazard generation : inertial delay and pure delay models /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09pht114.pdf.

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Lopes, Jeremy. "Design of an Innovative GALS (Globally Asynchronous Locally Synchronous), Non-Volatile Integrated Circuit for Space Applications." Thesis, Montpellier, 2017. http://www.theses.fr/2017MONTS052/document.

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Aujourd'hui, il existe plusieurs façons de développer des circuits microélectroniques adaptés aux applications spatiales qui répondent aux contraintes sévères de l'immunité contre les radiations, que ce soit en termes de technique de conception ou de processus de fabrication. Le but de ce doctorat est d'une part de combiner plusieurs techniques nouvelles de microélectronique pour concevoir des architectures adaptées à ce type d'application et d'autre part, d'incorporer des composants magnétiques non-volatiles intrinsèquement robustes aux rayonnements. Un tel couplage serait tout à fait novateur et profiterait sans précédent, en termes de surface, de consommation, de robustesse et de coût.Contrairement à la conception de circuits synchrones qui reposent sur un signal d'horloge, les circuits asynchrones ont l'avantage d'être plus ou moins insensibles aux variations temporel résultant par exemple des variations du processus de fabrication. En outre, en évitant l'utilisation d'une horloge, les circuits asynchrones ont une consommation d'énergie relativement faible. Les circuits asynchrones sont généralement conçus pour fonctionner en fonction des événements déterminés grâce à un protocole de "poignée de main" spécifique.Pour les applications avioniques et spatiales, il serait souhaitable de fournir un circuit asynchrone rendu robuste contre les effets des radiations. En effet, la présence de particules ionisantes à haute altitude ou dans l'espace peut induire des courants perturbateurs dans des circuits intégrés qui peuvent être suffisants pour provoquer un basculement à l'état binaire maintenu par une ou plusieurs grilles. Cela peut provoquer un dysfonctionnement du circuit, connu dans l'état de l'art en tant que single event upset (SEU). Il a été proposé de fournir un module redondant double (Dual Modular Redundency: DMR) ou un module redondant triple (Tripple Modular Redundcy: TMR) dans une conception de circuit asynchrone afin de fournir une protection contre les radiations. De telles techniques s'appuient sur la duplication du circuit dans le cas de DMR, ou en triplant le circuit dans le cas de TMR, et en détectant une discordance entre les sorties des circuits comme indication de l'apparition d'une SEU.L'intégration de composants non-volatils intrinsèquement robustes, tels que les jonctions de tunnel magnétique (JTM), l'élément principal de la mémoire MRAM, pourrait conduire à de nouvelles façons de retenir les données dans des environnements difficiles. Les dispositifs JTM sont constitués de matériaux ferromagnétiques avec des propriétés magnétiques qui ne sont pas sensibles aux rayonnements. Les données sont stockées sous la forme de la direction de l'aimantation et non sous la forme d'une charge électrique, qui est une propriété essentielle pour les applications spatiales. Il est également largement reconnu dans le domaine de la microélectronique que les circuits intégrés fabriqués sur les substrats SOI (Silicon On Insulator) sont plus robustes aux radiations.Il existe donc un besoin dans l'état de l'art pour un circuit ayant une surface et une consommation d'énergie relativement faibles, et qui permet une récupération après un SEU sans nécessiter de réinitialisation et qui présente des caractéristiques non-volatiles. L'objectif de ce doctorat est de combiner tous les avantages mentionnés ci-dessus en regroupant plusieurs méthodes de conception microélectronique répondant aux contraintes des applications spatiales dans une nouvelle architecture. Un Circuit complet a été imaginé, conçu, simulé et envoyé en fabrication. Ce circuit est composé d'un pipeline asynchrone d'additionneur et d'un test intégré complexe connu sous le nom de BIST (Built In Self Test). Apres fabrication, ce circuit sera testé. Premièrement des tests fonctionnels vont être réalisés, puis des tests sous laser pulsé seront menés ainsi que sous attaques aux ions lourds
Today, there are several ways to develop microelectronic circuits adapted for space applications that meet the harsh constraints of immunity towards radiation, whether in terms of technical design or manufacturing process. The aim of this doctorate is on the one hand to combine several novel techniques of microelectronics to design architectures adapted to this type of application, and on the other hand to incorporate non-volatile magnetic components inherently robust to radiation. Such an assembly would be quite innovative and would benefit without precedent, in terms of surface, consumption, robustness and cost.In contrast with synchronous circuit designs that rely on a clock signal, asynchronous circuits have the advantage of being more or less insensitive to delay variations resulting for example from variations in the manufacturing process. Furthermore, by avoiding the use of a clock, asynchronous circuits have relatively low power consumption. Asynchronous circuits are generally designed to operate based on events determined using a specific handshake protocol.For aviation and/or spatial applications, it would be desirable to provide an asynchronous circuit that is rendered robust against the effects of radiation. Indeed, the presence of ionising particles at high altitudes or in space can induce currents in integrated circuits that may be enough to cause a flip in the binary state held by one or more gates. This may cause the circuit to malfunction, known in the art as a single event upset (SEU). It has been proposed to provide dual modular redundancy (DMR) or triple modular redundancy (TMR) in an asynchronous circuit design in order to provide radiation protection. Such techniques rely on duplicating the circuit in the case of DMR, or triplicating the circuit in the case of TMR, and detecting a discordance between the outputs of the circuits as an indication of the occurrence of an SEU.The integration of inherently robust non-volatile components, such as Magnetic Tunnel Junctions (MTJ), the main element of MRAM memory, could lead to new ways of data retention in harsh environments. MTJ devices are constituted of ferromagnetic materials with magnetic properties that are not sensitive to radiation. Data is stored in the form of the direction of the magnetisation and not in the form of an electric charge, which is an essential property for space applications. It is also widely recognised in the field of microelectronics that integrated circuits manufactured on SOI (Silicon On Insulator) substrates are more robust to radiation.There is thus a need in the art for a circuit having relatively low surface area and power consumption, and that allows recovery following an SEU without requiring a reset and that has non-volatile characteristics. The objective of this doctorate is to combine all the above mentioned benefits by regrouping several methods of microelectronic design responding to the constraints of space applications into a novel architecture. A complete circuit has been created, designed, simulated, validated and sent to manufacturing in a 28nm FD-SOI process. This circuit is composed of an adder pipeline and a complex BIST (Build In Self Test). When fabricated, this circuit will be tested. First a functional test will be realised, then laser pules attacks will be performed and finally a heavy ions attack campaign
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Mallepalli, Samarsen Reddy. "Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplication." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Mallepalli_09007dcc803c4eec.pdf.

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Thesis (M.S.)--University of Missouri--Rolla, 2007.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 66-67).
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Parameswaran, Nair Ravi Sankar. "Delay-insensitive ternary logic (DITL)." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Parameswaran_Nair_09007dcc803bc548.pdf.

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Thesis (M.S.)--University of Missouri--Rolla, 2007.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 55-56).
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Germain, Sophie. "Contrôle du spectre électromagnétique d’un circuit numérique asynchrone." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT053.

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La compatibilité électromagnétique des circuits est devenue un enjeu majeur en conception numérique. Des méthodes de conception existent déjà pour réduire de manière qualitative le rayonnement des circuits synchrones. Cependant, il est difficile de réduire les harmoniques du spectre dues au signal d’horloge. La logique asynchrone est une alternative très intéressante, qui permet d’éviter la commutation simultanée de tous les éléments de mémorisation et de supprimer les harmoniques de l’horloge. Nous avons développé un flot de conception pour mettre en forme le rayonnement électromagnétique et ainsi répondre aux normes de compatibilité électromagnétique. Notre méthode s’applique à des circuits asynchrones. Une analyse temporelle statique permet d’extraire les délais à insérer dans le chemin de contrôle nécessaire au respect des hypothèses temporelles. Cette analyse sert aussi à annoter le modèle du circuit dans un simulateur analogique rapide, qui a été développé spécifiquement pour extraire sa consommation de courant. Grâce à ce simulateur, en calculant la transformée de Fourier, il est possible de remonter au spectre électromagnétique. Un algorithme génétique est alors utilisé pour créer des combinaisons de délais, permettant de mettre en forme le spectre selon le gabarit spécifié. Des mesures électromagnétiques sur un circuit de test, fabriqué en technologie CMOS 40 nm STMicroelectronics, ont montré que notre méthode permet de contrôler le rayonnement électromagnétique du circuit
Electromagnetic Compatibility has become a major issue for the digital designers. Several techniques exist qualitatively reducing the electromagnetic emissions of synchronous circuits. Nevertheless, the clocked activity produces strong periodic current pulses on the power supply, generating harmonics in the electromagnetic spectrum. Contrarily, asynchronous designs, also known as clockless circuits, show a spread electromagnetic spectrum without harmonics. We have developed a design flow in order to shape the electromagnetic spectrum and meet electromagnetic compatibility standards. Our method only applies to asynchronous circuits. A static timing analysis is performed to extract the delays of the control path that guarantee the timing assumptions. This analysis is used to annotate the circuit model in a fast analog simulator, which was specifically developed to extract its current consumption. Thanks to this simulator and a Fast Fourier Transform, it is possible to get the electromagnetic spectrum. A genetic algorithm is then used to create delay combinations shaping the spectrum in order to match the targeted spectral mask. Electromagnetic measurements on a test chip, manufactured in STMicroelectronics CMOS 40nm technology, have shown that our method allows controlling the electromagnetic field of the circuit
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Books on the topic "Asynchronous circuit design (clockless)"

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library, Wiley online, ed. Logically determined design: Clockless system design with NULL convention logic. Hoboken, N.J: John Wiley & Sons, 2005.

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Myers, Chris J. Asynchronous circuit design. New York: J. Wiley & Sons, 2001.

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Birtwistle, Graham, and Alan Davis, eds. Asynchronous Digital Circuit Design. London: Springer London, 1995. http://dx.doi.org/10.1007/978-1-4471-3575-3.

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Sparsø, Jens, and Steve Furber, eds. Principles of Asynchronous Circuit Design. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3385-3.

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Meng, Teresa H. Asynchronous Circuit Design for VLSI Signal Processing. Boston, MA: Springer US, 1994.

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Meng, Teresa H., and Sharad Malik, eds. Asynchronous Circuit Design for VLSI Signal Processing. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2794-7.

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Spars©ı, Jens. Principles of Asynchronous Circuit Design: A Systems Perspective. Boston, MA: Springer US, 2001.

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IFIP WG10.5 Working Conference on Asynchronous Design Methodologies (1993 Manchester, England). Asynchronous design methodologies: Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March-2 April, 1993. Amsterdam: North-Holland, 1993.

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Vasyukevich, Vadim. Asynchronous Operators of Sequential Logic: Venjunction & Sequention: Digital Circuit Analysis and Design. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011.

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Multi-point interconnects for globally-asynchronous locally-synchronous systems. Konstanz: Hartung-Gorre Verlag, 2005.

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Book chapters on the topic "Asynchronous circuit design (clockless)"

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Pessolano, Francesco, and Joep WL Kessels. "Asynchronous First-in First-out Queues." In Integrated Circuit Design, 178–86. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45373-3_18.

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Sparsø, Jens, and Steve Furber. "Handshake Circuit Implementations." In Principles of Asynchronous Circuit Design, 57–80. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3385-3_5.

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Davis, Al, and Steven M. Nowick. "Asynchronous Circuit Design: Motivation, Background, & Methods." In Asynchronous Digital Circuit Design, 1–49. London: Springer London, 1995. http://dx.doi.org/10.1007/978-1-4471-3575-3_1.

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Ebergen, Jo C., John Segers, and Igor Benko. "Parallel Program and Asynchronous Circuit Design." In Asynchronous Digital Circuit Design, 50–103. London: Springer London, 1995. http://dx.doi.org/10.1007/978-1-4471-3575-3_2.

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Davis, Al. "Synthesizing Asynchronous Circuits: Practice and Experience." In Asynchronous Digital Circuit Design, 104–50. London: Springer London, 1995. http://dx.doi.org/10.1007/978-1-4471-3575-3_3.

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van Berkel, Kees, and Martin Rem. "VLSI Programming of Asynchronous Circuits for Low Power." In Asynchronous Digital Circuit Design, 151–210. London: Springer London, 1995. http://dx.doi.org/10.1007/978-1-4471-3575-3_4.

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Furber, Steve. "Computing without Clocks: Micropipelining the ARM Processor." In Asynchronous Digital Circuit Design, 211–62. London: Springer London, 1995. http://dx.doi.org/10.1007/978-1-4471-3575-3_5.

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Vogler, Walter, and Ralf Wollowski. "Decomposition in Asynchronous Circuit Design." In Concurrency and Hardware Design, 152–90. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-36190-1_5.

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Vogler, Walter, and Ralf Wollowski. "Decomposition in Asynchronous Circuit Design." In FST TCS 2002: Foundations of Software Technology and Theoretical Computer Science, 336–47. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-36206-1_30.

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Starodoubtsev, N., A. Bystrov, and A. Yakovlev. "Semi-modular Latch Chains for Asynchronous Circuit Design." In Integrated Circuit Design, 168–77. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45373-3_17.

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Conference papers on the topic "Asynchronous circuit design (clockless)"

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Renaudin, Marc, Aurelien Buhrig, Charles Guillemet, Robin Wilson, and Sylvain Engels. "Clockless Design Performance Monitoring for Nanometer Technologies." In 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE, 2014. http://dx.doi.org/10.1109/async.2014.24.

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Bhatti, Muhammad Kamran, Behlol Nawaz, and Abdul Majeed Soomro. "Design & Analysis of Asynchronous (Clockless) Circuits and Implementation using Mentor Graphics ASIC Design Tools." In 2019 2nd International Conference on Communication, Computing and Digital systems (C-CODE). IEEE, 2019. http://dx.doi.org/10.1109/c-code.2019.8680988.

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Purohit, Sohan, and Martin Margala. "Data driven DCVSL: A clockless approach to dynamic differential circuit design." In 2010 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2010. http://dx.doi.org/10.1109/mwscas.2010.5548907.

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Le Huy, Nguyen, Pham Chi Thanh, Tran Duc Linh, and Alex Stojcevski. "Design and simulation of a novel clockless Fast Fourier Transform (FFT) circuit." In 2017 Seventh International Conference on Information Science and Technology (ICIST). IEEE, 2017. http://dx.doi.org/10.1109/icist.2017.7926775.

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Peeters, Ad, and Mark de Wit. "Asynchronous circuit design using Handshake Solutions." In 2008 IEEE International SOC Conference (SOCC). IEEE, 2008. http://dx.doi.org/10.1109/socc.2008.4641555.

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Mocho, R. U. R., G. H. Sartori, R. P. Ribas, and A. I. Reis. "Asynchronous circuit design on reconfigurable devices." In the 19th annual symposium. New York, New York, USA: ACM Press, 2006. http://dx.doi.org/10.1145/1150343.1150355.

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Li, Zongming, Baichao An, Haoyu Lu, Qiang Liu, and Liying Yuan. "Asynchronous Motor Fault Detection Circuit Design." In International Conference on Energy 2014. Science & Engineering Research Support soCiety, 2014. http://dx.doi.org/10.14257/astl.2014.53.55.

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Yakovlev, A. "Petri nets and asynchronous circuit design." In IEE Colloquium on Design and Test of Asynchronous Systems. IEE, 1996. http://dx.doi.org/10.1049/ic:19960253.

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Wei, Xiaoni. "Asynchronous reset design architecture." In 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT). IEEE, 2014. http://dx.doi.org/10.1109/icsict.2014.7021404.

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Wu, Gang, Tao Lin, Hsin-Ho Huang, Chris Chu, and Peter A. Beerel. "Asynchronous circuit placement by Lagrangian relaxation." In 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2014. http://dx.doi.org/10.1109/iccad.2014.7001420.

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