Dissertations / Theses on the topic 'Asynchronous circuit design (clockless)'

L'étude des circuits asynchrones est un secteur dans lequel de nombreuses recherches ont été effectuées ces dernières années. Les circuits asynchrones ont démontré plusieurs caractéristiques intéressantes comme la robustesse, l'extensibilité, la faible consommation ou le faible rayonnement électromagnétique. Parmi les différentes classes de circuits asynchrones, les circuits quasi-insensibles aux délais (QDI) ont montré des caractéristiques extrêmement intéressantes en termes de faible consommation et de robustesse aux variations PVT (Process, Voltage, Temperature). L'usage de ces circuits est notamment bien adapté aux applications fonctionnant dans un environnement sévère et pour lesquelles la consommation est un critère primordial. Les travaux de cette thèse s'inscrivent dans ce cadre et visent la conception et la synthèse de machines à états asynchrones (QDI) faiblement consommatrices. Une méthode de synthèse dédiée à des contrôleurs asynchrones à faible consommation a donc été développée. Cette technique s'est montrée particulièrement efficace pour synthétiser les contrôleurs de grande taille. La méthode s'appuie sur une modélisation appropriée des contrôleurs et une technique de synthèse dirigée par la syntaxe utilisant des composants spécifiques appelés séquenceurs. Les circuits obtenus ont été vérifiés formellement afin de s'assurer de leurs propriétés en termes de robustesse et de correction fonctionnelle. A cette occasion, une méthode de vérification formelle a été mise en place pour valider les contrôleurs d'une part, et plus généralement, n'importe quel circuit asynchrone d'autre part. Cette technique fait appel à une modélisation hiérarchique des circuits asynchrones en PSL et à un outil de vérification formelle (RAT)
The study of asynchronous circuits is an area where much research has been conducted in recent years. Asynchronous circuits have shown several interesting features like robustness, scalability, low consumption or low electromagnetic radiation. Among the different classes of asynchronous circuits, Quasi Delay Insensitive circuits (QDI) showed very interesting characteristics in terms of low power consumption and robustness to variations of PVT (Process, Voltage, and Temperature). The use of these circuits is particularly well suited for applications operating in a critical environment and for which consumption is paramount. In this framework, the work of this thesis aims the low power consumption design and synthesis of asynchronous state machines (QDI). A method for synthesizing low-consumption asynchronous sequential controllers has been developed. The method relies on an adequate modeling of controllers and a direct mapping synthesis technique using specific components called sequencers. This technique is suitable for synthesizing large controllers. The circuits obtained are formally verified to ensure their properties in terms of robustness and are proved functionally correct. Thereby, a formal verification method has been implemented to validate the sequential controllers on the one hand, and more generally, any other asynchronous circuit. This technique uses a hierarchical model of asynchronous circuits in PSL and a formal verification tool called RAT

Synchronous circuits are pervasive in modern digital systems, such as smart-phones, wearable devices and computers. Synchronous circuits are controlled by a global clock signal, which greatly simplifies their design but is also a limitation in some applications. Asynchronous circuits are a logical alternative: they do not use a global clock to synchronise their components. Instead, every component reacts to input events at the rate they occur. Asynchronous circuits are not widely adopted by industry, because they are often harder to design and require more sophisticated tools and formal models. Signal Transition Graphs (STGs) is a well-studied formal model for the specification, verification and synthesis of asynchronous circuits with state-of-the-art tool support. STGs use a graphical notation where vertices and arcs specify the operation of an asynchronous circuit. These graphical specifications can be difficult to describe compositionally, and provide little reusability of useful sections of a graph. In this thesis we present Asynchronous Concepts, a new design methodology for asynchronous circuit design. A concept is a self-contained description of a circuit requirement, which is composable with any other concept, allowing compositional specification of large asynchronous circuits. Concepts can be shared, reused and extended by users, promoting the reuse of behaviours within single or multiple specifications. Asynchronous Concepts can be translated to STGs to benefit from the existing theory and tools developed by the asynchronous circuits community. Plato is a software tool developed for Asynchronous Concepts that supports the presented design methodology, and provides automated methods for translation to STGs. The design flow which utilises Asynchronous Concepts is automated using Plato and the open-source toolsuite Workcraft, which can use the translated STGs in verification and synthesis using integrated tools. The proposed language, the design flow, and the supporting tools are evaluated on real-world case studies.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.
Includes bibliographical references (leaves 52-54). Also available in electronic version. Access restricted to campus users.

Aujourd'hui, il existe plusieurs façons de développer des circuits microélectroniques adaptés aux applications spatiales qui répondent aux contraintes sévères de l'immunité contre les radiations, que ce soit en termes de technique de conception ou de processus de fabrication. Le but de ce doctorat est d'une part de combiner plusieurs techniques nouvelles de microélectronique pour concevoir des architectures adaptées à ce type d'application et d'autre part, d'incorporer des composants magnétiques non-volatiles intrinsèquement robustes aux rayonnements. Un tel couplage serait tout à fait novateur et profiterait sans précédent, en termes de surface, de consommation, de robustesse et de coût.Contrairement à la conception de circuits synchrones qui reposent sur un signal d'horloge, les circuits asynchrones ont l'avantage d'être plus ou moins insensibles aux variations temporel résultant par exemple des variations du processus de fabrication. En outre, en évitant l'utilisation d'une horloge, les circuits asynchrones ont une consommation d'énergie relativement faible. Les circuits asynchrones sont généralement conçus pour fonctionner en fonction des événements déterminés grâce à un protocole de "poignée de main" spécifique.Pour les applications avioniques et spatiales, il serait souhaitable de fournir un circuit asynchrone rendu robuste contre les effets des radiations. En effet, la présence de particules ionisantes à haute altitude ou dans l'espace peut induire des courants perturbateurs dans des circuits intégrés qui peuvent être suffisants pour provoquer un basculement à l'état binaire maintenu par une ou plusieurs grilles. Cela peut provoquer un dysfonctionnement du circuit, connu dans l'état de l'art en tant que single event upset (SEU). Il a été proposé de fournir un module redondant double (Dual Modular Redundency: DMR) ou un module redondant triple (Tripple Modular Redundcy: TMR) dans une conception de circuit asynchrone afin de fournir une protection contre les radiations. De telles techniques s'appuient sur la duplication du circuit dans le cas de DMR, ou en triplant le circuit dans le cas de TMR, et en détectant une discordance entre les sorties des circuits comme indication de l'apparition d'une SEU.L'intégration de composants non-volatils intrinsèquement robustes, tels que les jonctions de tunnel magnétique (JTM), l'élément principal de la mémoire MRAM, pourrait conduire à de nouvelles façons de retenir les données dans des environnements difficiles. Les dispositifs JTM sont constitués de matériaux ferromagnétiques avec des propriétés magnétiques qui ne sont pas sensibles aux rayonnements. Les données sont stockées sous la forme de la direction de l'aimantation et non sous la forme d'une charge électrique, qui est une propriété essentielle pour les applications spatiales. Il est également largement reconnu dans le domaine de la microélectronique que les circuits intégrés fabriqués sur les substrats SOI (Silicon On Insulator) sont plus robustes aux radiations.Il existe donc un besoin dans l'état de l'art pour un circuit ayant une surface et une consommation d'énergie relativement faibles, et qui permet une récupération après un SEU sans nécessiter de réinitialisation et qui présente des caractéristiques non-volatiles. L'objectif de ce doctorat est de combiner tous les avantages mentionnés ci-dessus en regroupant plusieurs méthodes de conception microélectronique répondant aux contraintes des applications spatiales dans une nouvelle architecture. Un Circuit complet a été imaginé, conçu, simulé et envoyé en fabrication. Ce circuit est composé d'un pipeline asynchrone d'additionneur et d'un test intégré complexe connu sous le nom de BIST (Built In Self Test). Apres fabrication, ce circuit sera testé. Premièrement des tests fonctionnels vont être réalisés, puis des tests sous laser pulsé seront menés ainsi que sous attaques aux ions lourds
Today, there are several ways to develop microelectronic circuits adapted for space applications that meet the harsh constraints of immunity towards radiation, whether in terms of technical design or manufacturing process. The aim of this doctorate is on the one hand to combine several novel techniques of microelectronics to design architectures adapted to this type of application, and on the other hand to incorporate non-volatile magnetic components inherently robust to radiation. Such an assembly would be quite innovative and would benefit without precedent, in terms of surface, consumption, robustness and cost.In contrast with synchronous circuit designs that rely on a clock signal, asynchronous circuits have the advantage of being more or less insensitive to delay variations resulting for example from variations in the manufacturing process. Furthermore, by avoiding the use of a clock, asynchronous circuits have relatively low power consumption. Asynchronous circuits are generally designed to operate based on events determined using a specific handshake protocol.For aviation and/or spatial applications, it would be desirable to provide an asynchronous circuit that is rendered robust against the effects of radiation. Indeed, the presence of ionising particles at high altitudes or in space can induce currents in integrated circuits that may be enough to cause a flip in the binary state held by one or more gates. This may cause the circuit to malfunction, known in the art as a single event upset (SEU). It has been proposed to provide dual modular redundancy (DMR) or triple modular redundancy (TMR) in an asynchronous circuit design in order to provide radiation protection. Such techniques rely on duplicating the circuit in the case of DMR, or triplicating the circuit in the case of TMR, and detecting a discordance between the outputs of the circuits as an indication of the occurrence of an SEU.The integration of inherently robust non-volatile components, such as Magnetic Tunnel Junctions (MTJ), the main element of MRAM memory, could lead to new ways of data retention in harsh environments. MTJ devices are constituted of ferromagnetic materials with magnetic properties that are not sensitive to radiation. Data is stored in the form of the direction of the magnetisation and not in the form of an electric charge, which is an essential property for space applications. It is also widely recognised in the field of microelectronics that integrated circuits manufactured on SOI (Silicon On Insulator) substrates are more robust to radiation.There is thus a need in the art for a circuit having relatively low surface area and power consumption, and that allows recovery following an SEU without requiring a reset and that has non-volatile characteristics. The objective of this doctorate is to combine all the above mentioned benefits by regrouping several methods of microelectronic design responding to the constraints of space applications into a novel architecture. A complete circuit has been created, designed, simulated, validated and sent to manufacturing in a 28nm FD-SOI process. This circuit is composed of an adder pipeline and a complex BIST (Build In Self Test). When fabricated, this circuit will be tested. First a functional test will be realised, then laser pules attacks will be performed and finally a heavy ions attack campaign

Thesis (M.S.)--University of Missouri--Rolla, 2007.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 66-67).

Thesis (M.S.)--University of Missouri--Rolla, 2007.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 55-56).

La compatibilité électromagnétique des circuits est devenue un enjeu majeur en conception numérique. Des méthodes de conception existent déjà pour réduire de manière qualitative le rayonnement des circuits synchrones. Cependant, il est difficile de réduire les harmoniques du spectre dues au signal d’horloge. La logique asynchrone est une alternative très intéressante, qui permet d’éviter la commutation simultanée de tous les éléments de mémorisation et de supprimer les harmoniques de l’horloge. Nous avons développé un flot de conception pour mettre en forme le rayonnement électromagnétique et ainsi répondre aux normes de compatibilité électromagnétique. Notre méthode s’applique à des circuits asynchrones. Une analyse temporelle statique permet d’extraire les délais à insérer dans le chemin de contrôle nécessaire au respect des hypothèses temporelles. Cette analyse sert aussi à annoter le modèle du circuit dans un simulateur analogique rapide, qui a été développé spécifiquement pour extraire sa consommation de courant. Grâce à ce simulateur, en calculant la transformée de Fourier, il est possible de remonter au spectre électromagnétique. Un algorithme génétique est alors utilisé pour créer des combinaisons de délais, permettant de mettre en forme le spectre selon le gabarit spécifié. Des mesures électromagnétiques sur un circuit de test, fabriqué en technologie CMOS 40 nm STMicroelectronics, ont montré que notre méthode permet de contrôler le rayonnement électromagnétique du circuit
Electromagnetic Compatibility has become a major issue for the digital designers. Several techniques exist qualitatively reducing the electromagnetic emissions of synchronous circuits. Nevertheless, the clocked activity produces strong periodic current pulses on the power supply, generating harmonics in the electromagnetic spectrum. Contrarily, asynchronous designs, also known as clockless circuits, show a spread electromagnetic spectrum without harmonics. We have developed a design flow in order to shape the electromagnetic spectrum and meet electromagnetic compatibility standards. Our method only applies to asynchronous circuits. A static timing analysis is performed to extract the delays of the control path that guarantee the timing assumptions. This analysis is used to annotate the circuit model in a fast analog simulator, which was specifically developed to extract its current consumption. Thanks to this simulator and a Fast Fourier Transform, it is possible to get the electromagnetic spectrum. A genetic algorithm is then used to create delay combinations shaping the spectrum in order to match the targeted spectral mask. Electromagnetic measurements on a test chip, manufactured in STMicroelectronics CMOS 40nm technology, have shown that our method allows controlling the electromagnetic field of the circuit

The first part of this work is devoted to the design of a traction asynchronous motor. The second part focuses on the developed method of the equivalent circuit parameters identification of the asynchronous motor in the form of -network. It is explained here that the equivalent circuit in the shape of a -network, alternatively of an inverse 'I-network, is exactly equivalent and fully-fledged to a T-network, although one of two stray inductances is formally missing. Furthermore, the relationships for the conversions of the T-network parameters to the -network parameters and back, and of the T-network to the inverse 'I-network and back are found. The third part deals with the calculation of the torque and the current characteristics of the asynchronous motor. A sensitive analysis of the torque characteristic is carried out on the individual parameters of the equivalent circuit of the asynchronous motor in the form of a -network and a method of the measurement by means of a flywheel is used for the torque characteristic measurement of the asynchronous motor. The fourth part focuses on the verification of the identified -network parameters in the Matlab-model of the traction drive.

Ce mémoire de thèse présente l'étude d'une structure cylindrique de machine à double entrefer, en versions asynchrone et synchrone. L'étude théorique est basée sur l'identification du schéma équivalent de la machine à partir des simulations numériques par la méthode des éléments finis. Les paramètres qui caractérisent son comportement en régime dynamique sont déterminés en simulant l'essai de la réponse fréquentielle à l'arrêt. Une maquette, dont le double stator peut fonctionner soit en mode asynchrone, avec un rotor à cage d'écureuil, soit en mode synchrone, avec un rotor à aimants permanents, a été dimensionnée et construite pour la caractérisation expérimentale de cette structure. Chaque version de la maquette est comparée avec une machine classique de même type. La version synchrone s'avère mieux adaptée à la structure à double entrefer : sa puissance massique est sensiblement améliorée et son rotor ne pose pas de problèmes particuliers de tenue mécanique. Les deux versions de cette maquette sont intéressantes par leur moment d'inertie rotorique réduit

碩士
大同大學
通訊工程研究所
96
This thesis proposes an asynchronous two-dimension discrete cosine transform (2-D DCT) processor. In asynchronous design, we used Sutherland’s Micropipelines to implement handshake pipeline. In DCT process, we adopt row-column decomposition method to separate 2-D DCT into two one-dimensional discrete cosine transform (1-D DCT) and a transpose memory. In order to realize the matrix calculation easily, multiplier and accumulator method has been adapted. We implement 2-D DCT function with Field Programable Gate Array (FPGA), and verify the design by the function simulation and timing simulation. FPGA has the programble property, so it’s very convient to be used in design level. We design asynchronous circuit which is based on FPGA architecture. The proposed circuit has asynchronous design spirit, but not completely followed the asynchronous design of the reference paper. The timing simulation result of 2-D DCT is not satisfied, the reason is related with FPGA architecture and the compile tool. Because we can not control the placement and routing of the circuit very well, the programs are auto compiled by FPGA tool, so it could cause the circuit failed. Although we met many challenges in FPGA design, but these experiences can be refered in the future ASIC asynchronous design.

碩士
淡江大學
電機工程學系
91
Pipeline architecture is a common paradigm for very high-speed computing. Pipeline architecture provides high speed because it allows many operations to be executed in concurrent. As silicon feature sizes decrease and chip sizes increase, there are two problems in synchronous systems become increasingly costly to solve. The higher power consumption comes from clock networks, and clock skew causes logic circuit calculating wrong data. A different circuit is designed to solve above two problems in synchronous system. Therefore, synchronous system is converted to asynchronous system. In the asynchronous system, the clock networks replaced by handshake circuit used to govern the operations of the pipeline. A new robust handshake scheme for asynchronous system is proposed in this thesis. In the asynchronous system study, the handshake methodologies have about ten years history. And the new handshake methodology not only has the advantages of the previous handshake methodologies but also has some advantages its own. First, pre-charge time does not affect calculation time. Second, fast due to its simplicity four transistors. Third, asynchronous systems are more flexibility asymmetric data path. A new technique is also proposed in the data path. It combines single-rail dynamic circuits with dual-rail dynamic circuits in the data path. And it brings some advantages that reduce power consumption and chip area while asynchronous systems maintain the calculation speed. Finally, the new robust handshake methodology is implemented into a 4x4-bit asynchronous array multiplier. The circuit is implemented by TSMC 0.35 um CMOS process. The measurement results have been shown that the asymmetric asynchronous array multiplier can achieve an input to output latency of 17n second, a throughput rate of 120M Hz, a power consumption of 330mW.

So Pui Tak.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.
Includes bibliographical references.
Abstracts in English and Chinese.
Abstract --- p.ii
Acknowledgement --- p.v
Table of Contents --- p.vi
List of Figures --- p.ix
List of Tables --- p.xii
Chapter Chapter 1 --- Introduction --- p.11
Chapter 1.1 --- Overview --- p.1-1
Chapter 1.1 --- Power Consumption in Conventional CMOS circuit --- p.1-1
Chapter 1.2 --- Power Consumption in Synchronous Circuit --- p.1-6
Chapter 1.4 --- Objectives --- p.1-7
Chapter 1.5 --- Thesis Outline --- p.1-8
Chapter Chapter 2 --- Background Theory --- p.2-1
Chapter 2.1 --- Introduction --- p.2-1
Chapter 2.2 --- Definition of Adiabatic Principle --- p.2-1
Chapter 2.3 --- Overview of Adiabatic Circuit --- p.2-3
Chapter 2.4 --- Asynchro nous Circuits --- p.2-7
Chapter Chapter 3 --- Adiabatic Circuit usingRVS --- p.3-1
Chapter 3.1 --- Introduction --- p.3-1
Chapter 3.2 --- Architecture --- p.3-2
Chapter 3.3 --- Ramp Voltage Supply Generator --- p.3-4
Chapter 3.4 --- Circuit Evaluation --- p.3-7
Chapter 3.5 --- Simulation Results --- p.3-8
Chapter 3.4 --- Experimental Results --- p.3-9
Chapter Chapter 4 --- Asynchronous Circuit Technique --- p.4-1
Chapter 4.1 --- Introduction --- p.4-1
Chapter 4.2 --- Architecture --- p.4-1
Chapter 4.2.1 --- Muller Distributor Block Design --- p.4-2
Chapter 4.2.2 --- Delay Block Design --- p.4-4
Chapter Chapter 5 --- Adiabatic -Asynchronous Multiplier --- p.5-1
Chapter 5.1 --- Introduction --- p.5-1
Chapter 5.2 --- Combination of Adiabatic and Asynchronous Techniques. --- p.5-1
Chapter 5.3 --- Oscillator Block Design --- p.5-3
Chapter 5.4 --- Multiplier Architecture --- p.5-6
Chapter Chapter 6 --- Layout Consideration --- p.6-1
Chapter 6.1 --- Introduction --- p.6-1
Chapter 6.2 --- Floorplanning --- p.6-1
Chapter 6.3 --- Routing Channels --- p.6-2
Chapter 6.3 --- Power Supply --- p.6-4
Chapter 6.4 --- Input Protection Circuitry --- p.6-5
Chapter 6.5 --- Die Micrographs of the Chip --- p.6-7
Chapter Chapter 7 --- Simulation Results --- p.7-1
Chapter 7.1 --- Introduction --- p.7-1
Chapter 7.2 --- Muller Distributor Control Signal --- p.7-1
Chapter 7.3 --- Power Consumption --- p.7-6
Chapter 7.3.1 --- Synchronous Multiplier --- p.7-6
Chapter 7.3.2 --- AAT Multiplier --- p.7-7
Chapter 7.3.3 --- Power Comparison --- p.7-8
Chapter Chapter 8 --- Measurement Results --- p.8-1
Chapter 8.1 --- Introduction --- p.8-1
Chapter 8.2 --- Experimental Setup --- p.8-2
Chapter 8.3 --- Measurement Results --- p.8-6
Chapter Chapter 9 --- Conclusion --- p.9-1
Chapter 9.1 --- Contributions --- p.9-1
Chapter Chapter 10 --- Bibliography --- p.10-1
Appendix I Building Blocks --- p.1
Appendix II Simulated Waveform --- p.7
Appendix III Measured Waveform --- p.8
Appendix IV Pin List --- p.9

碩士
國立清華大學
電機工程學系
100
As the manufacturing technology progresses to deep sub-micron nodes, people must make more efforts to keep better clock signal in digital integrated circuit design than ever. Asynchronous circuits directly remove the clock signal, and make circuit operate more efficiently. In this thesis, we developed an asynchronous design implementation approach which adopts commercial computer aided design tools and synchronous cell libraries, in an attempt to remove the deficiency and restrictions in current asynchronous design flows. Most of current asynchronous design flows are different with synchronous standard flows. They need the support of additional cell libraries, and designers be reeducated for unfamiliar programming language and tools. The proposed asynchronous implementation approach is based on globally asynchronous locally synchronous (GALS) system. All the building blocks are separated and allow individual improvement and modifications. As a result of our research, we found that current synthesis tools are not suitable for asynchronous circuits, and thus we pointed the shortcomings of synchronous synthesis tools as applying to asynchronous designs. We hope that synthesis tools can be improved for the use of asynchronous IC design in the future. To measure the performance of the proposed asynchronous circuits, we analyzed the timing in single-stage and multiple-stage pipeline configurations, and pointed the phenomenon of blocking and starvation due to data dependency in multiple-stage circuits. At the end of thesis, full comparisons of synchronous and asynchronous designs in performance, area, energy, and modularity are carried out.

碩士
朝陽科技大學
資訊與通訊系碩士班
101
In recent year, high speed circuit such as voltage control oscillator (VCO) and dual-modulus prescaler in the face of vital design challenge. In previous divider designs dissipated over 40~50% power consumption in frequency synthesizers. Accordingly, we investigated conventional divider designs and presented a frequency divider with asynchronous circuit structure. This thesis presents both an extended true-single-phase-clock (E-TSPC) and true-single-phase-clock (TSPC) based high frequency divide-by-4/5 divider design for low supply voltage and low power dissipation applications. First, we use TSMC CMOS 1P6M 0.18μm process technology to implement the frequency divider circuit. By using asynchronous circuit scheme, the proposed design significantly reduces power consumption due to lower switching activity. And the third D flip-flops (DFF) hire true-single-phase-clock (TSPC) architectures to achieve lower short circuit power. Post layout simulation results show that when compared with recently design as much as 51% in power consumption and 53% in power-delay-product can be achieved by the proposed design. Finally, the proposed design has been implemented with a 0.18μm CMOS technology. When the supply voltage is 1.8V, the measured operation speed of the proposed divider reaches up to 5.6GHz with power consumption 0.88mW.

碩士
國立彰化師範大學
電子工程學系
97
This thesis proposes a novel low-power logic circuit, called handshaking quasi-adiabatic logic (HQAL), which combines the advantages of asynchronous circuits and adiabatic logics. The HQAL logics adopt dual-rail encoding, and employ handshaking to transfer data between the adjacent modules. Hence, HQAL has the advantages of asynchronous circuits: no clock skew problem, no power dissipation due to the clock tree, and no dynamic power dissipation when there are no input data. The power line of the HQAL logic gates is controlled by the handshake control chain (HCC). A HQAL logic gate is not supplied with power when it has no input data. Only when a HQAL gate has acquired its input data, it can gain the power and then operate in a way similar to the adiabatic logic. Hence, the HQAL logic can achieve low power dissipation. With the handshake control chain, the HQAL circuit can avoid the problem of data token overriding, which may occur in conventional asynchronous adiabatic logic (AAL) circuits. Simulation results showed that the HQAL implementation of a pipelined Sklansky adder can achieve 33.1% reduction in power dissipation, compared to the CMOS implementation, for a data rate of 700 MHz and 72.5% reduction in power dissipation for a data rate of 10 MHz. Also, the HQAL implementation can achieve up to 95.6% reduction in static power dissipation as the adiabatic logic blocks in HQAL are not powered and have negligible leakage power dissipation when they have no input.

碩士
南台科技大學
電子工程系
98
When we look up academic papers published in the earlier time, we could have found that synchronous and asynchronous circuit designs were developed and co-existed around the same time. Even as early as 1950, some scholars had already proposed the design methodology of asynchronous system which is characterized as low power, low eletro-magnetic interference (EMI), highly rebustness, modularization and so on in comparison with its counter part, the synchronous system. Because design and implementation of the asynchronous circuits are much more complex, thus the development of the asynchronous circuits started in a much slower pace. It did not become the mainstream design methodology until the 60s. In the recent trend on asynchronous circuit, well-developed electronic design automation (EDA) tools and the standardized elements and modules are being developed. Besides, the system function and the timing verification needed for large-scaled integrated circuit (IC) are available, too. For synchronous circuit or system, we may do the design with the application-specific integrated circuit (ASIC) design flows and conventional field-programmable gate array (FPGA). But it is not feasible if we try to design in the asynchronous way. If we have asynchronous FPGA as auxiliary tools, then the problem would be solved. On the market, there are a few asynchronous FPGA available, but the chip used on the FPGA is rare in this early stage, and the mass-production of it is as well. Lacking equipments and tools, costly chips, and incomplete set of examples and design flow are the reasons for unpopularity of asynchronous design. Therefore, this thesis proposed an asynchronous design flow based on accessing of synchronous FPGA. We hope this would speed up the widespread use of the asynchronous design, and lower the difficulties for the new entrants by reducing the needs various equipments for the experiment. This thesis proposed an asynchronous digital circuit design methodology based on the asynchronous FPGA, a tiny self-timed microprocessor is the actual example of the design. Furthermore, the example uses the available synchronous FPGA as the platform for verification. The design methodology is to use high level description in the algorithmic level through channel level in behavior description for verification, and we further transcribe to handshaking level asynchronous finite state machine and self-timed datapath, and to provide synthesizable HDL for FPGA for uploading onto the FPGA for system function verification. We will use the actual cases to prove that the asynchronous circuit design methodology is feasible for both academic training and a prototype for verification.

碩士
國立臺灣大學
電子工程學研究所
107
Asynchronous circuits have distinct advantages over their synchronous counterparts, e.g., in their security against side-channel attacks, resilience against process variation, robustness against environmental fluctuation, low electromagnetic interference, and ease of design composition, among other benefits. Among various asynchronous delay models, quasi-delay insensitive (QDI) circuits with dual-rail encoding are promising due to its relaxed timing assumption and timing robustness. Furthermore, dual-rail precharge logic (DRPL) has been considered to be a practical countermeasure method to mitigate information leakage in power consumption by dual-rail encoding. On the other hand, FPGA implementation becomes an essential building block in system-on-a-chip (SoC) design due to its reconfigurability. Compared to ASIC implementation, the reconfigurability of FPGAs also provides a convenient procedure for design adjustment against side-channel attacks through physical measurements. However, mapping QDI circuits on FPGA is challenging due to limited resources. In this thesis, we propose the effective implementation of asynchronous basic units on synchronous-based FPGA and show the design automation flow to synthesize more complex asynchronous design quickly. Besides, we propose the interface between synchronous and asynchronous domain for data transmission. Finally, to confirm the feasibility of our synthesis framework, we realize an Advanced Encryption Standard (AES) design and perform differential power analysis (DPA) to justify the security of asynchronous AES compared to its synchronous counterparts.

碩士
國立交通大學
電子工程系所
93
The interface circuit designs using handshake protocols and asynchronous first-in-first-out (FIFO) for globally-asynchronous locally-synchronous (GALS) systems are realized and apply to the Fast Fourier Transform Architecture in this thesis. A new pausible clock controller, write-port and read-port in asynchronous wrappers are proposed and data items can be transferred safely through adjacent wrappers operating at different clock frequencies. To increase the efficiency of throughput at the sender’s module, the asynchronous FIFO is inserted between two adjacent modules. An asynchronous FIFO cell is proposed to reduce the complexity of the handshake circuits by using Muller C element with some modifications. It has the properties of being low power, low latency and reusable. The physical layouts for the FIFO sizes of four, eight and sixteen are implemented based on the TSMC 0.13um 1P8M CMOS technology. The GALS design combined with dual-supply systems is applied to the 16-point radix-22 single-path delay feedback FFT architecture. The architecture is divided into three wrappers and each wrapper has its own local clock frequency and supply voltage. The interfaces formed from wrappers are implemented by handshake circuits and asynchronous FIFO, which are modified with level converters. Simulation results in TSMC 0.13um technology shows that the 16-point GALS-based FFT architecture in dual supply voltages has 30% power savings and 25.5% latency reduction compared to the globally-synchronous one in single supply voltage. These techniques will be widely used in the future systems-on-a-chip (SOC) design.